74ACT11873
DUAL 4-BIT D-TYPE LATCH
WITH 3STATE OUTPUTS
SCAS096 FEBRUARY 1990 REVISED APRIL 1993
Copyright
1993, Texas Instruments Incorporated
1
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
Inputs Are TTL-Voltage Compatible
3-State Buffer-Type Outputs Drive Bus
Lines Directly
Bus-Structured Pinout
Flow-Through Architecture to Optimize
PCB Layout
Center-Pin V
CC
and GND Configurations to
Minimize High-Speed Switching Noise
EPIC
t
(Enhanced-Performance Implanted
CMOS) 1-
m
m Process
500-mA Typical Latch-Up Immunity at
125
C
Package Options Include Plastic Small-
Outline Packages and Standard Plastic
300-mil DIPs
description
These dual 4-bit registers feature 3-state outputs designed specifically for bus driving. This makes these
devices particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working
registers.
The dual 4-bit latch is transparent D-type. When the latch enable input (1C or 2C) is high, the (Q) outputs will
follow the data (D) inputs in true form, according to the function table. When the latch enable input is taken low,
the outputs will be latched. When CLR goes low, the Q outputs go low independently of enable C. The outputs
are in a high-impedance state when OC (output control) is at a high logic level.
The 74ACT11873 is characterized for operation from 40
C to 85
C.
OC
L
L
L
L
H
CLR
L
H
H
H
X
C
X
H
H
L
X
D
X
H
L
X
X
OUTPUT
Q
L
H
L
Qo
Z
INPUTS
FUNCTION TABLE
DW OR NT PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
1C
1Q1
1Q2
1Q3
1Q4
GND
GND
GND
GND
2Q1
2Q2
2Q3
2Q4
2C
1OC
1CLR
1D1
1D2
1D3
1D4
V
CC
V
CC
2D1
2D2
2D3
2D4
2CLR
2OC
EPIC is a trademark of Texas Instruments Incorporated.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
74ACT11873
DUAL 4-BIT D-TYPE LATCH
WITH 3STATE OUTPUTS
SCAS096 FEBRUARY 1990 REVISED APRIL 1993
2
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
logic symbol
logic diagram (positive logic)
each quad latch
This symbol is in accordance with ANSI/IEEE Std 91-1984
and IEC Publication 617-12.
2D4
2D3
2D2
2D1
2CLR
2CLK
2OE
1D4
1D3
1D2
1D1
1CLR
1CLK
1OE
17
18
19
20
16
14
15
20
21
22
23
27
1
28
2Q4
2Q3
2Q2
2Q1
1Q4
1Q3
1Q2
1Q1
13
12
11
10
5
4
3
2
EN
C1
R
1D
1D
R
C1
EN
Q4
Q3
Q2
Q1
D4
D3
D2
D1
CLR
CLK
OE
1D
C1
R
1D
C1
R
1D
C1
R
1D
C1
R
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
}
Supply voltage range, V
CC
0.5 V to 7 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, V
I
(see Note 1)
0.5 V to V
CC
+ 0.5 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output voltage range, V
O
(see Note 1)
0.5 V to V
CC
+ 0.5 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, I
IK
(V
I
< 0 or V
I
> V
CC
)
20 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output clamp current, I
OK
(V
O
< 0 or V
O
> V
CC
)
50 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous output current, I
O
(V
O
= 0 to V
CC
)
50 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous current through V
CC
or GND
200 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range
65
C to 150
C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
74ACT11873
DUAL 4-BIT D-TYPE LATCH
WITH 3STATE OUTPUTS
SCAS096 FEBRUARY 1990 REVISED APRIL 1993
3
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
recommended operating conditions
MIN
MAX
UNIT
VCC
Supply voltage
4.5
5.5
V
VIH
High-level input voltage
2
V
VIL
Low-level input voltage
0.8
V
VI
Input voltage
0
VCC
V
VO
Output voltage
0
VCC
V
IOH
High-level output current
24
mA
IOL
Low-level output current
24
mA
D
t/
D
v
Input transition rise or fall rate
0
10
ns/V
TA
Operating free-air temperature
40
85
C
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
TA = 25
C
MIN
MAX
UNIT
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX
MIN
MAX
UNIT
IOH = 50
m
A
4.5 V
4.4
4.4
IOH = 50
m
A
5.5 V
5.4
5.4
VOH
IOH = 24 mA
4.5 V
3.94
3.8
V
IOH = 24 mA
5.5 V
4.94
4.8
IOH = 75 mA
5.5 V
3.85
IOL = 50
m
A
4.5 V
0.1
0.1
IOL = 50
m
A
5.5 V
0.1
0.1
VOL
IOL = 24 mA
4.5 V
0.36
0.44
V
IOL = 24 mA
5.5 V
0.36
0.44
IOL = 75 mA
5.5 V
1.65
IOZ
VO = VCC or GND
5.5 V
0.5
5
m
A
II
VI = VCC or GND
5.5 V
0.1
1
m
A
ICC
VI = VCC or GND, IO = 0
5.5 V
8
80
m
A
D
I
One input at 3.4 V,
5 5 V
0 9
1
mA
D
ICC
,
Other inputs at GND or VCC
5.5 V
0.9
1
mA
Ci
VI = VCC or GND
5 V
4.5
pF
Co
VO = VCC or GND
5 V
13.5
pF
Not more than one output should be tested at a time, and the duration of the test should not exceed 10 ms.
This is the increase in supply current for each input that is at one of the specified TTL voltage levels rather than 0 V to VCC.
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (see Figure 1)
TA = 25
C
MIN
MAX
UNIT
MIN
MAX
MIN
MAX
UNIT
t
Pulse duration
CLR low
5
5
ns
tw
Pulse duration
C high
5
5
ns
t
Setup time before C
Data high
6
6
ns
tsu
Setup time before C
Data low
3
3
ns
th
Hold time after C
Data high
0
0
ns
th
Hold time after C
Data low
0
0
ns
74ACT11873
DUAL 4-BIT D-TYPE LATCH
WITH 3STATE OUTPUTS
SCAS096 FEBRUARY 1990 REVISED APRIL 1993
4
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (see Figure 1)
PARAMETER
FROM
TO
TA = 25
C
MIN
MAX
UNIT
PARAMETER
(INPUT)
(OUTPUT)
MIN
TYP
MAX
MIN
MAX
UNIT
tPLH
D
Q
4.4
7.2
8.8
4.4
10
ns
tPHL
D
Q
3
6.6
9.1
3
10.2
ns
tPLH
C
Q
4.7
8.1
10
4.7
11.3
ns
tPHL
C
Q
5.2
8.9
10.9
5.2
12.3
ns
tPHL
CLR
Q
2.9
6.5
9
2.9
10
ns
tPZH
OC
Q
1.9
4.9
7.1
1.9
8
ns
tPZL
OC
Q
2.7
6.4
9.1
2.7
10.3
ns
tPHZ
OC
Q
5.7
8
9.5
5.7
10.2
ns
tPLZ
OC
Q
5.2
7.8
9.1
5.2
9.8
ns
operating characteristics, V
CC
= 5 V, T
A
= 25
C
PARAMETER
TEST CONDITIONS
TYP
UNIT
C d
Power dissipation capacitance per latch
Outputs enabled
CL = 50 pF f = 1 MHz
40
pF
Cpd Power dissipation capacitance per latch
Outputs disabled
CL = 50 pF, f = 1 MHz
7
pF
74ACT11873
DUAL 4-BIT D-TYPE LATCH
WITH 3STATE OUTPUTS
SCAS096 FEBRUARY 1990 REVISED APRIL 1993
5
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
From Output
Under Test
CL = 50 pF
(see Note A)
LOAD CIRCUIT
S1
2 X VCC
Open
GND
500
500
TEST
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
S1
Open
2 x VCC
GND
1.5 V
1.5 V
1.5 V
3 V
3 V
0 V
0 V
th
tsu
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
Data
Input
3 V
0
3 V
0
1.5 V
1.5 V
1.5 V
1.5 V
tw
High-Level
Input
Low-Level
Input
tPLH
tPHL
tPHL
tPLH
VOH
VOH
VOL
VOL
1.5 V
1.5 V
3 V
0
50%
50%
Input
(see Note B)
Out-of-Phase
Output
In-Phase
Output
Output
Control
(Low-Level
Enabling)
Output
Waveform 1
S1 at 2 x VCC
(see Note C)
Output
Waveform 2
S1 at GND
(see Note C)
VOL
VOH
tPZL
tPZH
tPLZ
tPHZ
1.5 V
1.5 V
0
50%
20%
50%
80%
ENABLE AND DISABLE TIMES
VOLTAGE WAVEFORMS
3 V
Timing Input
(see Note B)
50%
50%
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VCC
0 V
NOTES: A. CL includes probe and jig capacitance.
B. All input pulses are supplied by generators having the following characteristics: PRR
10 MHz, ZO = 50
, tr
2.5 ns, tf
2.5 ns.
C. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
D. The outputs are measured one at a time with one transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
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accordance with TI's standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
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Copyright
1998, Texas Instruments Incorporated
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