74ACT11181
ARITHMETIC LOGIC UNIT/FUNCTION GENERATOR
SCAS086 D3200, OCTOBER 1989 REVISED APRIL 1993
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
Copyright
1993, Texas Instruments Incorporated
21
Inputs Are TTL-Voltage Compatible
New Flow-Through Architecture Optimizes
PCB Layout
Center-Pin V
CC
and GND Configurations
Minimize High-Speed Switching Noise
EPIC
t
(Enhanced-Performance Implanted
CMOS) 1-
m
m Process
500-mA Typical Latch-Up Immunity at 125
C
Full Look Ahead for High-Speed Operations
on Long Words
Arithmetic Operating Modes:
Addition
Subtraction
Shift Operand A One Position
Magnitude Comparison
Plus Twelve Other Arithmetic
Operations
Logic Function Modes:
Exclusive-OR
Comparator
AND, NAND, OR, NOR
logic symbol
4
19
25
20
26
23
27
24
28
1
2
15
16
17
18
CI
P
Q
Q
P
P
Q
F3
F2
F1
Cn+4
A = B
G
P
Q
P
6(P = Q)
31
0
M
4
0
3
11
B3
A3
B2
A2
B1
A1
B0
A0
M
S3
S2
S1
S0
ALU
10
5
12
14
13
Cn
(0 ... 15) CP
(0 ... 15) CG
(0 ... 15) CO
F0
[1]
[2]
[4]
[8]
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
C
n
M
A = B
F0
F1
GND
GND
GND
GND
F2
F3
P
G
C
n + 4
A0
A1
A2
A3
B0
B1
V
CC
V
CC
B2
B3
S0
S1
S2
S3
DW PACKAGE
(TOP VIEW)
EPIC is a trademark of Texas Instruments Incorporated.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
74ACT11181
ARITHMETIC LOGIC UNIT/FUNCTION GENERATOR
SCAS086 D3200, OCTOBER 1989 REVISED APRIL 1993
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
22
description
The 74ACT11181 is an arithmetic logic unit (ALU)/function generator that has a complexity of 75 equivalent
gates on a monolithic chip. These circuits perform 16 binary arithmetic operations on two 4-bit words as shown
in Tables 1 and 2. These operations are selected by the four function-select lines (S0, S1, S2, S3) and include
addition, subtraction, decrement, and straight transfer. When performing arithmetic manipulations, the internal
carries must be enabled by applying a low-level voltage to the mode control input (M). A full carry look-ahead
scheme is made available in these devices for fast, simultaneous carry generation by means of two cascade
outputs G and P for the four bits in the package. When used in conjunction with the 'ACT11882 full carry
look-ahead circuits, high-speed arithmetic operations can be performed. The method of cascading 'ACT11882
circuits with these ALUs to provide multilevel full-carry look-ahead operation is illustrated under signal
designations.
If high speed is not important, a ripple-carry input (C
n
) and a ripple-carry output (C
n + 4
) are available. However,
the ripple-carry delay has also been minimized so that arithmetic manipulations for small word lengths can be
performed without external circuitry.
The 74ACT11181 will accommodate active-high or active-low data if the pin designations are interpreted as
follows:
PACKAGE
PIN NUMBERS AND DESIGNATIONS
DW, JT, or NT
25
26
27
28
19
20
23
24
11
10
5
4
1
14
12
13
FK
4
5
6
7
26
27
2
3
18
17
12
11
8
2
19
20
Active-low data
(Table 1)
A3
A2
A1
A0
B3
B2
B1
B0
F3
F2
F1
F0
Cn
Cn+4
P
G
Active-high data
(Table 2)
A3
A2
A1
A0
B3
B2
B1
B0
F3
F2
F1
F0
Cn
Cn+4
X
Y
Subtraction is accomplished by 1's complement addition where the 1's complement of the subtrahend is
generated internally. The resultant output is A B 1, which requires an end-around or forced carry to provide
A B.
The 74ACT11181 can also be used as a comparator. The A = B output is internally decoded from the function
outputs (F0, F1, F2, F3) so that when two words of equal magnitude are applied at the A and B inputs, it will
assume a high level to indicate equality (A = B). When performing this comparison, the ALU must be in the
subtract mode with C
n
= H. The A = B output is open drain so that it can be wired-AND connected to give a
comparison for more than four bits. The carry output (C
n + 4
) can also be used to supply relative magnitude
information. Again, the ALU must be placed in the subtract mode by placing the function select inputs S3, S2,
S1, S0 at L, H, H, L, respectively.
INPUT C
OUTPUT C
4
ACTIVE-LOW DATA
ACTIVE-HIGH DATA
INPUT Cn
OUTPUT Cn+4
(FIGURE 1)
(FIGURE 2)
H
H
A
B
A
B
H
L
A < B
A > B
L
H
A > B
A < B
L
L
A
B
A
B
These circuits have been designed not only to incorporate all of the designer's requirements for arithmetic
operation but also to provide 16 possible functions of two Boolean variables without using external circuitry.
These logic functions are selected using the four function-select inputs (S0, S1, S2, S3) with the mode-control
input (M) at a high level to disable the internal carry. The 16 logic functions are detailed in Tables 1 and 2 and
include exclusive-OR, NAND, AND, NOR, and OR functions.
74ACT11181
ARITHMETIC LOGIC UNIT/FUNCTION GENERATOR
SCAS086 D3200, OCTOBER 1989 REVISED APRIL 1993
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
23
signal designations
In both Figures 1 and 2, the polarity indicators (
) indicate that the associated input or output data is active
low with respect to the function shown inside the symbol, and the symbols are the same in both figures. The
signal designations in Figure 1 agree with the indicated internal functions based on active-low data and should
be used with the logic functions and arithmetic operations shown in Table 1. The signal designations have been
changed in Figure 2 to accommodate the logic functions and arithmetic operations for the active-high data given
in Table 2. The 74ACT11181 and 'ACT11881 together with the 'ACT11882 can be used with the signal
designations of either Figure 1 or Figure 2.
1
2
6(P = Q)
11
10
5
4
14
3
13
12
A = B
Cn + 4
F0
F1
F2
F3
18
17
16
15
2
1
28
24
27
23
26
20
25
19
S0
S1
S2
S3
M
Cn
A0
B0
A1
B1
A2
B2
A3
B3
P
Q
P
Q
P
Q
P
Q
[1]
[2]
[4]
[8]
0
4
M 0
31
C1
C1
31
0
M
4
0
[8]
[4]
[2]
[1]
Q
P
Q
P
Q
P
Q
P
B3
A3
B2
A2
B1
A1
B0
A0
Cn
M
S3
S2
S1
S0
19
25
20
26
23
27
24
28
1
2
15
16
17
18
F3
F2
F1
F0
Cn + 4
A = B
12
13
3
14
4
5
10
11
(0 . . . 15) )CO
6(P = Q)
(0 . . . 15) )CG
(0 . . . 15) )CP
(0 . . . 15) )CP
(0 . . . 15) )CG
(0 . . . 15) )CO
Cn
3
ALU
ALU
P
G
X
Y
P0
28
27
26
25
24
23
20
19
18
17
16
15
14
13
CPG
CPG
C1
CP0
CG0
CP1
CG1
CP2
CG2
CP3
CG3
CP4
CG4
CP5
CG5
CP6
CG6
CP7
CG7
C1
CP0
CG0
CP1
CG1
CP2
CG2
CP3
CG3
CP4
CG4
CP5
CG5
CP6
CG6
CP7
CG7
C01
C03
C05
C07
4
5
10
11
Cn + 8
Cn + 6
Cn + 24
Cn + 32
Cn
3
X0 1
2
28
27
26
25
24
23
20
19
18
17
16
15
14
13
C01
C03
C05
C07
4
5
10
11
Cn + 8
Cn + 16
Cn + 24
Cn + 32
(use with Table 1)
(use with Table 2)
G0
P1
G1
P2
G2
P3
G3
P4
G4
P5
G5
P6
G6
P7
G7
Y0
X1
Y1
X2
Y2
X3
Y3
X4
Y4
X5
Y5
X6
Y6
X7
Y7
74ACT11181
74ACT11181
'ACT11882
'ACT11882
Figure 1
Figure 2
74ACT11181
ARITHMETIC LOGIC UNIT/FUNCTION GENERATOR
SCAS086 D3200, OCTOBER 1989 REVISED APRIL 1993
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
24
Table 1
SELECTION
ACTIVE-LOW DATA
SELECTION
M = H
M = L; ARITHMETIC OPERATIONS
S3
S2
S1
S0
LOGIC
FUNCTIONS
Cn = L
(no carry)
Cn = H
(with carry)
L
L
L
L
F = A
F = A MINUS 1
F = A
L
L
L
H
F = AB
F = AB MINUS 1
F = AB
L
L
H
L
F = A + B
F = AB MINUS 1
F = AB
L
L
H
H
F = 1
F = MINUS 1 (2's COMP)
F = ZERO
L
H
L
L
F = A + B
F = A PLUS (A + B)
F = A PLUS (A + B) PLUS 1
L
H
L
H
F = B
F = AB PLUS (A + B)
F = AB PLUS (A + B) PLUS 1
L
H
H
L
F = A
B
F = A MINUS B MINUS 1
F = A MINUS B
L
H
H
H
F = A
+
B
F = A + B
F = (A + B) PLUS 1
H
L
L
L
F = AB
F = A PLUS (A + B)
F = A PLUS (A + B) PLUS 1
H
L
L
H
F = A
B
F = A PLUS B
F = A PLUS B PLUS 1
H
L
H
L
F = B
F = AB PLUS (A + B)
F = AB PLUS (A + B) PLUS 1
H
L
H
H
F = A + B
F = (A + B)
F = (A + B) PLUS 1
H
H
L
L
F = 0
F = A PLUS A
{
F = A PLUS A PLUS 1
H
H
L
H
F = AB
F = AB PLUS A
F = AB PLUS A PLUS 1
H
H
H
L
F = AB
F = AB PLUS A
F = AB PLUS A PLUS 1
H
H
H
H
F = A
F = A
F = A PLUS 1
Table 2
SELECTION
ACTIVE-HIGH DATA
SELECTION
M = H
M = L; ARITHMETIC OPERATIONS
S3
S2
S1
S0
M H
LOGIC
FUNCTIONS
Cn = H
(no carry)
Cn = L
(with carry)
L
L
L
L
F = A
F = A
F = A PLUS 1
L
L
L
H
F = A + B
F = A + B
F = (A + B) PLUS 1
L
L
H
L
F = AB
F = A + B
F = (A + B) PLUS 1
L
L
H
H
F = 0
F = MINUS 1 (2's COMP)
F = ZERO
L
H
L
L
F = AB
F = A PLUS AB
F = A PLUS AB PLUS 1
L
H
L
H
F = B
F = (A + B) PLUS AB
F = (A + B) PLUS AB PLUS 1
L
H
H
L
F = A
B
F = A MINUS B MINUS 1
F = A MINUS B
L
H
H
H
F = AB
F = AB MINUS 1
F = AB
H
L
L
L
F = A + B
F = A PLUS AB
F = A PLUS AB PLUS 1
H
L
L
H
F = A
B
F = A PLUS B
F = A PLUS B PLUS 1
H
L
H
L
F = B
F = (A + B) PLUS AB
F = (A + B) PLUS AB PLUS 1
H
L
H
H
F = AB
F = AB MINUS 1
F = AB
H
H
L
L
F = 1
F = A PLUS A
{
F = A PLUS A PLUS 1
H
H
L
H
F = A + B
F = (A + B) PLUS A
F = (A + B) PLUS A PLUS 1
H
H
H
L
F = A + B
F = (A + B) PLUS A
F = (A + B) PLUS A PLUS 1
H
H
H
H
F = A
F = A MINUS 1
F = A
Each bit is shifted to the next more significant position.
74ACT11181
ARITHMETIC LOGIC UNIT/FUNCTION GENERATOR
SCAS086 D3200, OCTOBER 1989 REVISED APRIL 1993
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
25
logic diagram (positive logic)
15
16
17
18
19
B3
25
A3
20
B2
26
A2
23
B1
27
A1
24
B0
28
A0
2
M
1
Cn
13
G
14
Cn + 4
12
P
11
F3
10
F2
3
A = B
5
F1
4
F0
S3
S2
S1
S0
74ACT11181
ARITHMETIC LOGIC UNIT/FUNCTION GENERATOR
SCAS086 D3200, OCTOBER 1989 REVISED APRIL 1993
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
26
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
CC
0.5 V to 7 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, V
I
(see Note 1)
0.5 V to V
CC
+ 0.5 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output voltage range, V
O
(see Note 1)
0.5 V to V
CC
+ 0.5 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, I
IK
(V
I
< 0 or V
I
> V
CC
)
20 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output clamp current, I
OK
(V
O
< 0 or V
O
> V
CC
)
50 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous output current, I
O
(V
O
= 0 to V
CC
)
50 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous current through V
CC
or GND
200 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range
65
C to 150
C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
recommended operating conditions
MIN
MAX
UNIT
VCC
Supply voltage
4.5
5.5
V
VIH
High-level input voltage
2
V
VIL
Low-level input voltage
0.8
V
VI
Input voltage
0
VCC
V
VO
Output voltage
0
VCC
V
IOH
High-level output current
All outputs except A = B
24
mA
IOL
Low-level output current
24
mA
D
t /
D
v
Input transition rise or fall rate
0
10
ns/ V
TA
Operating free-air temperature
40
85
C
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
TA = 25
C
MIN
MAX
UNIT
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX
MIN
MAX
UNIT
IOH = 50
m
A
4.5 V
4.4
4.4
IOH = 50
m
A
5.5 V
5.4
5.4
V
Any output
IOH = 24 mA
4.5 V
3.94
3.8
V
VOH
y
except A = B
IOH = 24 mA
5.5 V
4.94
4.8
V
IOH = 50 mA
5.5 V
IOH = 75 mA
5.5 V
3.85
IOH
A = B
VCC = 5.5 V,
VO = VCC
5.5 V
0.5
5
m
A
IOL = 50
m
A
4.5 V
0.1
0.1
IOL = 50
m
A
5.5 V
0.1
0.1
V
IOL = 24 mA
4.5 V
0.36
0.44
V
VOL
IOL = 24 mA
5.5 V
0.36
0.44
V
IOL = 50 mA
5.5 V
IOL = 75 mA
5.5 V
1.65
II
VI = VCC or GND
5.5 V
0.1
1
m
A
ICC
VI = VCC or GND, IO = 0
5.5 V
8
80
m
A
ICC
One input at 3.4 V, Other inputs at GND or VCC
5.5 V
0.9
1
mA
Ci
VI = VCC or GND
5 V
4.5
pF
Co
A = B
VO = VCC or GND
5 V
11
pF
Not more than one output should be tested at a time, and the duration of the test should not exceed 10 ms.
This is the increase in supply current for each input that is at one of the specified TTL voltage levels rather than 0 V or VCC.
74ACT11181
ARITHMETIC LOGIC UNIT/FUNCTION GENERATOR
SCAS086 D3200, OCTOBER 1989 REVISED APRIL 1993
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
27
switching characteristics over recommended operating free-air temperature range,
V
CC
= 5 V
0.5 V (unless otherwise noted) (see Figure 3)
addition mode; M = S1 = S2 = 0 V, S0 = S3 = 4.5 V
PARAMETER
FROM
TO
TA = 25
C
MIN
MAX
UNIT
PARAMETER
(INPUT)
(OUTPUT)
MIN
TYP
MAX
MIN
MAX
UNIT
tPLH
C
C
4
1.5
10.7
17.5
1.5
18.6
ns
tPHL
Cn
Cn + 4
1.5
11.3
16.2
1.5
18.3
ns
tPLH
An A
C
4
1.5
12.7
20.3
1.5
21.8
ns
tPHL
Any A
Cn + 4
1.5
14
19.7
1.5
22
ns
tPLH
An B
C
4
1.5
13.5
21.6
1.5
23.2
ns
tPHL
Any B
Cn + 4
1.5
13.6
19.7
1.5
22
ns
tPLH
C
Any F
1.5
11.2
17.1
1.5
18.7
ns
tPHL
Cn
Any F
1.5
9.9
15.9
1.5
17.4
ns
tPLH
An A
G
1.5
12.8
20.9
1.5
23.3
ns
tPHL
Any A
G
1.5
12.7
17.8
1.5
20.9
ns
tPLH
An B
G
1.5
12.7
20.6
1.5
22.1
ns
tPHL
Any B
G
1.5
14.3
19.2
1.5
21.3
ns
tPLH
An A
P
1.5
11.4
18.4
1.5
19.6
ns
tPHL
Any A
P
1.5
9.6
16.6
1.5
17.4
ns
tPLH
An B
P
1.5
11.3
18.2
1.5
19.3
ns
tPHL
Any B
P
1.5
10.6
15.6
1.5
16.6
ns
tPLH
Ai
Fi
1.5
11.8
17.7
1.5
19.5
ns
tPHL
Ai
Fi
1.5
11
17.7
1.5
18.7
ns
tPLH
Bi
Fi
1.5
11.6
17.3
1.5
19.1
ns
tPHL
Bi
Fi
1.5
12
19.4
1.5
20.6
ns
tPLH
Ai
An F e cept Fi
1.5
13
18.9
1.5
21
ns
tPHL
Ai
Any F except Fi
1.5
12.4
18.8
1.5
20.2
ns
tPLH
An B
An F e cept Fi
1.5
13.1
18.7
1.5
21
ns
tPHL
Any B
Any F except Fi
1.5
13.5
19.8
1.5
21.3
ns
mode switching; S1 = S2 = 0 V, S0 = S3 = 4.5 V
PARAMETER
FROM
TO
TA = 25
C
MIN
MAX
UNIT
PARAMETER
(INPUT)
(OUTPUT)
MIN
TYP
MAX
MIN
MAX
UNIT
tPLH
M
An F
1.5
9.5
15
1.5
16.3
ns
tPHL
M
Any F
1.5
10.6
16.4
1.5
17.5
ns
tPLH
M
A = B
1.5
15.7
19.3
1.5
20.1
ns
tPHL
M
A = B
1.5
14
18.7
1.5
21.8
ns
74ACT11181
ARITHMETIC LOGIC UNIT/FUNCTION GENERATOR
SCAS086 D3200, OCTOBER 1989 REVISED APRIL 1993
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
28
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (see Figure 3)
subtraction mode; M = S0 = S3 = 0 V, S1 = S2 = 4.5 V
PARAMETER
FROM
TO
TA = 25
C
MIN
MAX
UNIT
PARAMETER
(INPUT)
(OUTPUT)
MIN
TYP
MAX
MIN
MAX
UNIT
tPLH
C
C
4
1.5
10.7
17.5
1.5
18.6
ns
tPHL
Cn
Cn + 4
1.5
11.3
16.2
1.5
18.3
ns
tPLH
Any A
C
4
1.5
12.7
20.3
1.5
21.8
ns
tPHL
Any A
Cn + 4
1.5
13.5
19.7
1.5
20.8
ns
tPLH
Any B
C
4
1.5
13.8
21.1
1.5
22.7
ns
tPHL
Any B
Cn + 4
1.5
14.8
20.7
1.5
23
ns
tPLH
C
Any F
1.5
11.2
17.1
1.5
18.7
ns
tPHL
Cn
Any F
1.5
9.9
15.9
1.5
17.4
ns
tPLH
Any A
G
1.5
12.8
20.8
1.5
22.2
ns
tPHL
Any A
G
1.5
12.7
18.4
1.5
20.7
ns
tPLH
Any B
G
1.5
13.2
20.8
1.5
21.6
ns
tPHL
Any B
G
1.5
11.5
18.5
1.5
19.6
ns
tPLH
Any A
P
1.5
9.6
14.6
1.5
15.5
ns
tPHL
Any A
P
1.5
10.8
18.8
1.5
20
ns
tPLH
Any B
P
1.5
10.4
15.1
1.5
16.3
ns
tPHL
Any B
P
1.5
11.9
17.8
1.5
19.6
ns
tPLH
Ai
Fi
1.5
11.2
17.2
1.5
19.9
ns
tPHL
Ai
Fi
1.5
12.1
17.8
1.5
19.5
ns
tPLH
Bi
Fi
1.5
12
18.6
1.5
20.7
ns
tPHL
Bi
Fi
1.5
13.2
19
1.5
21.1
ns
tPLH
Any A
Any F
1.5
12.6
18.9
1.5
20.3
ns
tPHL
Any A
Any F
1.5
13.6
19.4
1.5
21.5
ns
tPLH
Any B
An F
1.5
13.1
18.7
1.5
20.4
ns
tPHL
Any B
Any F
1.5
18
21.6
1.5
23.7
ns
tPLH
Any A
A = B
1.5
16
21.5
1.5
24.6
ns
tPHL
Any A
A = B
1.5
18.5
22.7
1.5
23.9
ns
tPLH
Any B
A = B
1.5
18.5
22.7
1.5
23.9
ns
tPHL
Any B
A = B
1.5
16.5
22
1.5
25.4
ns
74ACT11181
ARITHMETIC LOGIC UNIT/FUNCTION GENERATOR
SCAS086 D3200, OCTOBER 1989 REVISED APRIL 1993
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
29
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (see Figure 3)
logic and arithmetic modes
PARAMETER
FROM
TO
TEST CONDITIONS
TA = 25
C
MIN
MAX
UNIT
PARAMETER
(INPUT)
(OUTPUT)
TEST CONDITIONS
MIN
TYP
MAX
MIN
MAX
UNIT
tPLH
Any A
Any F
M = 4 5 V (logic mode)
1.5
10
15.9
1.5
18.3
ns
tPHL
Any A
Any F
M = 4.5 V (logic mode)
1.5
11
17.4
1.5
19.6
ns
tPLH
Bi
Fi
M = 4 5 V (logic mode)
1.5
12.2
18
1.5
19.6
ns
tPHL
Bi
Fi
M = 4.5 V (logic mode)
1.5
11.5
18.3
1.5
19.6
ns
tPLH
Any S
Any F
M
0 V (arithmetic mode)
1.5
12.1
18.3
1.5
20.1
ns
tPHL
Any S
Any F
M = 0 V (arithmetic mode)
1.5
10.6
15.8
1.5
17.4
ns
tPLH
Any S
A = B
M
0 V (arithmetic mode)
1.5
18.7
22.1
1.5
23.4
ns
tPHL
Any S
A = B
M = 0 V (arithmetic mode)
1.5
17.2
22.2
1.5
25.4
ns
tPLH
Any S
C
4
M = 4 5 V (logic mode)
1.5
13.9
21.8
1.5
23.6
ns
tPHL
Any S
Cn + 4
M = 4.5 V (logic mode)
1.5
15.3
22.3
1.5
25.2
ns
tPLH
Any S
G
M
0 V (arithmetic mode)
1.5
12.7
20.5
1.5
22.3
ns
tPHL
Any S
G
M = 0 V (arithmetic mode)
1.5
13.5
19.7
1.5
22
ns
tPLH
Any S
P
M = 4 5 V (logic mode)
1.5
12.4
18.6
1.5
20.5
ns
tPHL
Any S
P
M = 4.5 V (logic mode)
1.5
11.7
17.7
1.5
18
ns
operating characteristics, V
CC
= 5 V, T
A
= 25
C
PARAMETER
TEST CONDITIONS
TYP
UNIT
Cpd Power dissipation capacitance
CL = 50 pF, f = 1 MHz
119
pF
74ACT11181
ARITHMETIC LOGIC UNIT/FUNCTION GENERATOR
SCAS086 D3200, OCTOBER 1989 REVISED APRIL 1993
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
210
PARAMETER MEASUREMENT INFORMATION
ADDITION MODE TEST TABLE
FUNCTION INPUTS: M = S1 = S2 = 0 V, S0 = S2 = 4.5 V
PARAMETER
INPUT
UNDER
OTHER INPUT
SAME BIT
OTHER DATA INPUTS
OUTPUT
UNDER
OUTPUT
WAVEFORM
PARAMETER
UNDER
TEST
APPLY
4.5 V
APPLY
GND
APPLY
4.5 V
APPLY
GND
UNDER
TEST
WAVEFORM
(See Figure 3)
tPLH
Ai
Bi
None
Remaining
C
Fi
In Phase
tPHL
Ai
Bi
None
g
A and B
Cn
Fi
In-Phase
tPLH
Bi
Ai
None
Remaining
C
Fi
In Phase
tPHL
Bi
Ai
None
Remaining
A and B
Cn
Fi
In-Phase
tPLH
Ai
Bi
None
None
Remaining
P
In Phase
tPHL
Ai
Bi
None
None
Remaining
A and B, Cn
P
In-Phase
tPLH
Bi
Ai
None
None
Remaining
P
In Phase
tPHL
Bi
Ai
None
None
Remaining
A and B, Cn
P
In-Phase
tPHL
Ai
None
Bi
Remaining
Remaining
G
In Phase
tPHL
Ai
None
Bi
Remaining
B
Remaining
A, Cn
G
In-Phase
tPLH
Bi
None
Ai
Remaining
Remaining
G
In Phase
tPHL
Bi
None
Ai
Remaining
B
Remaining
A, Cn
G
In-Phase
tPLH
C
None
None
All
All
Any F
In Phase
tPHL
Cn
None
None
All
A
All
B
Any F
or Cn + 4
In-Phase
tPLH
Ai
None
Bi
Remaining
Remaining
C
4
Out of Phase
tPHL
Ai
None
Bi
Remaining
B
Remaining
A, Cn
Cn + 4
Out-of-Phase
tPLH
Bi
None
Ai
Remaining
Remaining
C
4
Out of Phase
tPHL
Bi
None
Ai
Remaining
B
Remaining
A, Cn
Cn + 4
Out-of-Phase
MODE SWITCHING TEST TABLE
FUNCTION INPUTS: S1 = S2 = 0 V, S0 = S3 = 4.5 V
PARAMETER
INPUT
UNDER
OTHER INPUT
SAME BIT
OTHER DATA INPUTS
OUTPUT
UNDER
OUTPUT
WAVEFORM
PARAMETER
UNDER
TEST
APPLY
4.5 V
APPLY
GND
APPLY
4.5 V
APPLY
GND
UNDER
TEST
WAVEFORM
(See Figure 3)
tPLH
M
Remaining
B2 A2 C
Any F
In Phase
tPHL
M
--
--
g
A and B
B2, A2, Cn
Any F
In-Phase
tPLH
M
Remaining
B1 A1 C
A = B
In Phase
tPHL
M
--
--
Remaining
A and B
B1, A1, Cn
A = B
In-Phase
74ACT11181
ARITHMETIC LOGIC UNIT/FUNCTION GENERATOR
SCAS086 D3200, OCTOBER 1989 REVISED APRIL 1993
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
211
PARAMETER MEASUREMENT INFORMATION
SUBTRACTION MODE TEST TABLE
FUNCTION INPUTS: S1 = S2 = 4.5 V, S0 = S3 = M = 0 V
PARAMETER
INPUT
UNDER
OTHER INPUT
SAME BIT
OTHER DATA INPUTS
OUTPUT
UNDER
OUTPUT
WAVEFORM
PARAMETER
UNDER
TEST
APPLY
4.5 V
APPLY
GND
APPLY
4.5 V
APPLY
GND
UNDER
TEST
WAVEFORM
(See Figure 3)
tPLH
Ai
None
Bi
Remaining
Remaining
Fi
In Phase
tPHL
Ai
None
Bi
g
A
g
B, Cn
Fi
In-Phase
tPLH
Bi
Ai
None
Remaining
Remaining
Fi
Out of Phase
tPHL
Bi
Ai
None
Remaining
A
g
B, Cn
Fi
Out-of-Phase
tPLH
Ai
None
Bi
None
Remaining
P
In Phase
tPHL
Ai
None
Bi
None
Remaining
A and B, Cn
P
In-Phase
tPLH
Bi
Ai
None
None
Remaining
P
Out of Phase
tPHL
Bi
Ai
None
None
Remaining
A and B, Cn
P
Out-of-Phase
tPHL
Ai
Bi
None
None
Remaining
G
In Phase
tPHL
Ai
Bi
None
None
Remaining
A and B, Cn
G
In-Phase
tPLH
Bi
None
Ai
None
Remaining
G
Out of Phase
tPHL
Bi
None
Ai
None
Remaining
A and B, Cn
G
Out-of-Phase
tPLH
Ai
None
Bi
Remaining
Remaining
A = B
In Phase
tPHL
Ai
None
Bi
Remaining
A
Remaining
B, Cn
A = B
In-Phase
tPLH
Bi
Ai
None
Remaining
Remaining
A = B
Out of Phase
tPHL
Bi
Ai
None
Remaining
A
Remaining
B, Cn
A = B
Out-of-Phase
tPLH
C
None
None
All
None
Cn + 4
In Phase
tPHL
Cn
None
None
All
A and B
None
Cn + 4
or any F
In-Phase
tPLH
Ai
Bi
None
None
Remaining
C
4
Out of Phase
tPHL
Ai
Bi
None
None
Remaining
A and B, Cn
Cn + 4
Out-of-Phase
tPLH
Bi
None
Ai
None
Remaining
C
4
In Phase
tPHL
Bi
None
Ai
None
Remaining
A and B, Cn
Cn + 4
In-Phase
LOGIC MODE TEST TABLE
FUNCTION INPUTS: S1 = S2 = M = 4.5 V, S0 = S3 = 0 V
PARAMETER
INPUT
UNDER
OTHER INPUT
SAME BIT
OTHER DATA INPUTS
OUTPUT
UNDER
OUTPUT
WAVEFORM
PARAMETER
UNDER
TEST
APPLY
4.5 V
APPLY
GND
APPLY
4.5 V
APPLY
GND
UNDER
TEST
WAVEFORM
(See Figure 3)
tPLH
Ai
Bi
None
None
Remaining
Fi
Out of Phase
tPHL
Ai
Bi
None
None
g
A and B, Cn
Fi
Out-of-Phase
tPLH
Bi
Ai
None
None
Remaining
Fi
Out of Phase
tPHL
Bi
Ai
None
None
Remaining
A and B, Cn
Fi
Out-of-Phase
74ACT11181
ARITHMETIC LOGIC UNIT/FUNCTION GENERATOR
SCAS086 D3200, OCTOBER 1989 REVISED APRIL 1993
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
212
PARAMETER MEASUREMENT INFORMATION
From Output
Under Test
RL = 1 k
Test Point
VCC
LOAD CIRCUIT, TOTEM-POLE OUTPUTS
From Output
Under Test
CL = 50 pF
(see Note A)
500
CL = 50 pF
(see Note A)
LOAD CIRCUIT, OPEN-DRAIN OUTPUT
50% VCC
tPLH
tPHL
tPHL
tPLH
VOH
VOH
VOL
VOL
1.5 V
1.5 V
3 V
0 V
50% VCC
50% VCC
Input
(see Note B)
Out-of-Phase
Output
In-Phase
Output
50% VCC
VOLTAGE WAVEFORMS
NOTES: A. CL includes probe and jig capacitance.
B. Input pulses are supplied by generators having the following characteristics: PRR
10 MHz, ZO = 50
, tr = 3 ns, tf = 3 ns.
C. The outputs are measured one at a time with one input transition per measurement.
Figure 3. Load Circuits and Voltage Waveforms
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