78P2253
E4/STM-1/STS-3/OC-3
Transceiver
JUNE 2002
DESCRIPTION
The 78P2253 is a transceiver IC designed for
155.52Mbit/s (OC-3, STS-3 or STM-1) transmission
which can also be applied to 139.264Mbit/s (E4*)
rates. It is used at the interface to a 75
coaxial
cable using CMI coding or a fiber optic module.
Interface to digital framer circuits is accomplished via
a serial PECL or parallel CMOS interface.
The transmitter includes a PLL to multiply the
reference clock to the transmission frequency. The
receiver provides adaptive equalization for accurate
clock and data recovery. The 78P2253 is built in a
BiCMOS technology for high performance and low
power operation. It operates with a 3.3V or 5V power
supply and is packaged in a 64-pin TQFP.
FEATURES
139.264Mbit/s or 155.52Mbit/s interface for
CMI coded transmission using 75
coaxial
cable
Compliant with ITU-T G.703, G.825, G.958;
Telcordia TR-NWT-00253; and ANSI
T1.105.03-1994, T1.105.05-1994, T1.102-1993
Integrated Clock Recovery Unit (CRU)
Serial PECL Interface
Four and Eight bit Parallel CMOS Interfaces
PECL Interfaces for connection to Fiber
Optic Modules for SONET OC3 applications
Adaptive Equalization
Integrated Clock Multiplier PLL
Advanced BiCMOS Process
BLOCK DIAGRAM
Crystal
Oscillator
Clock
Generator
Binary
to CMI
Clock
Recovery
Adaptive
Equalizer
CMI to
Binary
Bias
XT
A
L
2
XT
A
L
1
CM
I/
EC
L
RF
O
LOS
ECLINN
ECLINP
CMIINN
CMIINP
ECLOUTN
ECLOUTP
CMIOUTN
CMIOUTP
CKIN
TXCK
TXCKP,N
TXDTP,N
RXDTP,N
RXCKP,N
L
L
BAC
K
RLBACK
LF
Signal
Detector
TXDT[7:0]
RXDT[7:0]
RXCK
8B
I
T
/
$B
I
T
E4
/
SO
NE
T
PAR
/
SER
HUB/
HO
S
T
78P2253
E4/STM-1/STS-3/OC-3
Transceiver
2
FUNCTIONAL DESCRIPTION
The 78P2253 contains all the necessary transmit
and receive circuitry for connection between
139.264Mbit/s or 155.52Mbit/s signals and digital
Framer/Deframer ICs.
OPERATING RATE
The 78P2253 has a variety of operating modes and
rates. They are summarized in the tables below.
More detailed descriptions can be found in the
sections that follow.
Standard
E4/
SONET
SONET
SONET
SONET
CMI/
ECL
ECL
ECL
ECL
Rate
(Mbit/s)
Reference
Frequency
Active I/O
OC-3 0 0
155.52
19.44
MHz
ECL
STS-3
STM-1
0 1
155.52
19.44
MHz
CMI
1
0
139.264
17.408
MHz
ECL
E4* 1
1
139.264
17.408
MHz
CMI
The digital interface of the 78P2253 can be either
Serial PECL, 4-bit Parallel CMOS or 8-bit Parallel
CMOS.
Mode
PAR/
SER
SER
SER
SER
8BIT/
$BIT
$BIT
$BIT
$BIT
Data pins Clock pins
Clock Frequency
(MHz)
Serial 0 X
TXDTP,N
RXDTP,N
TXCKP,N
RXCKP,N
155.52 (Sonet)
139.264 (E4*)
4-bit
Parallel
1 0
TXDT[3:0]
RXDT[3:0]
TXCK
RXCK
38.88 (Sonet)
34.816 (E4*)
8-bit
Parallel
1 1
TXDT[7:0]
RXDT[7:0]
TXCK
RXCK
19.44 (Sonet)
17.408 (E4*)
Transmit timing is derived from either the reference
clock (the crystal oscillator or CKIN), or the
recovered receive clock. LLBACK and RLBACK
control the local and remote loopback modes
respectively.
LLBACK RLBACK HUB/
HOST
HOST
HOST
HOST
Transmit Clock
derived from
0 0 1 Reference
1 0 1 Reference
X 1 1 Receiver
X X 0
Receiver
TRANSMISSION MEDIUM CHOICES
The CMI/
ECL pin selects one of two media for
transmission:
When the CMI/
ECL pin is high, the chip is in CMI
mode and a 75
coaxial cable is used as the
transmission medium. In this mode, the CMIOUTP
and CMIOUTN pins are active. They connect the
chip to the coaxial cable through a transformer and
matching resistors. In CMI mode the transmitter
shapes the transmit pulses to meet the appropriate
template and the adaptive equalizer corrects the
received signal for dispersive attenuation. In CMI
mode the data signal from the digital
Framer/Deframer IC is converted to CMI code by the
Binary to CMI encoder. The ECLOUTP and
ECLOUTN pins are inoperative and should be left
open.
When the CMI/
ECL pin is low, the chip is in ECL
mode and a fiber optics transceiver is used. The
output data signal from the pins ECLOUTP and
ECLOUTN have PECL levels. In this mode, the CMI
pins are inoperative and should be left open. The
CMI encoder/decoder is disabled.
TRANSMITTER OPERATION
The transmitter section generates an analog signal
for transmission through either a fiber optic module
or a transformer onto the coaxial cable.
When the PAR/
SER pin is low, the chip is in serial
mode. Serial data is input from the digital
Framer/Deframer IC to the 78P2253 on the TXDTP
and TXDTN pins at PECL levels. The data is timed
with the clock generated by the 78P2253 on the
TXCKP and TXCKN pins. In this mode the
8BIT/
$BIT pin is ignored.
When the PAR/
SER pin is high, the chip is in parallel
mode. Parallel data is input from the digital
Framer/Deframer IC to the 78P2253 on the
TXDT[7:0] pins. The input data is timed with the
transmit clock output from TXCK. When 8BIT/
$BIT is
high all eight bits of TXDT[7:0] are used and the
clock frequency at TXCK is one-eighth the standard
frequency. When 8BIT/
$BIT is low the lower four
bits, TXDT[3:0] are used and TXCK is one-fourth the
standard frequency.
Note that the first bit output from the ECL/CMI
interface (CMIOUTP,N for CMI mode and
ECLOUTP,N for ECL mode) is the most significant
bit on the parallel interface, TXDT7 in eight bit mode,
TXDT3 in four bit mode.
78P2253
E4/STM-1/STS-3/OC-3
Transceiver
3
TRANSMITTER OPERATION (continued)
The clock is generated by a phase-locked oscillator
(PLO). The PLO can be locked to a crystal oscillator
operating at one-eighth of the standard clock
frequency, 19.44MHz for OC-3, STS-3 and STM-1
and 17.408MHz for E4*. This is shown in Figure 1a.
An external clock signal at CKIN may also be
substituted for a crystal as the reference frequency
for the chip. In this mode, XTAL1 and XTAL2 must
be configured as shown in Figure 1b.
Note that the chip can be in either ECL or CMI mode
when using an external clock or a crystal for the
reference. In serial mode the reference clock is also
output from TXCK. In parallel mode, the parallel
transmit clock is output from TXCK.
The HUB/
HOST input changes the reference signal
for the clock generator. In the hub mode (HUB/
HOST
high), the transmit clock reference is derived from
either the crystal oscillator or CKIN. In host mode
(HUB/
HOST low), the transmit clock reference is
derived from the recovered receive clock.
Figure 1a: Using Crystal
XTAL1
XTAL2
CKIN
17.408 MHz (E4)
19.440 MHz (Sonet)
Figure 1b: Using External Clock
RECEIVER OPERATION
The receiver accepts serial, CMI coded data, at
155.52Mbit/s or 139.264Mbit/s from the CMI inputs
or NRZ coded data from the ECL inputs. In both
cases, the clock signal is recovered using a low jitter
PLL circuit.
In CMI mode, the inputs CMIINP and CMIINN
receive the input signal from a coaxial cable that is
transformer-coupled to the chip. The ECL pins
should be left open. In CMI mode, the received
signal is also equalized for dispersive cable
attenuation and decoded in the CMI to binary
decoder.
In ECL mode, the pins ECLINP and ECLINN receive
the input signal.
In serial mode, the received data is output on the
RXDTP and RXDTN pins and the recovered clock is
output on the RXCKP and RXCKN pins.
In parallel mode, the received data is converted to
parallel, eight bits if 8BIT/
$BIT is high and four if it is
low. The first bit received will arrive on the most
significant output pin, RXDT[7] in eight bit mode and
RXDT[3] in four bit mode. The recovered clock is
output on the RXCK pin.
The LOS pin goes high when the signal detector
detects a loss-of-signal condition.
LOOPBACK OPERATION
The 78P2253 is capable of performing signal
loopback in two ways:
The RLBACK pin selects the remote loopback
mode. In this mode, the received signal is "looped
back" and sent out of transmitter in place of the
transmit input signal.
The LLBACK pin selects the local loop-back mode,
and causes the receiver to use the transmitter output
signal as its input. Local loopback is disabled when
HUB/
HOST is low or RLBACK is high.
*E4 MODE OPERATION
For further information on the 78P2253's ability to
operate at E4 data rates, please contact TDK
Semiconductor.
78P2253
E4/STM-1/STS-3/OC-3
Transceiver
4
PIN DESCRIPTION
LEGEND
TYPE DESCRIPTION
TYPE DESCRIPTION
A
Analog Pin
PI
PECL Digital Input
CI
CMOS Digital Input
PO
PECL Digital Output
CO
CMOS Digital Output
S
Supply Pin
TRANSMIT PINS
NAME PIN
TYPE
DESCRIPTION
TXDTP
TXDTN
19
20
PI
Transmit Data Inputs - Serial Mode.
TXCKP
TXCKN
22
23
PO
Transmit Clock Output - Serial Mode.
TXDT[7:0] 11-18
CI
Transmit Data Inputs Parallel Mode. TXDT[7:4] are ignored in 4 bit
mode.
TXCK 10
CO
Reference Clock Output Serial mode.
Transmit Clock Output Parallel Mode.
CMIOUTP
CMIOUTN
60
59
A
Transmit Output in CMI mode.
No signal is output in ECL mode.
ECLOUTP
ECLOUTN
56
55
PO
Transmit Outputs for ECL mode.
No signal is output in CMI mode.
RECEIVE PINS
NAME PIN
TYPE
DESCRIPTION
CMIINP
CMIINN
50
49
A
Receive inputs in CMI mode.
Transformer coupled from the coaxial cable.
Ignored in ECL mode.
ECLINP
ECLINN
52
51
PI
Receiver inputs in ECL mode.
Ignored in CMI mode.
RXCKP
RXCKN
25
26
PO
Recovered Receive Clock Serial Mode.
RXCK
38
CO
Recovered Receive Clock Parallel Mode.
RXDTP
RXDTN
27
28
PO
Receive data Serial Mode.
RXDT[7:0] 30-37
CO
Receive data Parallel Mode. In 4 bit mode RXDT[3:0] are used and
RXDT[7:4] are pulled low.
78P2253
E4/STM-1/STS-3/OC-3
Transceiver
5
PIN DESCRIPTION
(continued)
REFERENCE CLOCK PINS
NAME PIN
TYPE
DESCRIPTION
XTAL1
XTAL2
5
6
A
Crystal Pins. Connect as in Figure 1a.
CKIN 9
CI
Reference clock input. The crystal oscillator connections should be
left open when used. Connect as in Figure 1b.
CONTROL AND STATUS PINS
NAME PIN
TYPE
DESCRIPTION
RLBACK
41
CI
Loopback receiver output to transmitter input.
LLBACK 42
CI
Loopback transmitter output to receiver input. Disabled when
HUB/
HOST is low or RLBACK is high.
HUB/
HOST
2 CI
In HUB mode (input high) the transmit reference clock is derived from
the CKIN pin or the crystal oscillator. In HOST mode (input low) the
transmit reference clock is derived from the recovered receive clock.
CMI/
ECL
1
CI
Selects CMI (input high) or ECL (input low) modes.
E4/
SONET
64 CI
When high, E4* (139.264 Mbit/s) operation is selected. When low,
STM-1/STS-3/OC-3 (155.52Mbit/s) operation is selected.
8BIT/
$BIT
63 CI
Selects 8 bit parallel data when high and 4 bit parallel mode when
low. In serial mode this pin is ignored.
PAR/
SER
62
CI
Selects parallel mode when high and serial mode when low.
LOS
39
CO
High during a loss-of-signal condition.
ANALOG PINS
NAME PIN
TYPE
DESCRIPTION
RFO
46
A
External reference resistor.
LF
44
A
PLL loop filter capacitor.
POWER SUPPLY PINS
It is recommended that all VCC pins be connected to a single power supply plane and all GND pins be connected
to a single ground plane.
NAME PIN
TYPE
DESCRIPTION
VCC
3, 8, 24,
40, 43,
53, 54,
57
S Power
Supply.
GND
4, 7, 21,
29, 45,
47, 48,
58, 61
S Ground.
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