5-Bit Programmable 2-/3-/4-Phase
Synchronous Buck Controller
Preliminary Technical Data
ADP3186
FEATURES
Selectable 2-, 3- or 4-phase operation at up to
1 MHz per phase
1% worst-case differential sensing error over temperature
Logic-level PWM outputs for interface to external
high-power drivers
Active current balancing between all output phases
Built-in power good/crowbar blanking supports on-the-fly
VID code changes
5-bit digitally programmable 0.8 V to 1.55 V output
Programmable short circuit protection with
programmable latch-off delay
APPLICATIONS
Desktop PC power supplies for
AMD Opteron
TM
processors
VRM modules
GENERAL DESCRIPTION
The ADP3186 is a highly efficient multiphase synchronous buck
switching regulator controller optimized for converting a 12 V
main supply into the core supply voltage required by high per-
formance AMD processors. It uses an internal 5-bit DAC to
read a voltage identification (VID) code directly from the
processor, which is used to set the output voltage between 0.8 V
and 1.55 V. It uses a multimode PWM architecture to drive the
logic-level outputs at a programmable switching frequency that
can be optimized for VR size and efficiency. The phase
relationship of the output signals can be programmed to
provide 2-, 3-, or 4-phase operation, allowing the construction
of up to four complementary buck switching stages.
The ADP3186 also includes programmable no-load offset and
slope functions to adjust the output voltage as a function of the
load current so that it is always optimally positioned for a system
transient. The ADP3186 also provides accurate and reliable
short circuit protection, adjustable current limiting, and a delayed
power good output that accommodates on-the-fly output voltage
changes requested by the CPU.
The ADP3186 is specified over the commercial temperature
range of 0C to 85C and is available in a 28-lead TSSOP package.
FUNCTIONAL BLOCK DIAGRAM
VCC
PRECISION
REFERENCE
SOFT
START
DELAY
UVLO
SHUTDOWN
& BIAS
OSCILLATOR
+
GND
ADP3186
19
EN
11
DELAY
12
ILIMIT
15
PWRGD
10
28
RT
13
RAMPADJ
14
PWM2
26
8
FB
PWM3
25
PWM4
24
SW1
23
CSSUM
17
CSCOMP
18
SW2
22
SW3
21
SW4
20
CSREF
16
PWM1
VID4
1
VID3
2
VID2
3
VID1
4
VID0
5
FBRTN
7
COMP
9
VID
DAC
+
DAC+300mV
+
DAC-300mV
+
+
CSREF
CSREF
2.1V
EN
CURRENT
LIMIT
CIRCUIT
CROWBAR
CURRENT
LIMIT
+
CMP
+
CMP
+
CMP
+
+
CMP
CURRENT
BALANCING
CIRCUIT
2 / 3 / 4-PHASE
DRIVER LOGIC
EN
SET
RESET
RESET
RESET
RESET
27
CROWBAR
6
Figure 1
Rev. PrB
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infringements of patents or other rights of third parties that may result from its use.
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Fax: 781.326.8703
2004 Analog Devices, Inc. All rights reserved.
ADP3186
Preliminary Technical Data
Rev. PrB | Page 2 of 24
TABLE OF CONTENTS
Specifications..................................................................................... 3
Test Circuits....................................................................................... 5
Absolute Maximum Ratings............................................................ 6
ESD Caution.................................................................................. 6
Pin Configuration and Function Description .............................. 7
Typical Performance Characteristics ............................................. 8
Theory of Operation ........................................................................ 9
Start-Up Sequence........................................................................ 9
Master Clock Frequency.............................................................. 9
Output Voltage Differential Sensing .......................................... 9
Output Current Sensing .............................................................. 9
Active Impedance Control Mode............................................. 10
Current Control Mode and Thermal Balance ....................... 10
Voltage Control Mode................................................................ 10
Soft Start ...................................................................................... 10
Current Limit, Short Circuit, and Latch-off Protection ........ 11
Dynamic VID.............................................................................. 11
Power Good Monitoring ........................................................... 12
Output Crowbar ......................................................................... 12
Output Enable and UVLO ........................................................ 12
Application Information................................................................ 14
Setting the Clock Frequency ..................................................... 14
Soft Start and Current Limit Latch-Off Delay Times........... 14
Inductor Selection ...................................................................... 14
Designing an Inductor............................................................... 15
Selecting a Standard Inductor .............................................. 15
Output Droop Resistance.......................................................... 15
Inductor DCR Temperature Correction ................................. 16
Output Offset .............................................................................. 16
C
OUT
Selection ............................................................................. 17
Power MOSFETs......................................................................... 17
Ramp Resistor Selection............................................................ 18
COMP Pin Ramp ....................................................................... 19
Current Limit SetPoint .............................................................. 19
Feedback Loop Compensation Design.................................... 19
C
IN
Selection and Input Current di/dt Reduction................. 20
Tuning Procedure for ADP3186............................................... 21
DC Loadline Setting .............................................................. 21
AC Loadline Setting............................................................... 21
Initial Transient Setting ......................................................... 22
Layout and Component Placement ......................................... 22
General Recommendations .................................................. 22
Power Circuitry Recommendations .................................... 23
Signal Circuitry Recommendations .................................... 23
Outline Dimensions ....................................................................... 24
Ordering Guide .......................................................................... 24
REVISION HISTORY
Revision PrA: Initial Version
Revision PrB: Updated Electrical Table and Absolute Maximum Ratings
Preliminary Technical Data
ADP3186
Rev. PrB| Page 3 of 24
SPECIFICATIONS
Table 1.
VCC = 12 V, FBRTN = GND, T
A
= 0C to 85C, unless otherwise noted.
1
Parameter Symbol
Conditions Min
Typ
Max
Unit
ERROR
AMPLIFIER
Output Voltage Range
2
V
COMP
0.5
3.5 V
Accuracy V
FB
0.8 V Output
Referenced to FBRTN,
CSSUM = CSCOMP, Figure 2
0.792
0.808 V
1.175 V Output
Referenced to FBRTN,
CSSUM = CSCOMP, Figure 2
1.163
1.187 V
1.55 V Output
Referenced to FBRTN,
CSSUM = CSCOMP, Figure 2
1.535
1.566 V
Line Regulation
V
FB
VCC = 10 V to 14 V
0.05
%
Input Bias Current
I
FB
-13
-15.5
-17
A
FBRTN Current
I
FBRTN
100
200
A
Output Current
I
O(ERR)
FB Forced to V
OUT
3%
500
A
Gain Bandwidth Product
GBW
(ERR)
COMP = FB
20
MHz
Slew Rate
C
COMP
= 10 pF
25
V/
s
VID INPUTS
Input Low Voltage
V
IL(VID)
0.8
V
Input High Voltage
V
IH(VID)
2.0
V
Input Current, Input Voltage Low
I
IL(VID)
VID(X) = 0 V
20
26
A
Pull-Up Resistance
R
VID
100 120
k
Internal
Pull-Up
Voltage
2.0 2.4 2.65
V
VID Transition Delay Time
2
VID code change to FB change
400
ns
No CPU Detection Turn-Off Delay
Time
2
VID code change to 11111 to PWM
going low
400
ns
OSCILLATOR
Frequency Range
2
f
OSC
0.25
4
MHz
Frequency Variation
f
PHASE
T
A
= 25C, R
T
= 250 k
, 4-phase
155 200 245 kHz
T
A
= 25C, R
T
= 115 k
, 4-phase
400
kHz
T
A
= 25C, R
T
= 75 k
, 4-phase
600
kHz
Output Voltage
V
RT
R
T
= 100 k
to GND
1.9 2.0 2.1 V
Timing Resistor Value
500
k
RAMPADJ Output Voltage
V
RAMPADJ
RAMPADJ FB
-50
+50
mV
RAMPADJ Input Current Range
I
RAMPADJ
0
50
A
CURRENT
SENSE
AMPLIFIER
Offset Voltage
V
OS(CSA)
CSSUM CSREF, Figure 3
-3
+3
mV
Input Bias Current
I
BIAS(CSSUM)
-50
+50 nA
Gain Bandwidth Product
GBW
(CSA)
10
MHz
Slew Rate
C
CSCOMP
= 10 pF
10
V/
s
Input Common-Mode Range
CSSUM and CSREF
0
2.7
V
Positioning Accuracy
V
FB
Figure
4
-77 -80 -83 mV
Output Voltage Range
0.05
2.7
V
Output Current
I
CSCOMP
500
A
CURRENT
BALANCE
CIRCUIT
Common-Mode Range
V
SW(X)CM
-600
+200 mV
Input Resistance
R
SW(X)
SW(X) = 0 V
20
30
40
k
Input Current
I
SW(X)
SW(X) = 0 V
4
7
10
A
Input Current Matching
I
SW(X)
SW(X) = 0 V
-5
+5
%
ADP3186
Preliminary Technical Data
Rev. PrB | Page 4 of 24
Parameter Symbol
Conditions Min
Typ
Max
Units
CURRENT
LIMIT
COMPARATOR
Output Voltage
Normal
Mode
V
ILIMIT(NM)
EN > 0.8 V, R
ILIMIT
= 250 k
2.9 3 3.1 V
In Shutdown Mode
V
ILIMIT(SD)
EN < 0.4 V, I
ILIMIT
= -100
A
400
mV
Output Current, Normal Mode
I
ILIMIT(NM)
EN > 0.8 V, R
ILIMIT
= 250 k
12
A
Maximum Output Current
2
60
A
Current Limit Threshold Voltage
V
CL
V
CSREF
V
CSCOMP
, R
ILIMIT
= 250 k
105 125 145 mV
Current Limite Setting Ratio
V
CL
/I
ILIMIT
10.4
mV/
A
DELAY Normal Mode Voltage
V
DELAY(NM)
R
DELAY
= 250 k
2.9 3 3.1 V
DELAY Overcurrent Threshold
V
DELAY(OC)
R
DELAY
= 250 k
1.7 1.8 1.9 V
Latch-Off Delay Time
t
DELAY
R
DELAY
= 250 k
, C
DELAY
= 12 nF
1.5
ms
SOFT
START
Output Current, Soft-Start Mode
I
DELAY(SS)
During startup, DELAY < 2.4 V
15
20
25
A
Soft-Start Delay Time
t
DELAY(SS)
R
DELAY
= 250 k
, C
DELAY
= 12 nF,
VID code = 011111
1
ms
ENABLE
INPUT
Input Low Voltage
V
IL(EN)
0.4
V
Input High Voltage
V
IH(EN)
0.8
V
Input Current, Input Voltage Low
I
IL(EN)
EN = 0 V
-1
+1
A
Input Current, Input Voltage High
I
IH(EN)
EN = 1.25 V
10
25
A
POWER
GOOD
COMPARATOR
Undervoltage Threshold
V
PWRGD(UV)
Relative to nominal DAC output
-180 -250 -300 mV
Overvoltage Threshold
V
PWRGD(OV)
Relative to nominal DAC output
90
150
200
mV
Output Low Voltage
V
OL(PWRGD)
I
PWRGD(SINK)
= 4 mA
225
400
mV
Power Good Delay Time
During Soft Start
2
R
DELAY
= 250 k
, C
DELAY
= 12 nF,
VID code = 011111
1
ms
VID Code Changing
100
250
s
VID Code Static
200
ns
Crowbar Trip Point
V
CROWBAR
Relative to nominal DAC output
90
150
200
mV
Crowbar Reset Point
Relative
to
FBRTN
450 550 650 mV
Crowbar Delay Time
t
CROWBAR
Overvoltage to PWM going low
VID Code Changing
100
250
s
VID Code Static
400
ns
PWM OUTPUTS
Output Low Voltage
V
OL(PWM)
I
PWM(SINK)
= -400
A
160 500 mV
Output High Voltage
V
OH(PWM)
I
PWM(SOURCE)
= 400
A
4.0 5
V
SUPPLY
DC Supply Current
5
10
mA
UVLO Threshold Voltage
V
UVLO
VCC
rising
6.5 6.9 7.3 V
UVLO
Hysteresis
0.7 0.9 1.1 V
1
All limits at temperature extremes are guaranteed via correlation using standard statistical quality control (SQC).
2
Guaranteed by design or bench characterization, not production tested.
Preliminary Technical Data
ADP3186
Rev. PrB| Page 5 of 24
TEST CIRCUITS
250k
12 V
1.25 V
1F
+
100nF
100nF
ADP3186
VID4
VID3
VID2
VID1
VID0
CROWBAR
FBRTN
FB
COMP
PWRGD
EN
DELAY
RT
RAMPADJ
VCC
PWM1
PWM2
PWM3
PWM4
SW1
SW2
SW3
SW4
GND
CSCOMP
CSSUM
CSREF
ILIMIT
1
2
3
28
27
26
4
8
10
12
14
5
6
7
21
24
23
22
9
11
17
18
19
13
15
16
20
25
5-BIT CODE
250k
20k
1k
4.7nF
Figure 2. Closed-Loop Output Voltage Accuracy
+
CSSUM
18
CSCOMP
17
28
VCC
CSREF
16
GND
19
39k
100nF
1k
1.0V
ADP3186
+
12V
VOS =
CSCOMP - 1V
40
Figure 3. Current Sense Amplifier V
OS
+
CSSUM
18
CSCOMP
17
28
VCC
CSREF
16
COMP
8
FB
9
GND
V
FB
= FB - V
VID
19
200k
10k
200k
1.0V
ADP3186
+
80mV
+
12V
Figure 4. Positioning Voltage
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