SMM105
Preliminary Information
1
(See Last Page)
SUMMIT Microelectronics, Inc. 2003
1717 Fox Drive San Jose CA 95131 Phone 408 436-9890 FAX 408 436-9897
www.summitmicro.com
2068 1.3 6/23/03
1
FEATURES & APPLICATIONS
Extremely accurate (0.1%) Active
DC Output Control (ADOC)
ADOC Automatically adjusts supply output
voltage level under all load conditions
Capable of margining supplies with trim inputs
using either positive or negative trim pin control
Wide Margin/ADOC range from 0.3V to VDD
Uses either an internal or external VREF
Operates from any intermediate bus supply
from 8V to 15V and from 2.7V to 5.5V
Programmable START and READY pins
Two programmable general purpose monitor
sensors UV and OV with FAULT Output Flag
General Purpose 1k EEPROM with Write Protect
I
2
C 2-wire serial bus for programming
configuration and monitoring status.
28 lead QFN package
Applications
In-system test and control of Point-of-Load
(POL) Power Supplies for Multi-voltage
Processors, DSPs and ASICs
Enterprise and edge routers, servers, Storage
Area Networks
INTRODUCTION
The SMM105 actively controls the output voltage level
of a DC/DC converter that uses a Trim or VADJ/FB pin
to adjust the output. An Active DC Output Control
(ADOC) feature is used during normal operation to
maintain extremely accurate settings of supply
voltages and, during system test, to control margining
of the supplies using I
2
C commands. Total accuracy
with a 0.1% external reference is 0.2%, and 0.5%
using the internal reference. The device can margin
supplies with either positive or negative trim pin control
within a range of 0.3V to VDD. The SMM105 supply
can be from 12V, 8V, 5V or 3.3V to as low as 2.7V to
accommodate any intermediate bus supply.
The voltage settings (margin high/low and nominal)
are programmed into nonvolatile memory through the
industry standard I
2
C 2-wire data bus. The I
2
C bus is
also used to enable margin high, margin low, ADOC or
normal operation. When margining, the SMM105 will
check the voltage output of the converter and make
adjustments to the trim pin via a feedback loop to bring
the voltage to the margin setting. A margining status
register is set to indicate that the system is ready for
test. The SMM105 ADOC will continue to monitor and
adjust the channel output at the specified level.
SIMPLIFIED APPLICATIONS DRAWING
VIN
TRIM
V+
V-
VM
FILT_CAP
TRIM _CAP
SMM105
ASIC
Internal or
External
Voltage
Reference
VREF_CNTL
GND
1.2 VIN
SDA
SCL
I
2
C
BUS
3.3/5Vin (2.7V to 5.5V)
RE
A
D
Y
READY
VD
D
12
V
I
N
12VIN (8V to 15V)
VDD_CAP
ST
A
R
T
POWER GOOD
A2
A1
A0
W P#
FAULT#
FAULT#
COM P1
COM P2
DC/DC
Converter
TRIM
VM
ON/OFF
UV
OV
GND
Figure 1 Applications Schematic using the SMM105 Controller to actively control the DC output level
(ADOC) of a DC/DC Converter as well as margin control. The SMM105 can operate over a wide supply range
Note: This is an applications example only. Some pins, components and values are not shown.
Single-Channel Supply Voltage Marginer and Active DC Output Controller
SMM105
Preliminary Information
Summit Microelectronics, Inc
2068 1.3 6/23/03
2
GENERAL DESCRIPTION
The SMM105 is capable of controlling and margining
the DC output voltage of LDOs or DC/DC converters
that use a trim/adjust pin and to automatically change
the level using a unique Active DC Output Control
(ADOC). The ADOC function is programmable over a
standard 2-wire I
2
C serial data interface and can be
used to set the nominal DC output voltage as well as
the margin high and low settings. The part actively
controls the programmed set levels to maintain tight
control over load variations and voltage drops at the
point of load. The margin range will vary depending on
the supply manufacturer and model but the normal
range is 10% adjustment around the nominal output
setting. However, the SMM105 has the capability to
margin from VREF_CNTL to VDD.
The user can set the desired voltage settings
(nominal, margin high and margin low) into the EE
memory array for the device. Then, volatile registers
are used to select one of these settings. The registers
are accessed over the I
2
C bus.
In normal operation, Active DC Output Control is set to
adjust the nominal output voltage of the converter.
Typical converters have
2% accuracy ratings for their
output voltage. Using the Active DC Output Control
feature of the SMM105 can increase the accuracy to
0.1%. This high accuracy control of the converter
output voltage is extremely important in low voltage
applications where deviations in power supply voltage
can result in lower system performance. Active DC
Output Control can also be used for margining a
supply during system test or may be turned off by de-
selecting the function in the Control Select Register.
The margin high and margin low voltage settings can
range from 0.3V to VDD around the converters'
nominal output voltage setting depending on the
specified margin range of the DC-DC converter.
When the SMM105 receives the command to margin,
the Active DC Output Control will adjust the supply to
the selected margin voltage. Once the supply has
reached its margined set point, the Ready bit in the
status register will set and the READY pin will go
active. If Active DC Control is disabled, a margined
supply can return to its nominal voltage by writing to
the margin command register.
In order to obtain maximum accuracy, the SMM105
requires an external voltage reference. An external
reference with 0.1% accuracy will enable an overall
0.2% accuracy for the device. A configuration option
also exists so that an internal voltage reference can be
used, but with less accuracy. Total accuracy using the
internal reference is 0.5%. The SMM105 can be
powered from either a 12V or 8V input via an internal
regulator or the VDD input (Figure 3).
The SMM105 has two additional input pins and one
additional output pin. The input pins, COMP1 and
COMP2, are high impedance inputs, each connected
to a comparator and compared against the
VREF_CNTL input or the internal reference (VREF).
Each comparator can be independently programmed
to monitor for UV or OV. When either of the COMP1
or COMP2 inputs are in fault the open-drain FAULT#
output will be pulled low. A configuration option exists
to disable the FAULT# output during margining.
Programming of the SMM105 is performed over the
industry standard I
2
C 2-wire serial data interface. A
status register is available to read the state of the part
and a Write Protect (WP#) pin is available to prevent
writing to the configuration registers and EE memory.
Figure 2 Example Power Supply Margining using the SMM105. The waveform on the left is margin low to
high from 1.6V to 2.0V and the waveform on the right is margin high to nominal from 2.0V to 1.8V. The ADOC
function guarantees the output level to be within 0.2% with a 0.1% external reference. The bottom
waveform is the READY signal indicating margin is complete.
SMM105
Preliminary Information
Summit Microelectronics, Inc
2068 1.3 6/23/03
3
W P#
A0
A1
A2
SDA
SCL
VREF_CNTL
TRIM
TRIM_CAP
V+
V-
VM
12VIN
VDD_CAP
VDD
READY
START
COMP1
COMP2
OV/UV
OV/UV
FAULT#
Output
Control
MUX
V
R EF
Input Voltage
Sensing and
Signal
Conditioning
EE
Configuration
Registers
& M emory
I
2
C Serial
Interface
3.6/5V
Regulator
Trim
Drive
Supply
Arbitration
Figure 3 SMM105 Controller Internal Block Diagram.
PACKAGE AND PIN CONFIGURATION
1
28
21
20
19
18
17
16
15
22
23
24
25
26
27
2
3
4
5
6
7
14
13
SM M 105
Pin 1
SCL
A2
START
A1
READY
A0
GND
WP
#
V
R
EF_
CNT
L
FI
LT
_
C
A
P
FA
ULT
#
NC
COM
P
2
VM
VDD
TRIM
COM P1
TRIM _CAP
NC
NC
NC
SDA
NC
NC
NC
NC
VDD_
CA
P
12V
I
N
12
11
10
9
8
INTERNAL BLOCK DIAGRAM
28 Pin QFN
Top View
SMM105
Preliminary Information
Summit Microelectronics, Inc
2068 1.3 6/23/03
4
PIN DESCRIPTIONS
Pin
Number
Pin
Type
Pin Name
Pin Description
28
DATA SDA
I
2
C Bi-directional data line
1
CLK
SCL
I
2
C clock input.
2
I
A2
4
I
A1
6
I
A0
The address pins are biased either to VDD_CAP or GND. When
communicating with the SMM105 over the 2-wire bus these pins provide a
mechanism for assigning a unique bus address.
8
I
WP#
Write Protect active low input. When asserted, writes to the configuration
registers and general purpose EE are not allowed.
10
CAP
FILT_CAP
External capacitor input used to filter the VM input.
18
CAP
TRIM_CAP
External capacitor input used for Active Control and margining.
20
O
TRIM
Output voltage used to control and/or margin converter voltages. Connect
to the converter trim input.
14
I
VM
Voltage monitor input. Connect to the DC-DC converter positive sense line
or its' +Vout pin.
9
I
VREF_CNTL
Voltage reference input used for DC output control and margining.
VREF_CNTL can be programmed to output the internal 1.25V reference.
Pin should be left open if using VREF internal
21
PWR VDD
Power supply of the part.
7
GND
GND
Ground of the part. The SMM105 ground pin should be connected to the
ground of the device under control or to a star point ground. PCB layout
should take into consideration ground drops.
22
PWR 12VIN
12V power supply input internally regulated to either 3.6V or 5.5V. When
using the 3.6V internal regulator option, the 12VIN input can be as low as
8V. It can be as high as 15V using the 5.5V internal regulator.
3
I
START
Programmable active high/low input. The START input is used solely for
enabling Active Control and/or margining.
5
I/O
READY
Programmable active high/low open drain output indicates that VM is at its
set point. When programmed as an active high output, READY can also be
used as an input. When pulled low, it will latch the state of the comparator
inputs.
23
CAP
VDD_CAP
External capacitor input used to filter the internal supply rail.
19
I
COMP1
12
I
COMP2
COMP1 and COMP2 are high impedance inputs, each connected internally
to a comparator and compared against the VREF_CNTL input. Each
comparator can be independently programmed to monitor for UV or OV.
The monitor level is set externally with a resistive voltage divider.
11
O
FAULT#
When either of the COMP1 or COMP2 inputs are in fault the open-drain
FAULT# output will be pulled low. A configuration option exists to disable
the FAULT# output while the device is margining.
13,15,16,
17,24-27
NC
NC
No Connect. Leave floating; do not connect anything to the NC pins.
SMM105
Preliminary Information
Summit Microelectronics, Inc
2068 1.3 6/23/03
5
ABSOLUTE MAXIMUM RATINGS
Temperature Under Bias ...................... -55
C to 125
C
Storage Temperature............................ -65
C to 150
C
Terminal Voltage with Respect to GND:
VDD Supply Voltage ..........................-0.3V to 6.0V
12VIN Supply Voltage......................-0.3V to 15.0V
All Others ................................-0.3V to V
DD
+ 0.7V
Output Short Circuit Current ............................... 100mA
Lead Solder Temperature (10 secs)...................300
C
Junction Temperature..........................................150C
ESD Rating per JEDEC..................................2000V
Latch-Up testing per JEDEC..........................
100mA
Note - The device is not guaranteed to function outside its operating
rating. Stresses listed under Absolute Maximum Ratings may cause
permanent damage to the device. These are stress ratings only and
functional operation of the device at these or any other conditions
outside those listed in the operational sections of the specification is
not implied. Exposure to any absolute maximum rating for extended
periods may affect device performance and reliability. Devices are
ESD sensitive. Handling precautions are recommended.
RECOMMENDED OPERATING CONDITIONS
Temperature Range (Industrial) .......... 40
C to +85
C
(Commercial)............ 5
C to +70
C
VDD Supply Voltage.................................. 2.7V to 5.5V
12VIN Supply Voltage (1)........................ 8.0V to 14.0V
VIN.............................................................GND to VDD
VOUT.......................................................GND to 15.0V
Package Thermal Resistance (
JA
)
28 Lead QFN...........................................80
o
C/W
Moisture Classification Level 1 (MSL 1) per J-STD- 020
Note 1 Range depends on internal regulator set to 3.6V or 5.5V, see
12VIN specification below.
DC OPERATING CHARACTERISTICS
(Over recommended operating conditions, unless otherwise noted. All voltages are relative to GND.)
Symbol Parameter
Notes
Min.
Typ.
Max
Unit
VDD Supply
Voltage
2.7 3.3 5.5 V
Internally regulated to 5.5V
10
15
V
12VIN Supply
Voltage
Internally regulated to 3.6V
6
14
VM
Positive Sense Voltage
VM pin
-0.3
VDD
V
I
DD
Power Supply Current from
VDD
All TRIM pins and 12VIN floating
3
5
mA
I
12VIN
Power Supply Current from
12VIN
All TRIM pins and VDD floating
3
5
mA
TRIM Sourcing Max Current
1.5
mA
I
TRIM
TRIM output current
through 100
to 1.0V
TRIM Sinking Max Current
1.5
mA
V
ADOC
Margin Control/ADOC
Range
Depends on Trim range of DC-
DC Converter
VREF_CNTL
VDD
V
VDD = 2.7V
0.9xVDD
VDD
V
IH
Input High Voltage
VDD = 5.0V
0.7xVDD
VDD
V
VDD = 2.7V
0.1xVDD
V
IL
Input Low Voltage
VDD = 5.0V
0.3xVDD
V
V
OL
Programmable Open Drain
Output (READY)
ISINK = TBD
0.2
V
OV/UV
Monitor Voltage Range
COMP1 and COMP2 pins
-0.3
VDD
V
V
HYST
Base DC Hysteresis
COMP1 and COMP2 pins,
V
TH
-V
TL
Note 1
3 10
mV
Note 1 The Base DC Hysteresis voltage is measured with a 1.25V external voltage source. The resulting value is determined by subtracting
Threshold Low from Threshold High, V
TH
-V
TL
while monitoring the FAULT# pin state. Base DC Hysteresis is measured with a 1.25V input. Actual DC
Hysteresis is derived from the equation: (V
IN
/V
REF
)(Base Hysteresis). For example, if V
IN
=2.5V and V
REF
=1.25V then Actual DC Hysteresis=
(2.5V/1.25V)(0.003V)=6mV.
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