SUMMIT MICROELECTRONICS, Inc. 300 Orchard City Drive, Suite 131 Campbell, CA 95008 Telephone 408-378-6461 Fax 408-378-6586 www.summitmicro.com
1
SUMMIT MICROELECTRONICS, Inc. 1999
2023 1.5 4/24/99
Characteristics subject to change without notice
SUMMIT
MICROELECTRONICS, Inc.
FEATURES
Four 8-Bit DACS
-- Differential Non-linearity -
0.5LSB max
-- Integral Non-Linearity Error -
1LSB max
Each DAC has Independent Reference Inputs
-- Output Buffer Amplifiers Swing Rail-to-Rail
-- Ground to V
DD
Reference Input Range
Each DAC's Digital Inputs Maintained in
EEPROM
Power-On Reset Reloads Registers with
Nonvolatile Data
Simple Serial Interface for Reading and Writing
DAC values, SPITM and QSPITM compatible.
Fully operational from 2.7V to 5.5V
Low Power, 4mW max at +5V
Quad 8-Bit Nonvolatile DACPOTTM Electronic Potentiometer
With a Mute Control Input
S9418
OVERVIEW
The S9418 DACPOTTM is a serial input, voltage output,
quad 8-bit digital to analog converter. The S9418 oper-
ates from a single +2.7V to +5.5V supply. Internal preci-
sion buffers swing rail-to-rail and the reference input
range includes both ground and the positive supply.
The S9418 integrates four 8-bit DACs and their associ-
ated circuits which include; an enhanced unity gain opera-
tional amplifier output, an 8-bit data latch, an 8-bit non-
volatile register and an industry standard serial interface
for reading and writing data to the DACs' data latches and
registers. The DACs are independently programmable
and each has its own electrically isolated Vreference
inputs.
FUNCTIONAL BLOCK DIAGRAM
DO
DAC Section 0
DAC Section 1
DAC Section 2
DAC Section 3
8-bit DAC
AMP
2023 ILL2 1.2
Programming
Memory
Controller
8-bit E2PROM
8-bit Data Register
Control
Logic
CS
RDY/BSY
DI
CLK
MUTE
VDD
GND
VREFH0
VOUT0
VREFL0
VREFH1
VOUT1
VREFL1
VREFH2
VOUT2
VREFL2
VREFH3
VOUT3
VREFL3
Memory Control
Serial Data In
Serial Data Out
2
S9418
2023 1.5 4/24/99
The analog outputs of the S9418 can be programmed to
any one of 256 individual voltage steps. Each step value
is 1/256
th
of the voltage differential between VrefH and
VrefL of the respective DAC. Once programmed these
settings can be retained in nonvolatile memory during all
power conditions and will be automatically recalled upon
a power-up sequence. Each DAC can be independently
read without affecting the output voltage during the read
cycle. In addition each output can be adjusted an unlim-
ited number of times without altering the value stored in
the nonvolatile memory.
DEVICE OPERATION
Analog Section
The S9418 is an 8-bit, voltage output digital-to-analog
converter (DAC). The DAC consists of a resistor network
that converts 8-bit digital inputs into equivalent analog
output voltages in proportion to the applied reference
voltage.
Reference inputs
The voltage differential between the V
REFL
and V
REFH
inputs sets the full-scale output voltage for its respective
DAC. V
REFL
must be equal to or greater than ground
(positive voltage). V
REFH
must be greater (more positive)
than V
REFL
or equal to V
DD
.
PINOUT and SIGNAL DEFINITION
Pin
Name
Function
1, 2
V
REFH
Vreference High:
20, 19
V
REFH
V
DD
> V
REFL
3
V
DD
Power Supply Voltage
4
RDY/
BSY
Ready/Busy: open drain output
indicating status of nonvolatile
write operations
5
CLK
Clock Input Pin: used for serial
data communication
6
CS
Chip Select: When high deselects
the device and places it in a low
power mode
7
DI
Data Input: serial data input pin
8
DO
Data Output: serial data output pin
9
MUTE
When active forces V
OUT
to V
REFL
10
GND
Power Supply Ground
11, 12
V
REFL
Vreference Low
13, 14
15, 16
V
OUT
DAC Output: buffered D to A
17, 18
converter output
Output Buffer Amplifiers
The voltage outputs are from precision unity-gain follow-
ers that can slew up to 1V/
s. The outputs can swing from
V
REFL
to V
REFH
. With a 0V to 5V output transition the
amplifier outputs typically settle to 1LSB in 50
s.
DIGITAL INTERFACE
The S9418 employs a common 4-wire serial interface. It
is comprised of a Clock (CLK), Chip Select (
CS
) and Data
In (DI) input and a Data Out (DO) output. Data is clocked
into the device on the clock's rising edge and out of the
device on the clock's falling edge. Data is shifted in and
out MSB first. DO only becomes active after the device
has been selected and after a valid read command and
address has been received.
All data transfers are initiated after
CS
goes LOW and a
logic `1' is clocked into the device. This first data transfer
is the start bit and must precede all operations. Following
the start bit are two command bits used to specify which
of four commands to execute. The next two bits are the
address bits used to select one of the four DACs. The
action of the next eight clock cycles will be dependent
upon the command issued.
1
2
3
4
5
6
7
8
9
10
V
REFH
1
V
REFH
0
V
DD
CLK
RDY/BSY
CS
DI
DO
GND
11
12
13
14
15
16
17
18
19
20
V
REFH
2
V
REFH
3
V
OUT
0
V
OUT
1
V
OUT
2
V
OUT
3
V
REFL
3
V
REFL
2
V
REFL
1
V
REFL
0
MUTE
2023 ILL1 1.2
S9418
3
2023 1.5 4/24/99
Internally there are four DACs and associated with each
are two registers. There is one data register that is used
by the DAC to hold the digital value it converts. There is
also one nonvolatile register that holds the default value
that can be recalled into the data register during power-
up or by executing the Recall command.
READ
Read operations are initiated by taking
CS
LOW and
clocking in a start bit followed by the read command and
the address of the data register to be read. The next eight
clocks will output on the DO pin the contents of the
selected data register. This read will not affect the con-
tents of the register or the output of the DAC. Refer to
Figure 1 for an illustration of the sequence of bus condi-
tions for a read operation.
WRITE
Write operations are initiated by taking
CS
LOW and
clocking in a start bit followed by the write command and
the address of the data register to be written. This action
is followed by the host clocking eight bits of data into the
register, MSB first. The output of the selected DAC will
change as the last bit is clocked into the device. At this
point the clock counter will reset the command register,
requiring a full sequence to be initiated in order to write to
the DAC again.
NOTE: This write operation does not
affect the contents of the nonvolatile register. Therefore,
the nonvolatile register can contain the power-on default
settings (e.g. volume), and the write DAC command can
be used to make situational adjustments. Refer to Figure
2 for an illustration of the sequence of bus conditions for
a write operation.
FIGURE 1. READ SEQUENCE
S CH CL AH AL
1
0
0
A
A
NV Enable - Data Don't Care
1
0
1
A
A
Write Command - Data In
1
1
0
A
A
Read - Data Out
1
1
1
A
A
Recall -Data Don't Care
TABLE 1. COMMAND FORMAT
2023 PGM T1 1.0
S
T
A
R
T
C
A
C
A
1
1
0
0
CLK
DI
DO
RDY/BSY
Hi Z
Pulled Up to V
DD
D
D
1
0
3
4
5
6
7
2
D
D
D
D
D
D
CS
Hi Z
2023 ILL3 1.0
4
S9418
2023 1.5 4/24/99
FIGURE 2. WRITE SEQUENCE
NONVOLATILE WRITE
A nonvolatile write is a two step operation: it is initiated by
taking
CS
LOW and clocking in a start bit followed by the
NV Write Enable command. At this point the host can take
CS
back high or continue clocking in data. This data is
don't care and will be ignored by the S9418.
Next, the host takes
CS
LOW again and issues a write
command and address and then clocks in the eight data
bits to be programmed. The host will then bring
CS
HIGH
FIGURE 3. NONVOLATILE WRITE SEQUENCE
and the data will be latched into the data register and a
nonvolatile write operation will commence.
The status of the nonvolatile write can be monitored on the
RDY/
BSY
pin. A logic low indicates the write is still in
progress and the S9418 will not be accessible to the host;
a logic high indicates the write has completed and the
S9418 is ready for the next command. Refer to Figure 3
for an illustration of the sequence of bus conditions for a
nonvolatile write operation.
S
T
A
R
T
C
D
A
C
D
A
1
0
3
4
5
6
7
1
1
2
0
0
D
D
D
D
D
D
CLK
DI
DO
RDY/BSY
Hi Z
Pulled Up to V
DD
CS
VOUT
2023 ILL5 1.0
A
0
1
D
CLK
DI
RDY/BSY
Pulled Up to V
DD
Rising Edge Sets
NV Write Enable Latch
S
T
A
R
T
C
C
1
0
S
T
A
R
T
C
C
1
0
D
A
D
A
1
0
3
4
5
6
7
1
2
0
D
D
D
D
D
D
Address and Data
are Don't Care
Rising Edge Starts
NV Write
NV Write Enable
Latch is Reset
CS
2023 ILL4 1.0
S9418
5
2023 1.5 4/24/99
FIGURE 4. RECALL COMMAND SEQUENCE
RECALL COMMAND
The recall command will retrieve data from the selected
nonvolatile register and write it into the data register of the
associated DAC. This operation is initiated by taking
CS
LOW and clocking in a start bit followed by the recall
command and the address of the nonvolatile register to be
recalled. The eight bits of data are don't care, so
CS
can
be taken high any time after the address bits are clocked
in. Refer to Figure 4 for an illustration of the sequence of
bus conditions for a Recall operation.
Power-On Recall
Whenever the S9418 is powered on, the V
OUT
values will
be returned to the analog equivalent of the data byte
stored in the nonvolatile register.
MUTE Operation
The MUTE input is active high. Whenever the input is low,
the V
OUT
will reflect the value in the data register. If MUTE
is driven high the V
OUT
outputs will be switched to V
REFL
.
Releasing the MUTE input returns the V
OUT
outputs to the
analog equivalent of the data register contents.
S
T
A
R
T
C
A
C
A
1
1
0
0
CLK
DI
V
OUT
CS
2023 ILL6 1.0
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