1/10
USBLC6-4SC6
VERY LOW CAPACITANCE
ESD PROTECTION
REV. 2
SOT23-6L
February 2005
MAIN APPLICATIONS
USB2.0 ports up to 480Mb/s (high speed)
Backwards compatible with USB1.1 low and
full speed
Ethernet port: 10/100Mb/s
SIM card protection
Video line protection
Portable electronics
DESCRIPTION
The USBLC6-4SC6 is a monolithic Application
Specific Discrete dedicated to ESD protection of
high speed interfaces, such as USB2.0, Ethernet
links and Video lines.
Its very low line capacitance secures a high level
of signal integrity without compromising in
protecting sensitive chips against the most
stringent characterized ESD strikes.
FEATURES
4 data lines protection
Protects V
BUS
Very low capacitance: 3pF typ.
SOT23-6L package
RoHS compliant
BENEFITS
Very low capacitance between lines to GND for
optimized data integrity and speed
Low PCB space consuming, 9mm maximum
foot print
Enhanced ESD protection
IEC61000-4-2 level 4 compliance guaranteed
at device level, hence greater immunity at
system level
ESD protection of V
BUS
. Allows ESD current
flowing to Ground when ESD event occurs on
data line
High reliability offered by monolithic integration
Low leakage current for longer operation of
battery powered devices
Fast response time
Consistent D+ / D- signal balance:
- Best capacitance matching tolerance
I/O to GND = 0.015pF
- Compliant with USB 2.0 requirements < 1pF
Table 1: Order Code
Part Number
Marking
USBLC6-4SC6
UL46
Figure 1: Functional Diagram
1
1
6
2
5
3
4
I/O1
I/O4
GND
V
BUS
I/O2
I/O3
COMPLIES WITH THE FOLLOWING STANDARDS:
IEC61000-4-2 level4:
15kV (air discharge)
8kV
(contact discharge)
ASD
(Application Specific Devices)
USBLC6-4SC6
2/10
Table 2: Absolute Ratings
Table 3: Electrical Characteristics (
Tamb
= 25C)
Symbol
Parameter
Value
Unit
V
PP
Peak pulse voltage
At device level:
IEC61000-4-2 air discharge
IEC61000-4-2 contact discharge
MIL STD883C-Method 3015-6
15
15
25
kV
T
stg
Storage temperature range
-55 to +150
C
T
j
Maximum junction temperature
125
C
T
L
Lead solder temperature (10 seconds duration)
260
C
Symbol
Parameter
Test Conditions
Value
Unit
Min.
Typ.
Max.
V
RM
Reverse stand-off voltage
5
V
I
RM
Leakage current
V
RM
= 5V
2
A
V
BR
Breakdown voltage between V
BUS
and GND
I
R
= 1mA
6
V
V
F
Forward voltage
I
R
= 10mA
0.86
V
V
CL
Clamping voltage
I
PP
= 1A, t
p
= 8/20s
Any I/O pin to GND
12
V
I
PP
= 5A, t
p
= 8/20s
Any I/O pin to GND
17
V
C
i/o-GND
Capacitance between I/O and GND V
R
= 1.65V
3
4
pF
C
i/o-GND
0.015
C
i/o-i/o
Capacitance between I/O
V
R
= 1.65V
1.85
2.7
pF
C
i/o-i/o
0.04
USBLC6-4SC6
3/10
Figure 2: Capacitance versus voltage (typical
values)
Figure 3: Line capacitance versus frequency
(typical values)
Figure 4: Relative variation of leakage current
versus junction temperature (typical values)
Figure 5: Frequency response
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
C(pF)
F=1MHz
V
=30mV
T =25C
OSC
RMS
j
C =I/O-I/O
j
C =I/O-GND
O
Data line voltage (V)
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
1
10
100
1000
C(pF)
V
=30mV
T =25C
OSC
RMS
j
V
=1.65V
CC
F(MHz)
V
=0V
CC
1
10
100
25
50
75
100
125
T (C)
j
V
=5V
BUS
I
[T
RM
j
] / I
[T
RM
j
=25C]
100.0k
1.0M
10.0M
100.0M
1.0G
-20.00
-15.00
-10.00
-5.00
0.00
USBLC6-4SC6
(50 )
S21(dB)
F(Hz)
USBLC6-4SC6
4/10
TECHNICAL INFORMATION
1. SURGE PROTECTION
The USBLC6-4SC6 is particularly optimized to perform surge protection based on the rail to rail topology.
The clamping voltage V
CL
can be calculated as follow :
V
CL
+ = V
BUS
+ V
F
for positive surges
V
CL
- = - V
F
for negative surges
with: V
F
= V
T
+ R
d
.I
p
(V
F
forward drop voltage) / (V
T
forward drop threshold voltage)
We assume that the value of the dynamic resistance of the clamping diode is typically:
R
d
= 1.4
and V
T
= 1.2V.
For an IEC61000-4-2 surge Level 4 (Contact Discharge: V
g
=8kV, R
g
=330
), V
BUS
= +5V, and if in first
approximation, we assume that : I
p
= V
g
/ R
g
= 24A.
So, we find:
V
CL
+ = +39V
V
CL
- = -34V
Note: the calculations do not take into account phenomena due to parasitic inductances.
2. SURGE PROTECTION APPLICATION EXAMPLE
If we consider that the connections from the pin V
BUS
to V
CC
and from GND to PCB GND are done by
two tracks of 10mm long and 0.5mm large; we assume that the parasitic inductances Lw of these tracks
are about 6nH. So when an IEC61000-4-2 surge occurs, due to the rise time of this spike (tr=1ns), the
voltage V
CL
has an extra value equal to Lw.dI/dt.
The dI/dt is calculated as: dI/dt = Ip/tr = 24 A/ns
The overvoltage due to the parasitic inductances is: Lw.dI/dt = 6 x 24 = 144V
By taking into account the effect of these parasitic inductances due to unsuitable layout, the clamping
voltage will be :
V
CL
+ = +39 + 144 = 183V
V
CL
- = -34 - 144 = -178V
We can reduce as much as possible these phenomena with simple layout optimization.
It's the reason why some recommendations have to be followed (see paragraph "How to ensure a good
ESD protection").
Figure 6: ESD behavior; parasitic phenomena due to unsuitable layout
Lw
VI/O
ESD
SURGE
GND
I/O
+V
CC
V
BUS
V
F
Lw di
dt
Lw di
dt
V
+ =
CL
V
+V +Lw
BUS
F
di
dt
surge >0
di
dt
surge <0
V
- =
CL
-V -Lw
F
t
tr=1ns
V
V
CC
F
+
Lw
di
dt
V
CL+
POSITIVE
SURGE
183V
-Lw
di
dt
t
tr=1ns
-
V
F
V
CL-
NEGATIVE
SURGE
-178V
USBLC6-4SC6
5/10
3. HOW TO ENSURE A GOOD ESD PROTECTION
While the USBLC6-4SC6 provides a high immunity to ESD surge, an efficient protection depends on the
layout of the board. In the same way, with the rail to rail topology, the track from the V
BUS
pin to the power
supply +V
CC
and from the V
BUS
pin to GND must be as short as possible to avoid overvoltages due to
parasitic phenomena (see figure 6).
It's often harder to connect the power supply near to the USBLC6-4SC6 unlike the ground thanks to the
ground plane that allows a short connection.
To ensure the same efficiency for positive surges when the connections can't be short enough, we
recommend to put close to the USBLC6-4SC6, between V
BUS
and ground, a capacitance of 100nF to
prevent from these kinds of overvoltage disturbances (see figure 7).
The add of this capacitance will allow a better protection by providing during surge a constant voltage.
The figures 8, 9 and 10 show the improvement of the ESD protection according to the recommendations
described above.
IMPORTANT:
A main precaution to take is to put the protection device closer to the disturbance source (generally the
connector).
Note: The measurements have been done with the USBLC6-4SC6 in open circuit.
Figure 7: ESD behavior: optimized layout and
add of a capacitance of 100nF
Figure 8: ESD behavior: measurements
conditions (with coupling capacitance)
Figure 9: Remaining voltage after the
USBLC6-4SC6 during positive ESD surge
Figure 10: Remaining voltage after the
USBLC6-4SC6 during negative ESD surge
REF1=GND
VI/O
ESD
SURGE
I/O
REF2=+
V
CC
C=100nF
Lw
V
+
V
CL
CC
F
V
+
=
surge >0
surge <0
V
V
CL
F
-
- =
t
V
+
CL
POSITIVE
SURGE
t
V
-
CL
NEGATIVE
SURGE
+5V
C=100nF
TEST BOARD
USBLC6-4SC6
ESD
SURGE
USBLC6-4SC6
6/10
4. CROSSTALK BEHAVIOR
4.1. Crosstalk phenomena
Figure 11: Crosstalk phenomena
The crosstalk phenomena are due to the coupling between 2 lines. The coupling factor (
12 or 21)
increases when the gap across lines decreases, particularly in silicon dice. In the example above the
expected signal on load R
L2
is
2
V
G2
, in fact the real voltage at this point has got an extra value
21
V
G1
.
This part of the V
G1
signal represents the effect of the crosstalk phenomenon of the line 1 on the line 2.
This phenomenon has to be taken into account when the drivers impose fast digital data or high frequency
analog signals in the disturbing line. The perturbed line will be more affected if it works with low voltage
signal or high load impedance (few k
).
Figure 12: Analog crosstalk measurements
Figure 12 gives the measurement circuit for the analog application. In usual frequency range of analog
signals (up to 240MHz) the effect on disturbed line is less than -55 dB (please see figure 13).
Line 1
Line 2
V
G1
V
G2
R
G1
R
G2
DRIVERS
R
L1
R
L2
RECEIVERS
+
1
12
V
G1
V
G2
+
2
21
V
G2
V
G1
SPECTRUM ANALYSER
Vout
50
TRACKING GENERATOR
Vg
Vin
50
TEST BOARD
+5V
USBLC6-4SC6
C=100nF
Figure 13: Analog crosstalk results
As the USBLC6-4SC6 is designed to protect high
speed data lines, it must ensure a good transmis-
sion of operating signals. The frequency response
(figure 5) gives attenuation information and shows
that the USBLC6-4SC6 is well suitable for data
line transmission up to 480 Mbit/s while it works
as a filter for undesirable signals like GSM
(900MHz) frequencies, for instance.
100.0k
1.0M
10.0M
100.0M
1.0G
-120.00
-90.00
-60.00
-30.00
0.00
USBLC6-4SC6
Aplac 7.70 User: ST Microelectronics Oct 29 2004
dB
f/Hz
USBLC6-4SC6
7/10
5. APPLICATION EXAMPLES
Figure 14: USB2.0 port application diagram using USBLC6-4SC6
Figure 15: T1/E1/Ethernet protection
HUB-
DOWNSTREAM
TRANSCEIVER
+ 5V
R
S
R
S
R
S
R
S
R
PD
R
PD
R
PD
R
PD
Protecting
Bus Switch
DEVICE-
UPSTREAM
TRANSCEIVER
+ 3.3V
SW
1
R
PU
V
BUS
D+
D-
GND
V
BUS
V
BUS
V
BUS
R
X LS/FS
+
R
X LS/FS
+
R
X LS/FS
+
R
X LS/FS
+
R
X HS
+
R
X HS
+
R
X HS
+
R
X HS
+
T
X HS
+
T
X HS
+
T
X HS
+
T
X HS
+
T
X LS/FS
+
T
X LS/FS
+
T
X LS/FS
+
T
X LS/FS
+
R
S
R
S
USB
connector
T
X LS/FS -
T
X LS/FS -
T
X LS/FS -
T
X LS/FS -
R
X LS/FS -
R
X LS/FS -
R
X LS/FS -
R
X LS/FS -
R
X HS -
R
X HS -
R
X HS -
R
X HS -
T
X HS -
T
X HS -
T
X HS -
T
X HS -
GND
GND
GND
GND
SW
2
DEVICE-
UPSTREAM
TRANSCEIVER
USBLC6-4SC6
USBLC6-2P6
USBLC6-2SC6
+ 3.3V
SW
1
R
PU
V
BUS
D+
D-
GND
R
S
R
S
USB
connector
SW
2
Open
Closed then open
High Speed HS
Open
Closed
Full Speed FS
Closed
Open
Low Speed LS
SW
2
SW
1
Mode
USBLC6-4SC6
+V
CC
100nF
DATA
TRANSCEIVER
SMP75-8
SMP75-8
Tx
Rx
USBLC6-4SC6
8/10
6. PSPICE MODEL
Figure 16 shows the PSPICE model of one USBLC6-4SC6 cell. In this model, the diodes are defined by
the PSPICE parameters given in figure 17.
Note: This simulation model is available only for an ambient temperature of 27C.
Figure 16: PSPICE model
Figure 17: PSPICE parameters
Figure
18:
USBLC6-4SC6 PCB layout
considerations
Vcc
Lpinsot 23
io1
Lbo ndso t 23 100 m
Lpinsot 23
Lpi nsot 23
100 m
io2
Lbo ndso t 23 100 m
Lpinsot 23
Lbo ndso t 23
io3
MODEL = Dhigh
MODEL = Dhigh
MODEL = Dhigh
MODEL = Dhigh
MODEL = Dlow
MODEL = Dlow
MODEL = Dlow
MODEL = Dlow
MODEL = Dzener
Rgn d
Lgn d
Lbo ndso t 23 100 m
Lpinsot 23
Lpinsot 23
io4
Lbo ndso t 23 100 m
Rvc c
Lvc c
100 m
Lbo ndso t 23
100 m
Lbo ndso t 23
0.1u
0.1u
0.1u
TT
0.6
0.6
0.6
VJ
0.42
0.63
0.38
RS
0.3333
0.3333
0.3333
M
1.24
1.13
1.62
N
100p
100p
100p
ISR
3.21p
2.27f
55.2p
IS
2.42
0.018
0.038
IKF
1m
1m
1m
IBV
20p
2.4p
2.4p
CJ0
7.3
50
50
BV
Dzener
Dhigh
Dlow
100p
Lvcc
350m
Rvcc
100p
Lgnd
350m
Rgnd
0.15n
Lpinsot23
0.564n
Lbondsot23
D+1
C
= 100nF
BUS
D-1
GND
USBLC6-4SC6
D+2
D-2
V
BUS
1
USBLC6-4SC6
9/10
Figure 19: SOT23-6L Package Mechanical Data
Figure 20: Foot Print Dimensions (in millimeters)
A2
A
L
H
c
B
E
D
e
e
A1
0.95
0.60
1.20
1.10
3.50
2.30
Table 4: Ordering Information
Ordering code
Marking
Package
Weight
Base qty
Delivery mode
USBLC6-4SC6
UL46
SOT23-6L
16.7 mg
3000
Tape & reel
Table 5: Revision History
Date
Revision
Description of Changes
10-Dec-2004
1
First issue.
28-Feb-2005
2
Minor layout update. No content change.
REF.
DIMENSIONS
Millimeters
Inches
Min.
Typ.
Max.
Min.
Typ.
Max.
A
0.90
1.45
0.035
0.057
A1
0
0.10
0
0.004
A2
0.90
1.30
0.035
0.051
b
0.35
0.50
0.014
0.02
C
0.09
0.20
0.004
0.008
D
2.80
3.05
0.110
0.120
E
1.50
1.75
0.059
0.069
e
0.95
0.037
H
2.60
3.00
0.102
0.118
L
0.10
0.60
0.004
0.024
0
10
0
10
USBLC6-4SC6
10/10
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of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
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