TDA7309
DIGITAL CONTROLLED STEREO AUDIO PROCESSOR
WITH LOUDNESS
INPUT MULTIPLEXER:
3 STEREO INPUTS
RECORD OUTPUT FUNCTION
LOUDNESS FUNCTION
VOLUME CONTROL IN 1dB STEPS
INDEPENDENT LEFT AND RIGHT VOLUME
CONTROL
SOFT MUTE FUNCTION
ALL FUNCTIONS PROGRAMMABLE VIA SE-
RIAL I
2
C BUS
DESCRIPTION
The TDA7309 is a control processor with inde-
pendent left and right volume control for quality
audio applications. Selectable external loudness
and soft mute functions are provided.
Control is accomplished by serial I
2
C bus micro-
processor interface.
The AC signal setting is obtained by resistor net-
works and switches combined with operational
amplifiers.
Thanks to the used BIPOLAR/CMOS Technology,
Low Distortion, Low Noise and Low DC stepping
are obtained.
September 1997
17
18
13
14
11
INPUT
SELECTOR
LEFT
INPUTS
RIGHT
INPUTS
SUPPLY
16
7
15
VOLUME +
LOUDNESS
SOFT
MUTE
19
LOUD(L)
22
F
CREF
12
LOUD(R)
MUTE
MUTE
6
4
5
8
9
2
OUT
LEFT
SCL
SDA
DIGGND
OUT
RIGHT
ADDR
D93AU045A
BUS
SERIAL BUS DECODER + LATCHES
20
3 x
2.2
F
3 x
2.2
F
VOLUME +
LOUDNESS
AGND
VS
3
CSM
100nF
100nF
TDA7309
10
Recout(R)
1
Recout(L)
BLOCK DIAGRAM
DIP20
SO20
ORDERING NUMBER:
TDA7309
TDA7309D
1/12
ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
Value
Unit
V
S
Operating Supply Voltage
10.5
V
T
amb
Operating Ambient Temperature
40 to 85
C
T
stg
Storage Temperature Range
55 to +150
C
QUICK REFERENCE DATA
Symbol
Parameter
Test Condition
Min.
Typ.
Max.
Unit
V
S
Operating Supply Voltage
6
10
V
V
CL
Max. Input Signal Handling
2
Vrms
THD
Total Harmonic Distortion
V = 1Vrms, f = 1KHz
0.01
0.1
%
S/N
Signal to Noise Ratio
106
dB
Sc
Channel Separation f = 1KHz
100
dB
Volume Control 1.0dB step
95
0
dB
Soft Mute Attenuation
60
dB
Direct Mute Attenuation
100
dB
RecoutL
OUTL
CSM
SDA
SCL
GND
DGND
ADD
OUTR
1
3
2
4
5
6
7
8
9
LOUDR
IN2R
IN1R
VS
CREF
IN1L
IN2L
LOUDL
IN3L
20
19
18
17
16
14
15
13
12
D94AU058A
RecoutR
10
IN3R
11
PIN CONNECTION (Top View)
IN1L
IN2L
IN3L
RecoutL
IN1R
IN2R
IN3R
RecoutR
17
18
20
1
14
13
10
11
19
12
5
4
6
8
LL
LR
SCL
SDA
DIGGND
ADD
CSM
3
2
16
15
CREF
AGND
7
OUTL
VS
OUTR
9
D94AU057A
TDA7309
TEST CIRCUIT
TDA7309
2/12
ELECTRICAL CHARACTERISTICS (Refer to the test circuit, T
amb
= 25
C, V
S
= 9V, R
L
= 10K
,
R
G
= 50
, all controls flat (G = 0), f = 1KHz unless otherwise specified.)
Symbol
Parameter
Test Condition
Min.
Typ.
Max.
Unit
SUPPLY
V
S
Supply Voltage
5 (*)
9
10
V
I
S
Supply Current
7
10
mA
SVR
Ripple Rejection
60
85
dB
INPUT SELECTORS
R
I
Input Resistance
35
50
65
K
S
in
Input Separation
80
90
dB
VOLUME CONTROL
C
RANGE
Control Range
92
dB
A
VMAX
Max. Attenuation
87
92
95
dB
A
STEP
Step resolution
0.5
1
1.5
dB
E
A
Attenuation Set Error
A
V
= 0 to -24dB
-1.2
1.2
dB
A
V
= -24 to -56dB
-3
2
dB
E
T
Tracking Error
2
dB
V
DC
DC Steps
adjacent attenuation steps
0
3
mV
from 0dB to A
V
max.
0.5
5
mV
A
mute
Output Mute Attenuation
80
100
dB
SOFT MUTE
T
d
Delay Time
C
smute
= 22nF 0 to 20dB
Fast Mode
Slow Mode
1
20
ms
ms
AUDIO OUTPUTS
V
CLIP
Clipping Level
d = 0.3%
2
2.6
Vrms
R
L
Output Load Resistance
2
K
R
out
Output Impedance
100
200
300
V
DC
DC Voltage Level
3.8
V
GENERAL
e
NO
Output Noise
BW = 20-20KHz, flat
output muted
all gains = 0dB
2.5
5
15
V
V
A curve all gains = 0dB
3
V
Et
Total Tracking Error
A
V
= 0 to 24dB
A
V
= -24 to 56dB
0
0
1
2
dB
dB
S/N
Signal to Noise Ratio
all gains = 0dB; V
O
= 1Vrms
95
106
dB
d
Distortion
0.01
0.1
%
S
C
Channel Separation
80
100
dB
BUS INPUTS
V
IL
Input Low Voltage
1
V
V
IH
Input High Voltage
3
V
I
IN
Input Current
V
in
= 0.4V
-5
+5
A
V
O
Output Voltage SDA
Acknowledge
I
O
= 1.6mA
0.4
0.8
V
(*) Hedevice work until 5V but no guarantee about SVR
THERMAL DATA
Symbol
Parameter
SO20
DIP20
Unit
R
th j-pins
Thermal resistance Junction to Pins
150
100
C/W
TDA7309
3/12
Figure 1: Noise vs. volume setting.
Figure 3: THD vs. frequency
Figure 5: Channel separation vs. frequency.
Figure 4: THD vs. R
LOAD
.
Figure 6: Output clip level vs. Supply Voltage.
Figure 2: SVRR vs. frequency.
TDA7309
4/12
Figure 7: Quiescent current vs. supply voltage.
Figure 9: Loudnes vs. Frequency
(C
LOUD
= 100nF) vs. Volume
Figure 10: Loudness vs. External Capacitors
Figure 8: Loudnessvs. Volume Attenuation.
TDA7309
5/12
I
2
C BUS INTERFACE
Data transmission from microprocessor to the
TDA7313 and viceversa takes place thru the 2
wires I
2
C BUS interface, consisting of the two
lines SDA and SCL (pull-up resistors to positive
supply voltage must be connected).
Data Validity
As shown in fig. 11, the data on the SDA line
must be stable during the high period of the clock.
The HIGH and LOW state of the data line can
only change when the clock signal on the SCL
line is LOW.
Start and Stop Conditions
As shown in fig. 12 a start condition is a HIGH to
LOW transition of the SDA line while SCL is
HIGH. The stop condition is a LOW to HIGH tran-
sition of the SDA line while SCL is HIGH.
Byte Format
Every byte transferred on the SDA line must con-
tain 8 bits. Each byte must be followed by an ac-
knowledge bit. The MSB is transferred first.
Acknowledge
The master (
P) puts a resistive HIGH level on the
SDA line during the acknowledge clock pulse (see
fig. 13). The peripheral (audioprocessor) that ac-
knowledges has to pull-down (LOW) the SDA line
during the acknowledge clock pulse, so that the
SDA line is stable LOW during this clock pulse.
The audioprocessor which has been addressed
has to generate an acknowledge after the recep-
tion of each byte, otherwise the SDA line remains
at the HIGH level during the ninth clock pulse
time. In this case the master transmitter can gen-
erate the STOP information in order to abort the
transfer.
Transmission without Acknowledge
Avoiding to detect the acknowledge of the audio-
processor, the
P can use a simplier transmis-
sion: simply it waits one clock without checking
the slave acknowledging, and sends the new
data.
This approach of course is less protected from
misworking and decreases the noise immunity.
Figure 11: Data Validity on the I
2
CBUS
Figure 12: Timing Diagram of I
2
CBUS
Figure 13: Acknowledge on the I
2
CBUS
TDA7309
6/12
SDA, SCL I
2
CBUS TIMING
Symbol
Parameter
Min.
Typ.
Max.
Unit
f
SCL
SCL clock frequency
0
400
kHz
t
BUF
Bus free time between a STOP and START condition
1.3
s
t
HD:STA
Hold time (repeated) START condition. After this period, the first
clock pulse is generated
0.6
s
t
LOW
LOW period of the SCL clock
1.3
s
t
HIGH
HIGH period of the SCL clock
0.6
s
t
SU:STA
Set-up time for a repeated START condition
0.6
s
t
HD:DA
Data hold time
0.300
s
t
SU:DAT
Data set-up time
100
ns
t
R
Rise time of both SDA and SCL signals
20
300
ns (*)
t
F
Fall time of both SDA and SCL signals
20
300
ns (*)
t
SU:STO
Set-up time for STOP condition
0.6
s
All values referred to V
IH min.
and V
IL max.
levels
(*) Must be guaranteed by the I
2
C BUS master.
SDA
SCL
t
BUF
P
S
t
HD;STA
t
LOW
t
R
t
F
t
HD;DAT
t
SU;DAT
t
HIGH
t
F
Sr
P
t
SU;STA
t
HD;STA
t
SP
t
SU;STO
D95AU314
P = STOP
S = START
Definition of timing on the I
2
C-bus
TDA7309
7/12
SOFTWARE SPECIFICATION
Interface Protocol
The interface protocol comprises:
A start condition (s)
A chip address byte, containing the TDA7309
address (the 8th bit of the byte must be 0). The
TDA7309 must always acknowledge at the end
of each transmitted byte.
A sequence of data (N-bytes + acknowledge)
A stop condition (P)
TDA7309 ADDRESS
MSB
first byte
LSB
MSB
LSB
MSB
LSB
S
0
0
1
1
0
0
A
0
ACK
DATA
ACK
DATA
ACK
P
Data Transferred (N-bytes + Acknowledge)
ACK = Acknowledge
S = Start
P = Stop
MAX CLOCK SPEED 100kbits/s
SOFTWARE SPECIFICATION
Chip address
MSB
LSB
0
0
1
1
0
0
1
0
pin address open
0
0
1
1
0
0
0
0
pin address close to ground
MSB
F6
F5
F4
F3
F2
F1
LSB
VOLUME
0
X
X
X
X
X
X
X
MUTE/LOUD
1
0
0
X
X
X
X
X
INPUTS
1
0
1
X
X
X
X
X
CHANNEL
1
1
0
X
X
X
X
X
CHANNEL ABILITATION CODES
MSB
F6
F5
F4
F3
F2
F1
LSB
FUNCTION
1
1
0
channel
X
X
X
0
0
RIGHT
X
X
X
0
1
LEFT
X
X
X
1
0
BOTH
X
X
X
1
1
BOTH
Power on reset condition
1 1 1 1 1 1 1 0
FUNCTION CODES
TDA7309
8/12
MSB
F6
F5
F4
F3
F2
F1
LSB
FUNCTION
0
step 1dB
0
0
0
0dB
0
0
1
-1dB
0
1
0
-2dB
0
1
1
-3dB
1
0
0
-4dB
1
0
1
-5dB
1
1
0
-6dB
1
1
1
-7dB
0
step 8dB
0
0
0
0
0dB
0
0
0
1
-8dB
0
0
1
0
-16dB
0
0
1
1
-24dB
0
1
0
0
-32dB
0
1
0
1
-40dB
0
1
1
0
-48dB
0
1
1
1
-56dB
1
0
0
0
-64dB
1
0
0
1
-72dB
1
0
1
0
-80dB
1
0
1
1
-88dB
1
1
X
X
MUTE
MUTE LOUDNESS CODES
MSB
F6
F5
F4
F3
F2
F1
LSB
FUNCTION
1
0
0
mute/loud
X
0
0
slow soft mute on
X
0
1
fast soft mute on
1
soft mute off
1
LOUD OFF
X
0
0
loud on (10dB)
X
1
0
loud on (20dB)
INPUT MULTIPLEXER CODES
MSB
F6
F5
F4
F3
F2
F1
LSB
FUNCTION
1
0
1
inputs
X
X
X
0
0
MUTE
X
X
X
0
1
IN2
X
X
X
1
0
IN3
X
X
X
1
1
IN1
VOLUME CODES
Purchase of I
2
C Components of SGS-THOMSON Microlectronics, conveys a license under the Philips
I
2
C Patent Rights to use these components in an I
2
C system, provided that the system conforms to
the I
2
C Standard Specifications as defined by Philips.
TDA7309
9/12
SO20 PACKAGE MECHANICAL DATA
DIM.
mm
inch
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
A
2.65
0.104
a1
0.1
0.3
0.004
0.012
a2
2.45
0.096
b
0.35
0.49
0.014
0.019
b1
0.23
0.32
0.009
0.013
C
0.5
0.020
c1
45 (typ.)
D
12.6
13.0
0.496
0.512
E
10
10.65
0.394
0.419
e
1.27
0.050
e3
11.43
0.450
F
7.4
7.6
0.291
0.299
L
0.5
1.27
0.020
0.050
M
0.75
0.030
S
8 (max.)
TDA7309
10/12
DIP20 PACKAGE MECHANICAL DATA
DIM.
mm
inch
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
a1
0.254
0.010
B
1.39
1.65
0.055
0.065
b
0.45
0.018
b1
0.25
0.010
D
25.4
1.000
E
8.5
0.335
e
2.54
0.100
e3
22.86
0.900
F
7.1
0.280
I
3.93
0.155
L
3.3
0.130
Z
1.34
0.053
TDA7309
11/12
Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsibility for the
consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No
license is granted by implication or otherwise under any patent or patent rights of SGS-THOMSON Microelectronics. Specification mentioned
in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. SGS-
THOMSON Microelectronics products are not authorized for use as critical components in life support devices or systems without express
written approval of SGS-THOMSON Microelectronics.
1997 SGS-THOMSON Microelectronics Printed in Italy All Rights Reserved
SGS-THOMSON Microelectronics GROUP OF COMPANIES
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TDA7309
12/12
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