1/19
December 2004
M30W0R6500T0
96 Mbit (64 + 32Mb, x16, Multiple Bank, Burst, Flash Memories)
1.8V Supply, Multi-Chip Package
FEATURES SUMMARY
MULTI-CHIP PACKAGE
1 die of 64 Mbit (4Mb x 16) Flash Memory
1 die of 32 Mbit (2Mb x 16) Flash Memory
SUPPLY VOLTAGE
V
DDF1
= V
DDF2
= V
DDQ
= 1.7 to 2.2V
V
PP
= 12V for fast Program (optional)
LOW POWER CONSUMPTION
ELECTRONIC SIGNATURE
Manufacturer Code: 20h
64Mb Device Code (Top Configuration):
8810h
32Mb Device Code (Top Configuration):
8814h
PACKAGE
Compliant with Lead-Free Soldering
Processes
Lead-Free Versions
FLASH MEMORY
SYNCHRONOUS / ASYNCHRONOUS READ
Synchronous Burst Read mode: 54MHz
Asynchronous/ Synchronous Page Read
mode
Random Access: 70ns
PROGRAMMING TIME
8s by Word typical for Fast Factory
Program
Double/Quadruple Word Program option
Enhanced Factory Program options
ARCHITECTURE
64Mbit and 32Mbit Flash memories
Multiple Bank Memory Array: 4 Mbit
Banks
Parameter Blocks (Top location)
DUAL OPERATIONS
Program Erase in one Bank while Read in
others
No delay between Read and Write
operations
Figure 1. Packages
BLOCK LOCKING
All blocks locked at Power up
Any combination of blocks can be locked
WP for Block Lock-Down
SECURITY
128 bit user programmable OTP cells
64 bit unique device number
One parameter block permanently
lockable
COMMON FLASH INTERFACE (CFI)
100,000 PROGRAM/ERASE CYCLES per
BLOCK
FBGA
Stacked LFBGA88 (ZA)
8 x 10mm
M30W0R6500T0
2/19
TABLE OF CONTENTS
FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
FLASH MEMORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Figure 1. Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
SUMMARY DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Figure 2. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Table 1. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 3. LFBGA Connections (Top view through package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
SIGNAL DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Address Inputs (A0-A21). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Data Input/Output (DQ0-DQ15). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Chip Enable (E
(F1/F2)
). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Output Enable (G
(F1/F2)
). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Write Enable (W). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Write Protect (WP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Reset (RP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Latch Enable (L). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Clock (K). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Wait (WAIT). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
V
DD(F1/F2)
Supply Voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
V
DDQ
Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
V
PP
Program Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
V
SS
Ground. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
V
SSQ
Ground. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
FUNCTIONAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 4. Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Table 2. Main Operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
64Mbit FLASH MEMORY COMPONENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
32Mbit FLASH MEMORY COMPONENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Table 3. Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
DC AND AC PARAMETERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Table 4. Operating and AC Measurement Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 5. AC Measurement I/O Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 6. AC Measurement Load Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Table 5. Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Table 6. DC Characteristics - Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Table 7. DC Characteristics - Voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3/19
M30W0R6500T0
PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 7. Stacked LFBGA88 8x10mm, 8x10 array, 0.8mm pitch, Bottom View Package Outline . 16
Table 8. Stacked LFBGA88 8x10mm - 8x10 ball array, 0.8mm pitch, Package Mechanical Data 16
PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 9. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
REVISION HISTORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 10. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
M30W0R6500T0
4/19
SUMMARY DESCRIPTION
The M30W0R6500T0 is a 96 Mbit device that is
composed of two separate 64-Mbit and 32-Mbit
Flash memories, both with Top Boot Block archi-
tecture.
Each Flash memory can be erased electrically at
block level and programmed in-system on a Word-
by-Word basis using a 1.7 to 2.2V V
DD
supply for
the circuitry and a 1.7 to 2.2V V
DDQ
supply for the
Input/Output pins. An optional 12V V
PP
power
supply is provided to speed up customer program-
ming.
Two Chip Enable signals are provided to select
and enable each memory. Only one memory can
be selected at a time. Once selected the memory
operates in the same way as the single memory
devices M58WR064E and M58WR032E (refer to
the respective datasheets).
The 64 Mbit Flash memory features an asymmet-
rical block architecture with an array of 135 blocks
divided into 4 Mbit banks. It has 15 banks each
containing 8 main blocks of 32 KWords, and one
parameter bank containing 8 parameter blocks of
4 KWords and 7 main blocks of 32 KWords.
The 32 Mbit Flash memory features an asymmet-
rical block architecture with an array of 71 blocks
divided into 4 Mbit banks. It has 7 banks each con-
taining 8 main blocks of 32 KWords, and one pa-
rameter bank containing 8 parameter blocks of 4
KWords and 7 main blocks of 32 KWords.
The Multiple Bank Architecture allows Dual Oper-
ations, while programming or erasing in one bank,
Read operations are possible in other banks. Only
one bank at a time is allowed to be in Program or
Erase mode. It is possible to perform burst reads
that cross bank boundaries.
Each block can be erased separately. Erase can
be suspended, in order to perform program in any
other block, and then resumed. Program can be
suspended to read data in any other block and
then resumed. Each block can be programmed
and erased over 100,000 cycles using the supply
voltage V
DD
. There are two Enhanced Factory
programming commands available to speed up
programming.
Program and Erase commands are written to the
Command Interface of the memory. An internal
Program/Erase Controller takes care of the tim-
ings necessary for program and erase operations.
The end of a program or erase operation can be
detected and any error conditions identified in the
Status Register. The command set required to
control the memory is consistent with JEDEC stan-
dards.
The M30W0R6500T0 supports synchronous burst
read and asynchronous read from all blocks of
each memory array; at power-up each device is
configured for asynchronous read. In synchronous
burst mode, data is output on each clock cycle at
frequencies of up to 54MHz.
Each device features an Automatic Standby
mode. When the bus is inactive during asynchro-
nous read operations, the device automatically
switches to the Automatic Standby mode. In this
condition the power consumption is reduced to the
standby value I
DD4
and the outputs are still driven.
The M30W0R6500T0 features an instant, individ-
ual block locking scheme that allows any block to
be locked or unlocked with no latency, enabling in-
stant code and data protection. All blocks have
three levels of protection. They can be locked and
locked-down individually preventing any acciden-
tal programming or erasure. There is an additional
hardware protection against program and erase.
When V
PP
V
PPLK
all blocks are protected against
program or erase. All blocks are locked at Power-
Up.
Each memory includes a Protection Register and
a Security Block to increase the protection of a
system's design. Each Protection Register is divid-
ed into two segments: a 64 bit segment containing
a unique device number written by ST, and a 128
bit segment One Time Programmable (OTP) by
the user. The user programmable segments can
be permanently protected. The Security Blocks,
parameter blocks 0, can be permanently protected
by the user.
The memory is offered in a Stacked LFBGA88
(8 x 10mm, 8x10 ball array, 0.8mm pitch) pack-
age.
In addition to the standard version, the packages
are also available in Lead-free version, in compli-
ance with JEDEC Std J-STD-020B, the ST ECO-
PACK 7191395 Specification, and the RoHS
(Restriction of Hazardous Substances) directive.
All packages are compliant with Lead-free solder-
ing processes.
The memory is supplied with all the bits erased
(set to `1').
5/19
M30W0R6500T0
Figure 2. Logic Diagram
Table 1. Signal Names
Note: 1. A21 is not connected to the 32Mbit Flash Memory com-
ponent.
AI08597
22
A0-A21
W
DQ0-DQ15
V
DDF1
M30W0R6500T0
E
F1
V
SS
16
G
F1
RP
WP
V
DDQ
V
PP
L
K
WAIT
V
SSQ
E
F2
G
F2
V
DDF2
A0-A21
1
Address Inputs
DQ0-DQ15
Data Input/Outputs, Command
Inputs
E
F1
Chip Enable of 64Mb Flash Device
E
F2
Chip Enable of 32Mb Flash Device
G
F1
Output Enable of 64Mb Flash
Device
G
F2
Output Enable of 32Mb Flash
Device
W
Write Enable
RP
Reset
WP
Write Protect
K
Clock
L
Latch Enable
WAIT
Wait
V
DDF1
Supply Voltage of 64Mb Flash
device
V
DDF2
Supply Voltage of 32Mb Flash
device
V
DDQ
Supply Voltage for Input/Output
Buffers
V
PP
Optional Supply Voltage for
Fast Program & Erase
V
SS
Ground
V
SSQ
Ground Input/Output Supply
NC
Not Connected Internally
DU
Do Not Use
PDF 
ZIP