1/18
December 2001
M27C800
8 Mbit (1Mb x8 or 512Kb x16) UV EPROM and OTP EPROM
s
5V 10% SUPPLY VOLTAGE in READ
OPERATION
s
ACCESS TIME: 50ns
s
BYTE-WIDE or WORD-WIDE
CONFIGURABLE
s
8 Mbit MASK ROM REPLACEMENT
s
LOW POWER CONSUMPTION
Active Current 70mA at 8MHz
Stand-by Current 50A
s
PROGRAMMING VOLTAGE: 12.5V 0.25V
s
PROGRAMMING TIME: 50s/word
s
ELECTRONIC SIGNATURE
Manufacturer Code: 20h
Device Code: B2h
DESCRIPTION
The M27C800 is an 8 Mbit EPROM offered in the
two ranges UV (ultra violet erase) and OTP (one
time programmable). It is ideally suited for micro-
processor systems requiring large data or program
storage. It is organised as either 1 Mwords of 8 bit
or 512 Kwords of 16 bit. The pin-out is compatible
with the most common 8 Mbit Mask ROM.
The FDIP42W (window ceramic frit-seal package)
has a transparent lid which allows the user to ex-
pose the chip to ultraviolet light to erase the bit pat-
tern.
A new pattern can then be written rapidly to the de-
vice by following the programming procedure.
For applications where the content is programmed
only one time and erasure is not required, the
M27C800 is offered in PDIP42, PLCC44 and
SO44 packages.
1
42
1
42
44
1
FDIP42W (F)
PDIP42 (B)
SO44 (M)
PLCC44 (K)
Figure 1. Logic Diagram
AI01593
19
A0-A18
BYTEVPP
Q0-Q14
VCC
M27C800
G
E
VSS
15
Q15A1
M27C800
2/18
Figure 2B. LCC Connections
AI02042
A11
A14
Q7
Q5
23
Q0
Q8
Q1
Q9
Q2
NC
Q12
A4
A0
E
VSS
A3
A2
12
A10
A16
1
A7
BYTEVPP
A13
A5
Q6
44
V
SS
A9
M27C800
A6
A12
Q13
VSS
Q14
34
Q10
A1
A15
Q15A1
G
Q3
Q11
V
CC
Q4
A18
A17
A8
NC
Figure 2A. DIP Connections
G
Q0
Q8
A3
A0
E
VSS
A2
A1
A13
VSS
A14
A15
Q7
A12
A16
BYTEVPP
Q15A1
Q5
Q2
Q3
VCC
Q11
Q4
Q14
A9
A8
A17
A4
A18
NC
A7
AI01594
M27C800
8
1
2
3
4
5
6
7
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
20
19
18
17
Q1
Q9
A6
A5
Q6
Q13
42
39
38
37
36
35
34
33
A11
A10
Q10
21
Q12
40
41
Figure 2C. SO Connections
G
Q0
Q8
A3
A0
E
VSS
A2
A1
A13
VSS
A14
A15
Q7
A12
A16
BYTEVPP
Q15A1
Q5
Q2
Q3
VCC
Q11
Q4
Q14
A9
NC
A18
A4
NC
NC
A7
AI01595
M27C800
8
2
3
4
5
6
7
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
20
19
18
17
Q1
Q9
A6
A5
Q6
Q13
44
39
38
37
36
35
34
33
A11
A10
Q10
21
Q12
40
43
1
42
41
A17
A8
Table 1. Signal Names
A0-A18
Address Inputs
Q0-Q7
Data Outputs
Q8-Q14
Data Outputs
Q15A1
Data Output / Address Input
E
Chip Enable
G
Output Enable
BYTEV
PP
Byte Mode / Program Supply
V
CC
Supply Voltage
V
SS
Ground
NC
Not Connected Internally
3/18
M27C800
Table 2. Absolute Maximum Ratings
(1)
Note: 1. Except for the rating "Operating Temperature Range", stresses above those listed in the Table "Absolute Maximum Ratings" may
cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions
above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating condi-
tions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant qual-
ity documents.
2. Minimum DC voltage on Input or Output is 0.5V with possible undershoot to 2.0V for a period less than 20ns. Maximum DC
voltage on Output is V
CC
+0.5V with possible overshoot to V
CC
+2V for a period less than 20ns.
3. Depends on range.
Table 3. Operating Modes
Note: X = V
IH
or V
IL
, V
ID
= 12V 0.5V.
Table 4. Electronic Signature
Symbol
Parameter
Value
Unit
T
A
Ambient Operating Temperature
(3)
40 to 125
C
T
BIAS
Temperature Under Bias
50 to 125
C
T
STG
Storage Temperature
65 to 150
C
V
IO
(2)
Input or Output Voltage (except A9)
2 to 7
V
V
CC
Supply Voltage
2 to 7
V
V
A9
(2)
A9 Voltage
2 to 13.5
V
V
PP
Program Supply Voltage
2 to 14
V
Mode
E
G
BYTEV
PP
A9
Q15A1
Q14-Q8
Q7-Q0
Read Word-wide
V
IL
V
IL
V
IH
X
Data Out
Data Out
Data Out
Read Byte-wide Upper
V
IL
V
IL
V
IL
X
V
IH
Hi-Z
Data Out
Read Byte-wide Lower
V
IL
V
IL
V
IL
X
V
IL
Hi-Z
Data Out
Output Disable
V
IL
V
IH
X
X
Hi-Z
Hi-Z
Hi-Z
Program
V
IL
Pulse
V
IH
V
PP
X
Data In
Data In
Data In
Verify
V
IH
V
IL
V
PP
X
Data Out
Data Out
Data Out
Program Inhibit
V
IH
V
IH
V
PP
X
Hi-Z
Hi-Z
Hi-Z
Standby
V
IH
X
X
X
Hi-Z
Hi-Z
Hi-Z
Electronic Signature
V
IL
V
IL
V
IH
V
ID
Code
Codes
Codes
Identifier
A0
Q15
and
Q7
Q14
and
Q6
Q13
and
Q5
Q12
and
Q4
Q11
and
Q3
Q10
and
Q2
Q9
and
Q1
Q8
and
Q0
Hex Data
Manufacturer's Code
V
IL
0
0
1
0
0
0
0
0
20h
Device Code
V
IH
1
0
1
1
0
0
1
0
B2h
M27C800
4/18
DEVICE OPERATION
The operating modes of the M27C800 are listed in
the Operating Modes Table. A single power supply
is required in the read mode. All inputs are TTL
compatible except for V
PP
and 12V on A9 for the
Electronic Signature.
Read Mode
The M27C800 has two organisations, Word-wide
and Byte-wide. The organisation is selected by the
signal level on the BYTEV
PP
pin. When BYTEV
PP
is at V
IH
the Word-wide organisation is selected
and the Q15A1 pin is used for Q15 Data Output.
When the BYTEV
PP
pin is at V
IL
the Byte-wide or-
ganisation is selected and the Q15A1 pin is used
for the Address Input A1. When the memory is
logically regarded as 16 bit wide, but read in the
Byte-wide organisation, then with A1 at V
IL
the
lower 8 bits of the 16 bit data are selected and with
A1 at V
IH
the upper 8 bits of the 16 bit data are
selected.
The M27C800 has two control functions, both of
which must be logically active in order to obtain
data at the outputs. In addition the Word-wide or
Byte- wide organisation must be selected.
Chip Enable (E) is the power control and should be
used for device selection. Output Enable (G) is the
output control and should be used to gate data to
the output pins independent of device selection.
Assuming that the addresses are stable, the ad-
dress access time (t
AVQV
) is equal to the delay
from E to output (t
ELQV
). Data is available at the
output after a delay of t
GLQV
from the falling edge
of G, assuming that E has been low and the ad-
dresses have been stable for at least t
AVQV
-t
GLQV
.
Table 5. AC Measurement Conditions
High Speed
Standard
Input Rise and Fall Times
10ns
20ns
Input Pulse Voltages
0 to 3V
0.4V to 2.4V
Input and Output Timing Ref. Voltages
1.5V
0.8V and 2V
Figure 3. AC Testing Input Output Waveform
AI01822
3V
High Speed
0V
1.5V
2.4V
Standard
0.4V
2.0V
0.8V
Figure 4. AC Testing Load Circuit
AI01823B
1.3V
OUT
CL
CL = 30pF for High Speed
CL = 100pF for Standard
CL includes JIG capacitance
3.3k
1N914
DEVICE
UNDER
TEST
5/18
M27C800
Table 7. Read Mode DC Characteristics
(1)
(T
A
= 0 to 70 C or 40 to 85 C; V
CC
= 5V 5% or 5V 10%; V
PP
= V
CC
)
Note: 1. V
CC
must be applied simultaneously with or before V
PP
and removed simultaneously or after V
PP
.
2. Maximum DC voltage on Output is V
CC
+ 0.5V.
Symbol
Parameter
Test Condition
Min
Max
Unit
I
LI
Input Leakage Current
0V
V
IN
V
CC
1
A
I
LO
Output Leakage Current
0V
V
OUT
V
CC
10
A
I
CC
Supply Current
E = V
IL
, G = V
IL
,
I
OUT
= 0mA, f = 8MHz
70
mA
E = V
IL
, G = V
IL
,
I
OUT
= 0mA, f = 5MHz
50
mA
I
CC1
Supply Current (Standby) TTL
E = V
IH
1
mA
I
CC2
Supply Current (Standby) CMOS
E > V
CC
0.2V
50
A
I
PP
Program Current
V
PP
= V
CC
10
A
V
IL
Input Low Voltage
0.3
0.8
V
V
IH
(2)
Input High Voltage
2
V
CC
+ 1
V
V
OL
Output Low Voltage
I
OL
= 2.1mA
0.4
V
V
OH
Output High Voltage TTL
I
OH
= 400A
2.4
V
Table 6. Capacitance
(1)
(T
A
= 25 C, f = 1 MHz)
Note: 1. Sampled only, not 100% tested.
Symbol
Parameter
Test Condition
Min
Max
Unit
C
IN
Input Capacitance (except BYTEV
PP
)
V
IN
= 0V
10
pF
Input Capacitance (BYTEV
PP
)
V
IN
= 0V
120
pF
C
OUT
Output Capacitance
V
OUT
= 0V
12
pF
Standby Mode
The M27C800 has a standby mode which reduces
the supply current from 50mA to 100A. The
M27C800 is placed in the standby mode by apply-
ing a CMOS high signal to the E input. When in the
standby mode, the outputs are in a high imped-
ance state, independent of the G input.
M27C800
6/18
Table 8A. Read Mode AC Characteristics
(1)
(T
A
= 0 to 70 C or 40 to 85 C; V
CC
= 5V 5% or 5V 10%; V
PP
= V
CC
)
Note: 1. V
CC
must be applied simultaneously with or before V
PP
and removed simultaneously or after V
PP.
2. Sampled only, not 100% tested.
3. Speed obtained with High Speed AC measurement conditions.
Table 8B. Read Mode AC Characteristics
(1)
(T
A
= 0 to 70 C or 40 to 85 C; V
CC
= 5V 5% or 5V 10%; V
PP
= V
CC
)
Note: 1. V
CC
must be applied simultaneously with or before V
PP
and removed simultaneously or after V
PP.
2. Sampled only, not 100% tested.
Symbol
Alt
Parameter
Test Condition
M27C800
Unit
-50
(3)
-70
-90
Min
Max
Min
Max
Min
Max
t
AVQV
t
ACC
Address Valid to Output
Valid
E = V
IL
, G = V
IL
50
70
90
ns
t
BHQV
t
ST
BYTE High to Output
Valid
E = V
IL
, G = V
IL
50
70
90
ns
t
ELQV
t
CE
Chip Enable Low to
Output Valid
G = V
IL
50
70
90
ns
t
GLQV
t
OE
Output Enable Low to
Output Valid
E = V
IL
30
35
45
ns
t
BLQZ
(2)
t
STD
BYTE Low to Output Hi-Z
E = V
IL
, G = V
IL
30
30
30
ns
t
EHQZ
(2)
t
DF
Chip Enable High to
Output Hi-Z
G = V
IL
0
30
0
30
0
30
ns
t
GHQZ
(2)
t
DF
Output Enable High to
Output Hi-Z
E = V
IL
0
30
0
30
0
30
ns
t
AXQX
t
OH
Address Transition to
Output Transition
E = V
IL
, G = V
IL
5
5
5
ns
t
BLQX
t
OH
BYTE Low to Output
Transition
E = V
IL
, G = V
IL
5
5
5
ns
Symbol
Alt
Parameter
Test Condition
M27C800
Unit
-100
-120/150
Min
Max
Min
Max
t
AVQV
t
ACC
Address Valid to Output Valid
E = V
IL
, G = V
IL
100
120
ns
t
BHQV
t
ST
BYTE High to Output Valid
E = V
IL
, G = V
IL
100
120
ns
t
ELQV
t
CE
Chip Enable Low to Output Valid
G = V
IL
100
120
ns
t
GLQV
t
OE
Output Enable Low to Output Valid
E = V
IL
50
60
ns
t
BLQZ
(2)
t
STD
BYTE Low to Output Hi-Z
E = V
IL
, G = V
IL
40
50
ns
t
EHQZ
(2)
t
DF
Chip Enable High to Output Hi-Z
G = V
IL
0
40
0
50
ns
t
GHQZ
(2)
t
DF
Output Enable High to Output Hi-Z
E = V
IL
0
40
0
50
ns
t
AXQX
t
OH
Address Transition to Output Transition
E = V
IL
, G = V
IL
5
5
ns
t
BLQX
t
OH
BYTE Low to Output Transition
E = V
IL
, G = V
IL
5
5
ns
7/18
M27C800
Figure 5. Word-Wide Read Mode AC Waveforms
Note: BYTEV
PP
= V
IH
.
AI01596B
tAXQX
tEHQZ
A0-A18
E
G
Q0-Q15
tAVQV
tGHQZ
tGLQV
tELQV
VALID
Hi-Z
VALID
Two Line Output Control
Because EPROMs are usually used in larger
memory arrays, this product features a 2-line con-
trol function which accommodates the use of mul-
tiple memory connection. The two-line control
function
allows:
a. the lowest possible memory power dissipation
b. complete assurance that output bus contention
will not occur.
For the most efficient use of these two control
lines, E should be decoded and used as the prima-
ry device selecting function, while G should be
made a common connection to all devices in the
array and connected to the READ line from the
system control bus. This ensures that all deselect-
ed memory devices are in their low power standby
mode and that the output pins are only active
when data is required from a particular memory
device.
System Considerations
The power switching characteristics of Advanced
CMOS EPROMs require careful decoupling of the
supplies to the devices. The supply current I
CC
has three segments of importance to the system
designer: the standby current, the active current
and the transient peaks that are produced by the
falling and rising edges of E.
The magnitude of the transient current peaks is
dependent on the capacitive and inductive loading
of the device outputs. The associated transient
voltage peaks can be suppressed by complying
with the two line output control and by properly se-
lected decoupling capacitors. It is recommended
that a 0.1F ceramic capacitor is used on every
device between V
CC
and V
SS
.
This should be a high frequency type of low inher-
ent inductance and should be placed as close as
possible to the device. In addition, a 4.7F electro-
lytic capacitor should be used between V
CC
and
V
SS
for every eight devices. This capacitor should
be mounted near the power supply connection
point. The purpose of this capacitor is to overcome
the voltage drop caused by the inductive effects of
PCB traces.
M27C800
8/18
Figure 6. Byte-Wide Read Mode AC Waveforms
Note: BYTEV
PP
= V
IL.
Figure 7. BYTE Transition AC Waveforms
Note: Chip Enable (E) and Output Enable (G) = V
IL
.
AI01597B
tAXQX
tEHQZ
A1,A0-A18
E
G
Q0-Q7
tAVQV
tGHQZ
tGLQV
tELQV
VALID
Hi-Z
VALID
AI01598C
tAXQX
tBHQV
A0-A18
BYTEVPP
tAVQV
tBLQX
tBLQZ
VALID
Hi-Z
A1
DATA OUT
DATA OUT
VALID
Q0-Q7
Q8-Q15
9/18
M27C800
Table 9. Programming Mode DC Characteristics
(1)
(T
A
= 25 C; V
CC
= 6.25V 0.25V; V
PP
= 12.5V 0.25V)
Note: 1. V
CC
must be applied simultaneously with or before V
PP
and removed simultaneously or after V
PP
.
Table 10. Programming Mode AC Characteristics
(1)
(T
A
= 25 C; V
CC
= 6.25V 0.25V; V
PP
= 12.5V 0.25V)
Note: 1. V
CC
must be applied simultaneously with or before V
PP
and removed simultaneously or after V
PP
.
2. Sampled only, not 100% tested.
Symbol
Parameter
Test Condition
Min
Max
Unit
I
LI
Input Leakage Current
0
V
IN
V
CC
1
A
I
CC
Supply Current
50
mA
I
PP
Program Current
E = V
IL
50
mA
V
IL
Input Low Voltage
0.3
0.8
V
V
IH
Input High Voltage
2.4
V
CC
+ 0.5
V
V
OL
Output Low Voltage
I
OL
= 2.1mA
0.4
V
V
OH
Output High Voltage TTL
I
OH
= 2.5mA
3.5
V
V
ID
A9 Voltage
11.5
12.5
V
Symbol
Alt
Parameter
Test Condition
Min
Max
Unit
t
AVEL
t
AS
Address Valid to Chip Enable Low
2
s
t
QVEL
t
DS
Input Valid to Chip Enable Low
2
s
t
VPHAV
t
VPS
V
PP
High to Address Valid
2
s
t
VCHAV
t
VCS
V
CC
High to Address Valid
2
s
t
ELEH
t
PW
Chip Enable Program Pulse Width
45
55
s
t
EHQX
t
DH
Chip Enable High to Input Transition
2
s
t
QXGL
t
OES
Input Transition to Output Enable Low
2
s
t
GLQV
t
OE
Output Enable Low to Output Valid
120
ns
t
GHQZ
(2)
t
DFP
Output Enable High to Output Hi-Z
0
130
ns
t
GHAX
t
AH
Output Enable High to Address
Transition
0
ns
Programming
When delivered (and after each erasure for UV
EPROM), all bits of the M27C800 are in the '1'
state. Data is introduced by selectively program-
ming '0's into the desired bit locations. Although
only '0's will be programmed, both '1's and '0's can
be present in the data word. The only way to
change a '0' to a '1' is by die exposition to ultravio-
let light (UVEPROM). The M27C800 is in the pro-
gramming mode when V
PP
input is at 12.5V, G is
at V
IH
and E is pulsed to V
IL
. The data to be pro-
grammed is applied to 16 bits in parallel to the data
output pins. The levels required for the address
and data inputs are TTL. V
CC
is specified to be
6.25V 0.25V.
M27C800
10/18
Figure 8. Programming and Verify Modes AC Waveforms
tAVEL
VALID
AI01599
A0-A18
Q0-Q15
BYTEVPP
VCC
G
DATA IN
DATA OUT
E
tQVEL
tVPHAV
tVCHAV
tEHQX
tELEH
tGLQV
tQXGL
tGHQZ
tGHAX
PROGRAM
VERIFY
Figure 9. Programming Flowchart
AI01044B
n = 0
Last
Addr
VERIFY
E = 50
s Pulse
++n
= 25
++ Addr
VCC = 6.25V, VPP = 12.5V
FAIL
CHECK ALL WORDS
BYTEVPP =VIH
1st: VCC = 6V
2nd: VCC = 4.2V
YES
NO
YES
NO
YES
NO
PRESTO III Programming Algorithm
The PRESTO III Programming Algorithm allows
the whole array to be programed with a guaran-
teed margin in a typical time of 26 seconds. Pro-
gramming with PRESTO III consists of applying a
sequence of 50s program pulses to each word
until a correct verify occurs (see Figure 9). During
programing and verify operation a MARGIN
MODE circuit is automatically activated to guaran-
tee that each cell is programed with enough mar-
gin. No overprogram pulse is applied since the
verify in MARGIN MODE provides the necessary
margin to each programmed cell.
Program Inhibit
Programming of multiple M27C800s in parallel
with different data is also easily accomplished. Ex-
cept for E, all like inputs including G of the parallel
M27C800 may be common. A TTL low level pulse
applied to a M27C800's E input and V
PP
at 12.5V,
will program that M27C800. A high level E input in-
hibits the other M27C800s from being pro-
grammed.
Program Verify
A verify (read) should be performed on the pro-
grammed bits to determine that they were correct-
ly programmed. The verify is accomplished with E
at V
IH
and G at V
IL
, V
PP
at 12.5V and V
CC
at
6.25V.
11/18
M27C800
Electronic Signature
The Electronic Signature (ES) mode allows the
reading out of a binary code from an EPROM that
will identify its manufacturer and type. This mode
is intended for use by programming equipment to
automatically match the device to be programmed
with its corresponding programming algorithm.
The ES mode is functional in the 25C 5C am-
bient temperature range that is required when pro-
gramming the M27C800. To activate the ES
mode, the programming equipment must force
11.5V to 12.5V on address line A9 of the
M27C800, with V
PP
= V
CC
= 5V. Two identifier
bytes may then be sequenced from the device out-
puts by toggling address line A0 from V
IL
to V
IH
. All
other address lines must be held at V
IL
during
Electronic Signature mode.
Byte 0 (A0 = V
IL
) represents the manufacturer
code and byte 1 (A0 = V
IH
) the device identifier
code. For the STMicroelectronics M27C800, these
two identifier bytes are given in Table 4 and can be
read-out on outputs Q7 to Q0.
ERASURE OPERATION (applies to UV EPROM)
The erasure characteristics of the M27C800 is
such that erasure begins when the cells are ex-
posed to light with wavelengths shorter than ap-
proximately 4000 . It should be noted that
sunlight and some type of fluorescent lamps have
wavelengths in the 3000-4000 range. Research
shows that constant exposure to room level fluo-
rescent lighting could erase a typical M27C800 in
about 3 years, while it would take approximately 1
week to cause erasure when exposed to direct
sunlight. If the M27C800 is to be exposed to these
types of lighting conditions for extended periods of
time, it is suggested that opaque labels be put over
the M27C800 window to prevent unintentional era-
sure. The recommended erasure procedure for
M27C800 is exposure to short wave ultraviolet
light which has a wavelength of 2537 . The inte-
grated dose (i.e. UV intensity x exposure time) for
erasure should be a minimum of 30 W-sec/cm
2
.
The erasure time with this dosage is approximate-
ly 30 to 40 minutes using an ultraviolet lamp with
12000 W/cm
2
power rating. The M27C800
should be placed within 2.5cm (1 inch) of the lamp
tubes during the erasure. Some lamps have a filter
on their tubes which should be removed before
erasure.
M27C800
12/18
Table 11. Ordering Information Scheme
Note: 1. High Speed, see AC Characteristics section for further information.
For a list of available options (Speed, Package, etc...) or for further information on any aspect of this de-
vice, please contact the STMicroelectronics Sales Office nearest to you.
Example:
M27C800
-50
X
M
1
TR
Device Type
M27
Supply Voltage
C = 5V
Device Function
800 = 8 Mbit (1Mb x8 or 512Kb x16)
Speed
-50
(1)
= 50 ns
-70 = 70 ns
-90 = 90 ns
-100 = 100 ns
-120 = 120 ns
-150 = 150 ns
V
CC
Tolerance
blank = 10%
X = 5%
Package
F = FDIP42W
B = PDIP42
K = PLCC44
M = SO44
Temperature Range
1 = 0 to 70 C
6 = 40 to 85 C
Options
TR = Tape & Reel Packing
13/18
M27C800
Table 1. Revision History
Date
Revision Details
March 1999
First Issue
25-Jan-2000
50ns speed class addes (Tables 8A and 11)
Electronic Signature change (Table 4)
FDIP42W Package Dimension, L Max added (Table 12)
25-Sep-2000
AN620 Reference removed
10-Dec-2001
Ordering Information Scheme (Table 11) clarified
M27C800
14/18
Table 12. FDIP42W - 42 pin Ceramic Frit-seal DIP, with window, Package Mechanical Data
Symbol
millimeters
inches
Typ
Min
Max
Typ
Min
Max
A
5.72
0.225
A1
0.51
1.40
0.020
0.055
A2
3.91
4.57
0.154
0.180
A3
3.89
4.50
0.153
0.177
B
0.41
0.56
0.016
0.022
B1
1.45
0.057
C
0.23
0.30
0.009
0.012
D
54.41
54.86
2.142
2.160
D2
50.80
2.000
E
15.24
0.600
E1
14.50
14.90
0.571
0.587
e
2.54
0.100
eA
14.99
0.590
eB
16.18
18.03
0.637
0.710
L
3.18
4.10
0.125
0.161
S
1.52
2.49
0.060
0.098
K
9.40
0.370
K1
11.43
0.450
4
11
4
11
N
42
42
Figure 10. FDIP42W - 42 pin Ceramic Frit-seal DIP, with window, Package Outline
Drawing is not to scale.
FDIPW-b
A3
A1
A
L
B1
B
e1
D
S
E1
E
N
1
C
eA
D2
K
K1
eB
A2
15/18
M27C800
Table 13. PDIP42 - 42 pin Plastic DIP, 600 mils width, Package Mechanical Data
Symbol
millimeters
inches
Typ
Min
Max
Typ
Min
Max
A
5.08
0.200
A1
0.25
0.010
A2
3.56
4.06
0.140
0.160
B
0.38
0.53
0.015
0.021
B1
1.27
1.65
0.050
0.065
C
0.20
0.36
0.008
0.014
D
52.20
52.71
2.055
2.075
D2
50.80
2.000
E
15.24
0.600
E1
13.59
13.84
0.535
0.545
e1
2.54
0.100
eA
14.99
0.590
eB
15.24
17.78
0.600
0.700
L
3.18
3.43
0.125
0.135
S
0.86
1.37
0.034
0.054
0
10
0
10
N
42
42
Figure 11. PDIP42 - 42 pin Plastic DIP, 600 mils width, Package Outline
Drawing is not to scale.
PDIP
A2
A1
A
L
B1
B
e1
D
S
E1
E
N
1
C
eA
eB
D2
M27C800
16/18
Table 14. PLCC44 - 44 lead Plastic Leaded Chip Carrier, Package Mechanical Data
Symbol
millimeters
inches
Typ
Min
Max
Typ
Min
Max
A
4.20
4.70
0.165
0.185
A1
2.29
3.04
0.090
0.120
A2
0.51
0.020
B
0.33
0.53
0.013
0.021
B1
0.66
0.81
0.026
0.032
D
17.40
17.65
0.685
0.695
D1
16.51
16.66
0.650
0.656
D2
14.99
16.00
0.590
0.630
E
17.40
17.65
0.685
0.695
E1
16.51
16.66
0.650
0.656
E2
14.99
16.00
0.590
0.630
e
1.27
0.050
F
0.00
0.25
0.000
0.010
R
0.89
0.035
N
44
44
CP
0.10
0.004
Figure 12. PLCC44 - 44 lead Plastic Leaded Chip Carrier, Package Outline
Drawing is not to scale.
PLCC
D
Ne
E1 E
1 N
D1
Nd
CP
B
D2/E2
e
B1
A1
A
R
0.51 (.020)
1.14 (.045)
F
A2
17/18
M27C800
Figure 13. SO44 - 44 lead Plastic Small Outline, 525 mils body width, Package Outline
Drawing is not to scale.
SO-b
E
N
CP
B
e
A2
D
C
L
A1
H
A
1
Table 15. SO44 - 44 lead Plastic Small Outline, 525 mils body width, Package Mechanical Data
Symbol
millimeters
inches
Typ
Min
Max
Typ
Min
Max
A
2.42
2.62
0.095
0.103
A1
0.22
0.23
0.009
0.010
A2
2.25
2.35
0.089
0.093
B
0.50
0.020
C
0.10
0.25
0.004
0.010
D
28.10
28.30
1.106
1.114
E
13.20
13.40
0.520
0.528
e
1.27
0.050
H
15.90
16.10
0.626
0.634
L
0.80
0.031
3
3
N
44
44
CP
0.10
0.004
M27C800
18/18
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
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