L6605

SMART CARD INTERFACE

ADVANCE DATA

8 DIFFERENT VPP OUTPUT VOLTAGE
LEVELS
V

, V

RISE AND FALL TIME FULL SPEC

WITH ISO/IEC 7816-3
POWER SUPPLY OUTPUT FOR MEMORY
CARD (5V/80mA)
POWER ON/OFF RESET
AUTOMATIC SWITCH-OFF OF ALL FUNCTIONS
IF THE REGULAR OPERATION IS ABORTED
BY EXTRACTING THE SMART CARD
INTERNAL STATUS FAILURE CODING
- INSERTION FAILURE CODE
- OVERTEMPERATURE FAILURE
ANTI-BOUNCING SYSTEM
INPUT/OUTPUT LOGIC TTL COMPATIBLE
THERMAL PROTECTION

DESCRIPTION
The L6605 is an IC dedicated as intelligent inter-
face between different types of smart cards and
microprocessors. The internal architecture can be
shared in a power supply section and in a diag-
nostic parts.
The power supply section can deliver 5V/80mA to

supply the card and V

/50mA to write the mem-

ory inside the card; the V

voltage can be pro-

grammed by means of the 3 serial input bit (see
TAB, 1).
Table 1: 3 bit DAC CODE

CODE

0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1

10V

12.5V
13.5V

15V
18V
21V
25V

This is advanced information on a new product now in development or undergoing evaluation. Details are subject to change without notice.

December 1992

BLOCK DIAGRAM

Powerdip 12+3+3

SO 12+4+4

ORDERING NUMBERS:

L6605

L6605D

MULTIPOWER BCD TECHNOLOGY

1/10

DESCRIPTION (continued)
The diagnostic part allows to monitor failures due
to overtemperature or wrong card positioning.
The failures are internally coded and readable in-
side the STATUS REGISTER through the bidirec-

tional pin DATA configurated in output.
The antibouncing circuitry, active during card in-
sertion only, rejects ripetitive switching-on of the
power supply sections.

PIN FUNCTION

Pin

Description

Input Power Supply voltage for V

regulated output and for device supply.

CSO

Output regulated voltage for card supply; I

CSmax

= 80mA; overload protected (81 to 200mA)

PPIN

Input power supply for V

regulated voltage

PPOUT

Programmable output regulated voltage for memory card writing; 8 voltage levels are allowed by
means of 3 bit DAC. I

PPmax

= 50mA.

CSEN

(Active Low) V

supply input enable; Its value is fixed from the

P allowing or not the normal R/W

operations on the card.

SWIT CH

Input signal produced by the reader system indicating that a card has been inserted. Internally, an
antibouncing system is provided to avoid multiple switching.

Chip select (active low). CS low level indicates an I/O operation request from

IRQ

Interrupt Request (Active low).
An IRQ low level indicates that a card insertion/extraction or Failure has occured.

PRG

Program (Active low).
PRG low level enables L6605 to deliver in output the V

PPO

level set by 3 bit DAC.

DATA

I/O pin for data exchange between

P and the device. Through this pin flow 3 bit input DAC or 2 bit

STATUS REGISTER code.

External clock.

EXT

Pin to connect an external capacitor for antibouncing delay time.

GND

4 pins to ground.

PIN CONNECTIONS (Top view)

Powerdip 12+3+3

SO 12+4+4

THERMAL DATA

Symbol

Parameter

L6605

L6605D

Unit

th j-amb

Thermal Resistance Junction to Ambient

50 (*)

C/W

(*) Soldered an a 35

thick 6cm

P.C. board copper area.

L6605

2/10

CIRCUIT OPERATION

CARD POWER SUPPLY
Regulated voltage to supply the card (5V/80mA).
During nominal condition (V

= 12V, I

= 80mA)

the V

range variation is equal to + 3%.

While during line/load variation (V

= 10V to 15V;

= 1mA to 80mA) the V

range is + 5%.

An internal circuitry checks the I

level; the pro-

tection block activates an IRQ with the proper fail-
ure code when the output current is in 81mA to
200mA range.
PROGRAMMING POWER SUPPLY
L6605 works in step-down mode by means of the
programmed output voltage V

. 8V

levels can

be selected programming the 3 bit DAC as per
Table 1. During nominal conditions (I

= 50mA;

PPI

= 30V) the V

range variation is equal to

ELECTRICAL CHARACTERISTICS (V

= 12V; T

= 25

Symbol

Parameter

Test Condition

Min.

Typ.

Max.

Unit

Supply Voltage

Card Supply Voltage
(Logic Inputs onset)

= 80mA, V

= 12V

= 1mA to 80mA

= 10V to 15V

LOAD min

= 5nF; C

LOAD max

= 20

4.85

4.75

5.15

5.25

Current Supply Card

CSS

Short Circuit

= 12V

200

PPI

Supply Voltage

PPO

2.5V

PPO

Programming Voltage

= 50mA; V

PPI

= 30V;

< 5ms

= 1mA to 50mA

PPI

= max. 33V (see note 1)

LOAD min

= 5nF

LOAD max

= 500nF (see note 2)

-2.5%

-5%

DAC

+2.5%

+5%

Output Program. Current

PPI

= 30V

PPs

Short Circuit

150

, Rise Time

LOAD min

= 5nF

LOAD max

= 500nF (see note 2)

= 50mA (see note 1)

200

off

, Fall Time

200

shadow

Shadow Timing

Cbounce = 0.1

SWLOW

Low Level Switch Input

0.8

SWHIGH

High Level Switch Input

Vs-2V

CKON

Clock ON Time

LOAD

= 50pF, I

SINK

= 4mA,

= 0.4V

CKOFF

Clock OFF Time

Delay Time

250

SET-UP1

1st bit Set-up Time

500

HOLD1

1st bit Hold Time

500

CKON

SET-UP2

Data Set-up Time

500

HOLD2

Data Hold Time

500

SCK

Clock Set-up Time

250

HCK

Clock Hold Time

250

Clock Frequency

500

KHz

Slew Rate

From rest state to
programming state and
viceversa

STH

Power ON/OFF Threshold

Logic inputs onset

8.5

9.5

SHY

STH

Hysteresis

0.6

Thermal Shutdown

180

Thermal Hysteresis

Note 1: True for values in Tab. 1 only. ;

Note 2: Values higher than 500nF are permitted, but the ton, toff timing will be out ISO norm.

L6605

3/10

2.5%; while during line/load variation (I

= 1mA

to 50mA; V

PPI

= max. 33V) the V

range is

5%.

An internal circuitry checks the I

level; the pro-

tection block activates an IRQ with the proper fail-
ure code when the output current is in 51mA to
150mA range. Under the power ON/OFF thresh-
old value the logic section and the power supply
regulators are disabled.

LOGIC SECTION
L6605 includes a logic circuitry in order to protect,
both card and itself. If a failure occours an asyn-
chronous IRQ is sent to the

P; consequently the

P forces low CS signal as I/O request. After CS

variation the

P sends also one "data direction

bit" into DATA DIRECTION REGISTER.

Direction bit = "0"
Pin DATA is configurated in output and the

reads the 2 bit STATUS REGISTER content

Code

1st bit

2nd bit

No insertion

No Failure

Card Inserted

Failure

Failure could be overtemperature over the 2 regu-
lators (VPP, VCS).

Direction bit = "1"
Pin DATA is configurated in input to allow the 3
bit DAC loading and than the programming of
V

PPo

output level voltage. (see Table 1).

During card insertion only rising edge of switch
signal is detected , while during card extraction
switch level is detected.
In card extraction mode if occours a mechanical
switch bouncing, which causes a pulse on
SWITCH input pin with duration t

s the

L6605 will have the 1st Status Register content
equal to "0" and 1 ms t

shadow

timing like during

card insertion mode.
Bouncing on SWITCH pin with duration T<50

will be transparent in the Status Register.

Figure 1: Card Insertion

L6605

4/10

Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsibility for the
consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No
license is granted by implication or otherwise under any patent or patent rights of SGS-THOMSON Microelectronics. Specifications men-
tioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied.
SGS-THOMSON Microelectronics products are not authorized for use as critical components in life support devices or systems without ex-
press written approval of SGS-THOMSON Microelectronics.

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L6605

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