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September 2002
s
STANDARDIZED SYMMETRICAL OUTPUT
CHARACTERISTICS
s
QUIESCENT CURRENT SPECIFIED UP TO
20V
s
5V, 10V AND 15V PARAMETRIC RATINGS
s
INPUT LEAKAGE CURRENT
I
I
= 100nA (MAX) AT V
DD
= 18V T
A
= 25C
s
100% TESTED FOR QUIESCENT CURRENT
s
MEETS ALL REQUIREMENTS OF JEDEC
JESD13B "STANDARD SPECIFICATIONS
FOR DESCRIPTION OF B SERIES CMOS
DEVICES"
DESCRIPTION
HCF40101B is a monolithic integrated circuit
fabricated in Metal Oxide Semiconductor
technology available in DIP and SOP packages.
HCF40101B is a 9-bit (8 data bits plus 1 parity bit)
parity generator/checker. It may be used to detect
errors in data transmission or data retrieval. Odd
and even outputs facilitate odd or even parity
generation and checking. When used as a parity
generator, a parity bit is supplied along with the
data to generate an even or odd parity output.
When used as a parity checker, the received data
bits and parity bits are compared for correct parity.
The even or odd outputs are used to indicate an
error in the received data. Word-length capability
is expandable by cascading. HCF40101B is also
provided with an inhibit control. If the inhibit control
is set at logical "1", the even and odd outputs go to
a logical "0"
HCF40101B
9 BIT PARITY GENERATOR CHECKER
PIN CONNECTION
ORDER CODES
PACKAGE
TUBE
T & R
DIP
HCF40101BEY
SOP
HCF40101BM1
HCF40101M013TR
DIP
SOP
HCF40101B
2/9
INPUT EQUIVALENT CIRCUIT
PIN DESCRIPTION
TRUTH TABLE
X : Don"t Care
FUNCTIONAL DIAGRAM
PIN No
SYMBOL
NAME AND FUNCTION
1, 2, 3, 4, 10,
11, 12, 13, 5
D1 to D9
Data Inputs
8
INHIBIT
Inhibit Control Input
9
EVEN OUT
Even Output
6
ODD OUT
Odd Output
7
V
SS
Negative Supply Voltage
14
V
DD
Positive Supply Voltage
INPUTS
OUTPUTS
D1 - D9
INHIBIT
EVEN
ODD
1's = Even
L
H
L
1's = Odd
L
L
H
X
H
L
L
HCF40101B
3/9
LOGIC DIAGRAM
ABSOLUTE MAXIMUM RATINGS
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is
not implied.
All voltage values are referred to V
SS
pin voltage.
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Value
Unit
V
DD
Supply Voltage
-0.5 to +22
V
V
I
DC Input Voltage
-0.5 to V
DD
+ 0.5
V
I
I
DC Input Current
10
mA
P
D
Power Dissipation per Package
200
mW
Power Dissipation per Output Transistor
100
mW
T
op
Operating Temperature
-55 to +125
C
T
stg
Storage Temperature
-65 to +150
C
Symbol
Parameter
Value
Unit
V
DD
Supply Voltage
3 to 20
V
V
I
Input Voltage
0 to V
DD
V
T
op
Operating Temperature
-55 to 125
C
HCF40101B
4/9
DC SPECIFICATIONS
The Noise Margin for both "1" and "0" level is: 1V min. with V
DD
=5V, 2V min. with V
DD
=10V, 2.5V min. with V
DD
=15V
Symbol
Parameter
Test Condition
Value
Unit
V
I
(V)
V
O
(V)
|I
O
|
(
A)
V
DD
(V)
T
A
= 25C
-40 to 85C
-55 to 125C
Min.
Typ.
Max.
Min.
Max.
Min.
Max.
I
L
Quiescent Current
0/5
5
0.04
5
150
150
A
0/10
10
0.04
10
300
300
0/15
15
0.04
20
600
600
0/20
20
0.08
100
3000
3000
V
OH
High Level Output
Voltage
0/5
<1
5
4.95
4.95
4.95
V
0/10
<1
10
9.95
9.95
9.95
0/15
<1
15
14.95
14.95
14.95
V
OL
Low Level Output
Voltage
5/0
<1
5
0.05
0.05
0.05
V
10/0
<1
10
0.05
0.05
0.05
15/0
<1
15
0.05
0.05
0.05
V
IH
High Level Input
Voltage
0.5/4.5
<1
5
3.5
3.5
3.5
V
1/9
<1
10
7
7
7
1.5/13.5
<1
15
11
11
11
V
IL
Low Level Input
Voltage
4.5/0.5
<1
5
1.5
1.5
1.5
V
9/1
<1
10
3
3
3
13.5/1.5
<1
15
4
4
4
I
OH
Output Drive
Current
0/5
2.5
<1
5
-1.36
-3.2
-1.15
-1.1
mA
0/5
4.6
<1
5
-0.44
-1
-0.36
-0.36
0/10
9.5
<1
10
-1.1
-2.6
-0.9
-0.9
0/15
13.5
<1
15
-3.0
-6.8
-2.4
-2.4
I
OL
Output Sink
Current
0/5
0.4
<1
5
0.44
1
0.36
0.36
mA
0/10
0.5
<1
10
1.1
2.6
0.9
0.9
0/15
1.5
<1
15
3.0
6.8
2.4
2.4
I
I
Input Leakage
Current
0/18
Any Input
18
10
-5
0.1
1
1
A
C
I
Input Capacitance
Any Input
5
7.5
pF
HCF40101B
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DYNAMIC ELECTRICAL CHARACTERISTICS (T
amb
= 25C, C
L
= 50pF, R
L
= 200K
, t
r
= t
f
= 20 ns)
(*) Typical temperature coefficient for all V
DD
value is 0.3 %/C.
TEST CIRCUIT
C
L
= 50pF or equivalent (includes jig and probe capacitance)
R
L
= 200K
R
T
= Z
OUT
of pulse generator (typically 50
)
Symbol
Parameter
Test Condition
Value (*)
Unit
V
DD
(V)
Min.
Typ.
Max.
t
PLH
t
PHL
Propagation Delay Time
5
350
700
ns
10
150
300
15
100
200
t
PLH
t
PHL
Propagation Delay Time
(INHIBIT to OUTPUT)
5
140
280
ns
10
70
140
15
50
100
t
TLH
t
THL
Transition Time
5
100
200
ns
10
50
100
15
40
80
HCF40101B
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WAVEFORM : PROPAGATION DELAY TIMES (f=1MHz; 50% duty cycle)
HCF40101B
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DIM.
mm.
inch
MIN.
TYP
MAX.
MIN.
TYP.
MAX.
a1
0.51
0.020
B
1.39
1.65
0.055
0.065
b
0.5
0.020
b1
0.25
0.010
D
20
0.787
E
8.5
0.335
e
2.54
0.100
e3
15.24
0.600
F
7.1
0.280
I
5.1
0.201
L
3.3
0.130
Z
1.27
2.54
0.050
0.100
Plastic DIP-14 MECHANICAL DATA
P001A
HCF40101B
8/9
DIM.
mm.
inch
MIN.
TYP
MAX.
MIN.
TYP.
MAX.
A
1.75
0.068
a1
0.1
0.2
0.003
0.007
a2
1.65
0.064
b
0.35
0.46
0.013
0.018
b1
0.19
0.25
0.007
0.010
C
0.5
0.019
c1
45 (typ.)
D
8.55
8.75
0.336
0.344
E
5.8
6.2
0.228
0.244
e
1.27
0.050
e3
7.62
0.300
F
3.8
4.0
0.149
0.157
G
4.6
5.3
0.181
0.208
L
0.5
1.27
0.019
0.050
M
0.68
0.026
S
(max.)
SO-14 MECHANICAL DATA
PO13G
8
HCF40101B
9/9
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the
consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from
its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications
mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information
previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or
systems without express written approval of STMicroelectronics.
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