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CB65000 Series
March 2002
FEATURE
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0.18 micron drawn, six layers of metal connected
by fully stackable vias and contacts, Shallow
Trench Isolation, low resistance, salicided
active areas and gates. Deep UV lithography.
s
1.8 V optimized High Performance and Low
Leakage transistors with 3.3 V I/O and supply
interface capability.
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Average gate density: 85K/mm
2
, plus low power
consumption of 30nanoWatt/Gate/MHz/
Stdload.
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Two input NAND delay of 35ps with High
Performane transistor and 60ps with Low
Leakage transistor.
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Library available in commercial, industrial and
military temperature range. Power supply
ranging from 1.2V and 1.95V for Core
(according to JESD 8-7 specification) and
between 3.0V and 3.6V for I/Os (alligned with
JESD 8-A specification).
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Broad I/O functionality including:
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Low Voltage CMOS.
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Low Voltage TTL,HSTL, SSTL.
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AGP 2X and 4X, USB, PCI, LVDS I/O interfaces
are also available.
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Drive capability up to 8 mA per buffer with slew
rate control, current spike suppression
impedance matching, and process
compensation capability to reduce delay
variation.
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Designs easily portable from previous
generations of CB55000 with an average factor
2 density increase, 30% speed improvement
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and 2.5 power reduction at respective nominal
voltages.
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Generators to support Single Port, Dual port
and multiple Port RAM, and ROMs with BIST
options.
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Extensive embedded function library including
ST DSP and micro-cores, third-party IPs,
Synopsys and Mentor Inventra synthetic
libraries ideally suited for complete System On
Chip fast integration .
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Embedded DRAM Capability
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80
m pitch linear and 50
m staggered pad
libraries.
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Fully independent power and ground
configuration for core and I/Os supported.
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I/O ring capability up to 1500 pads.
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Latch-up trigger current > 500 mA. ESD
protection above 4 kV in H.B.M.
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Oscillators and PLLs for wide frequency
spectrum.
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Broad range of more than 600 SSI cells.
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Design for test features including IEEE 1149.1
JTAG Boundary Scan architecture.
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Synopsys, Cadence and Mentor based design
systems with interface from multiple
workstations.
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Broad range of packaging solutions, including
PBGA, LBGA, SBGA, HPBGA, TQFP, PQFP,
PLCC up to 1000 pins with enhanced power
dissipation options.
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1.25 GigaHertzGigabit DLL technique.
CB65000 Super Integration
Cost Effective Product
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Architecture partitioning
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Trouble-free integration
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Application-specific
Your Product is Unique
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User specified cell integration
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Design confidentiality
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IP fully re-usable
HCMOS8D 0.18
m Standard Cells Family
CB65000 SERIES
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Figure 1. Process cross section and Interconnect perspective view
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CB65000 SERIES
1
GENERAL DESCRIPTION
The CB65000 standard cell series uses a high performance, low-voltage, 0.18
m drawn, six metal levels, high
density and high speed HCMOS8D process.
With an average routed gate density of 85,000 gates/mm
2
, the CB65000 family allows the integration of up to
30 million equivalent gates and is ideal for high-complexity or high-performance devices for computer, telecom-
munication and consumer products.
With a gate delay of 35 ps with High Performance transistor and 60 ps with Low Leakage transistor (for a 2-input
NAND gate at fan-out 1), the library meets the most demanding speed requirements in telecommunication and
computer application designs today.
Optimized for 1.8 V operation, the library features a power consumption of less than 35 nW/Gate/MHz (High
Performance; fan-out=1) and 25 nW/Gate/MHz (Low Leakage; fan-out=1) at 1.8 V.
The I/O buffers can be fully configured for both 1.8 V and 3.3 V interface options, with several high speed buffer
types available. These include: low voltage differential (LVDS) I/Os, PCI, AGP, USB, LVTTL, LVCMOS and SSTL.
The pad pitch down to 50
m, in a staggered arrangement, meets the requirements of high pin-count devices
which tend to become pad-limited at such library densities. For very high pin-count ICs, advanced solutions such
as Ball Grid Array packages are available.
New packaging solutions using a flip-chip approach are currently being developed.
Figure 2. HCMOS8D Front end cross section
CB65000 SERIES
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2
TECHNOLOGY OVERVIEW
The advanced HCMOS8D transistor architecture: at 0.18
m, very thin gate oxide: 35 Amstrong, optimized
threshold voltages and salicided source, drain, and gate leads to intrinsically high performances in both
N channel and P channel driving currents.
The major scaling factor is obtained through deep UV lithography at most masking levels, making sub-micron
pitch a reality.
Further integration in the process front-end comes from the use of the Shallow Trench Isolation process be-
tween active regions, both improving density and planarity of transistors. In order to allow full utilization of such
transistor density, up to 6 levels of metal are made available for routing.
The local interconnection level made in Tungsten, allows short interconnection at silicon layer improving mem-
ory and cell density., while all the six metal levels are of low resistivity aluminum for long range interconnection
and power distribution.
Figure 3. HCMOS8D Local Interconnect
The thick inter-level dielectric is completely planarized by Chemical Mechanical Polishing, which provides de-
fect-free isolation between stripes within the same as well as between different levels.
Usage of Tungsten plugs at contacts and vias allows extremely dense and reliable interconnection between
metal layers. These vias and contacts are fully stackable, providing a direct vertical electrical connection from
the active level up to the sixth metal level. This efficient interconnect scheme makes routing fast and easy, as
well as having a very positive impact on high gate count, random-logic blocks density and routability.
The combination of both high drive and dense transistors, easily interconnected with up to six fine-pitch metal
levels and isolated by thick and low K dielectric leads to an optimum gate density, with low parasitic resistance
and capacitance. This results in very short interconnected gate delay and minimized power consumption.
Figure 4.
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CB65000 SERIES
3
LIBRARY
The CB55000 library is organized into three categories:
SSI cell library
I/O cell library
Macrofunctions
3.1 SSI Cell Library Overview
The design of the CB65000 family has been optimized to allow extremely high density, high speed and low pow-
er designs. For these reasons, a wide range of cells with different ranges of driving capabilities are available in
the library.
The library cells have been optimized in terms of functional and electrical parameters, in order to have:
Good balancing
Maximum speed
Optimum threshold voltage
Symmetric V
dd
/V
ss
noise margins
Minimum power-speed value
The geometrical aspect of the cells is configured to allow an extremely dense design, fully exploiting the features
of the Place and Route tool in terms of horizontal and vertical routing grids. For Place and Route, up to six layers
of metal are utilized; the firsts four layers fully available for signal routing, while the fifth and sixth to power dis-
tribution, clock bussing and routing.
Figure 5. NR2 and F/F examples from CB65000
3.2 Core Logic
The propagation delays shown in CB65000 data book are given for worst case processing at 1.55V and 125C
and will be provided in the design while power data are referred to a fast process model at 1.95V and -40C.
However, there are additional factors that affect the delay characteristics of the cells. These include: loading
due to fanout and interconnect routing, supply voltage, junction temperature of the device, processing tolerance
and input signal transition time.
Prior to physical layout, the design system can estimate the delays associated with any critical path. The impact
of the placement and routing can be accurately RC back-annotated from the layout for final simulations of critical
timing. The median effects on the cells delay of junction temperature (Kt coefficient) and supply voltage (Kv co-
efficient) are extracted from real Silicon data.
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