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CB55000 Series
February 2002
FEATURE
s
0.25 micron drawn (0.20 micron effective
channel length process), six layers of metal
connected by fully stackable vias and contacts,
Shallow Trench Isolation, low resistance,
salicided active areas and gates. Deep UV
lithography.
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2.5 V optimized transistor with 3.3 V I/O and
supply interface capability.
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Average gate density: 30 K/mm2, plus low
power consumption of 70 nanoWatt/Gate/MHz/
Stdload.
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Two input NAND delay of 90 pS (typical) with
fanout=2.
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Library available in commercial, industrial and
military temperature range with supply ranging
from 2.70 V down to 1.8 V for the core
according to EIA/JESD 8-5 specification.
Additional low voltage range down to 1.5 V for
very low voltage/low power applications
supported
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Broad I/O functionality including:
Low Voltage CMOS.
Low Voltage TTL, PECL, HSTL, SSTL,
LVDS, PCI.
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AGP 2X and 4X, USB to support 2.5 V and 3.3
V I/O interface according to EIA/JESD 8A
specification.
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Drive capability up to 8 mA per buffer with slew
rate control, current spike suppression
impedance matching, and process
compensation capability to reduce delay
variation.
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Designs easily portable from previous
generations of CB45000 through cell mapping
with an average factor 2 density increase, 1.7
speed increase and 2.5 power reduction at
respective nominal voltages.
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Generators to support Single Port, Dual port
and multiple Port RAM, and ROMs with BIST
options.
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Extensive embedded function library including
ST DSP and micro-cores, third-party IPs,
Synopsys and Mentor Inventra synthetic
libraries ideally suited for complete System On
Chip fast integration .
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80
m pitch linear and 50
m staggered pad
libraries.
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Fully independent power and ground
configuration for core and I/Os supported.
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I/O ring capability up to 1500 pads.
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Latch-up trigger current > +/- 500 mA. ESD
protection above 4 kV in H.B.M.
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Oscillators and PLLs for wide frequency
spectrum.
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Broad range of more than 600 SSI cells.
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Design for test features including IEEE 1149.1
JTAG Boundary Scan architecture.
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Synopsys, Cadence and Mentor based design
systems with interface from multiple
workstations.
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Broad range of packaging solutions, including
BGA, LBGA, TQFP, PQFP, PLCC up to 1000
pins with enhanced power dissipation options.
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1.25 GigaHertzGigabit DLL technique.
CB55000 Super Integration
Cost Effective Product
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Architecture partitioning
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Trouble-free integration
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Application-specific
Your Product is Unique
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User specified cell integration
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Design confidentiality
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IP fully re-usable
DPRAM
ST20
ROM
DSP
HCMOS7 Standard Cells
CB55000 Series
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Figure 1. Metal 1 perspective view
CMOS 0.25
m, Shallow Trench Isolation, M1: Tungsten
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CB55000 Series
1
GENERAL DESCRIPTION
The CB55000 standard cell series uses a high performance, low-voltage, 0.25
m drawn (0.20
m effective),
six metal levels CMOS process HCMOS7 to a 90 pico-second internal delay while offering very low power dis-
sipation and high noise immunity.
With an average routed gate density of 30,000 gates/mm
2
, the CB55000 family allows the integration of up to
15 million equivalent gates and is ideal for high-complexity or high-performance devices for computer, telecom-
munication and consumer products.
With a typical gate delay of 70 ps (for a 2-input NAND gate at fan-out 1), the library meets the most demanding
speed requirements in telecommunication and computer application designs today.
Optimized for 2.5 V operation, the library features a power consumption of less than 70 nW/Gate/MHz (fan-
out=1) and 30 nW/Gate/MHz (fan-out=1) at 1.8 V.
The I/O buffers can be fully configured for both 2.5 V and 3.3 V interface options, with several high speed buffer
types available. These include: low voltage differential (LVDS) I/Os, PCI/AGP, PECLs, and HSTL.
The pad pitch down to 50
m, in a staggered arrangement, meets the requirements of high pin-count devices
which tend to become pad-limited at such library densities. For very high pin-count ICs, advanced packaging
solutions such as Chip Scale Packaging in fine pitch BGA are available.
New packaging solutions using a flip-chip approach are currently being developed.
Figure 2. HCMOS7 Front end cross section
MOS gate length: 0.25
m, Shallow Trench Isolation, M1: Tungsten
CB55000 Series
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2
TECHNOLOGY OVERVIEW
The advanced HCMOS7 transistor architecture: at 0.25
m drawn length and 0.20
m effective length, very thin
gate oxide: 5 nanometers, optimized threshold voltages and salicided source, drain, and gate leads to intrinsi-
cally high performances in both N channel and P channel driving currents.
The major scaling factor is obtained through deep UV lithography at most masking levels, making sub-micron
pitch a reality.
Further integration in the process front-end comes from the use of the Shallow Trench Isolation process be-
tween active regions, both improving density and planarity of transistors. In order to allow full utilization of such
transistor density, up to 6 levels of metal are made available for routing.
The first metal level is Tungsten for local interconnection, while the other five metal levels are of low resistivity
aluminum for long range interconnection and power distribution.
The thick inter-level dielectric is completely planarized by Chemical Mechanical Polishing, which provides de-
fect-free isolation between stripes within the same as well as between different levels.
Usage of Tungsten plugs at contacts and vias allows extremely dense and reliable interconnection between
metal layers. These vias and contacts are fully stackable, providing a direct vertical electrical connection from
the active level up to the sixth metal level. This efficient interconnect scheme makes routing fast and easy, as
well as having a very positive impact on high gate count, random-logic blocks density and routability.
The combination of both high drive and dense transistors, easily interconnected with up to six fine-pitch metal
levels and isolated by thick dielectric leads to an optimum gate density, with low parasitic resistance and capac-
itance. This results in very short interconnected gate delay and minimized power consumption.
Figure 3. HCMOS7 Back end Cross Section
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CB55000 Series
3
LIBRARY
The CB55000 library is organized into three categories:
SSI cell library
I/O cell library
Macrofunctions
3.1 SSI Cell Library Overview
The design of the CB55000 family has been optimized to allow extremely high density, high speed and low pow-
er designs. For these reasons, a wide range of cells with different ranges of driving capabilities are available in
the library.
The library cells have been optimized in terms of functional and electrical parameters, in order to have:
Good balancing
Maximum speed
Optimum threshold voltage
Symmetric V
dd
/V
ss
noise margins
Minimum power-speed value
The geometrical aspect of the cells was configured to allow an extremely dense design, fully exploiting the fea-
tures of the Place and Route tool in terms of horizontal and vertical routing grids. For Place and Route, up to
six layers of metal are utilized; the first metal layer is dedicated to intracell wiring, the second layer to power
distribution and routing, the third and forth layers to routing, and the fifth and sixth to power distribution, clock
bussing and routing.
Figure 4. ND2 figure from CB55000
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