M87C257
ADDRESS LATCHED
256K (32K x 8) UV EPROM and OTP EPROM
June 1996
1/13
AI00928B
15
A0-A14
ASVPP
Q0-Q7
VCC
M87C257
G
E
VSS
8
Figure 1. Logic Diagram
INTEGRATED ADDRESS LATCH
FAST ACCESS TIME: 45ns
LOW POWER "CMOS" CONSUMPTION:
Active Current 30mA
Standby Current 100
A
PROGRAMMING VOLTAGE: 12.75V
ELECTRONIC SIGNATURE for AUTOMATED
PROGRAMMING
PROGRAMMING TIMES of AROUND 3sec.
(PRESTO II ALGORITHM)
DESCRIPTION
The M87C257 is a high speed 262,144 bit UV
erasable and electrically programmable EPROM.
The M87C257 incorporates latches for all address
inputs to minimize chip count, reduce cost, and
simplify the design of multiplexed bus systems.
The Window Ceramic Frit-Seal Dual-in-Line pack-
age has a transparent lid which allows the user to
expose the chip to ultraviolet light to erase the bit
pattern. A new pattern can then be written to the
device by following the programming procedure.
For applications where the content is programmed
only one time and erasure is not required, the
M87C257 is offered in Plastic Leaded Chip Carrier,
package.
A0 - A14
Address Inputs
Q0 - Q7
Data Outputs
E
Chip Enable
G
Output Enable
ASV
PP
Address Strobe / Program Supply
V
CC
Supply Voltage
V
SS
Ground
Table 1. Signal Names
PLCC32 (C)
1
28
FDIP28W (F)
A1
A0
Q0
A7
A4
A3
A2
A6
A5
A13
A10
A8
A9
Q7
A14
A11
G
E
Q5
Q1
Q2
Q3
VSS
Q4
Q6
A12
ASVPP
VCC
AI00929
M87C257
8
1
2
3
4
5
6
7
9
10
11
12
13
14
16
15
28
27
26
25
24
23
22
21
20
19
18
17
Figure 2A. DIP Pin Connections
Warning: NC = Not Connected, DU = Dont't Use.
AI00930
A13
A8
A10
Q4
17
A0
NC
Q0
Q1
Q2
DU
Q3
A6
A3
A2
A1
A5
A4
9
A14
A9
1
ASV
PP
A11
Q6
A7
Q7
32
DU
V
CC
M87C257
A12
NC
Q5
G
E
25
V
SS
Figure 2B. LCC Pin Connections
DEVICE OPERATION
The modes of operation of the M87C257 are listed
in the Operating Modes. A single power supply is
required in the read mode. All inputs are TTL levels
except for V
PP
and 12V on A9 for Electronic Signa-
ture.
Read Mode
The M87C257 has two control functions, both of
which must be logically active in order to obtain
data at the outputs. Chip Enable (E) is the power
control and should be used for device selection.
Output Enable (G) is the output control and should
Symbol
Parameter
Value
Unit
T
A
Ambient Operating Temperature
40 to 125
C
T
BIAS
Temperature Under Bias
50 to 125
C
T
STG
Storage Temperature
65 to 150
C
V
IO
(2)
Input or Output Voltages (except A9)
2 to 7
V
V
CC
Supply Voltage
2 to 7
V
V
A9
(2)
A9 Voltage
2 to 13.5
V
V
PP
Program Supply Voltage
2 to 14
V
Notes: 1. Except for the rating "Operating Temperature Range", stresses above those listed in the Table "Absolute Maximum Ratings"
may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other
conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum
Rating conditions for extended periods may affect device reliability. Refer also to the SGS-THOMSON SURE Program and other
relevant quality documents.
2. Minimum DC voltage on Input or Output is 0.5V with possible undershoot to 2.0V for a period less than 20ns. Maximum DC
voltage on Output is V
CC
+0.5V with possible overshoot to V
CC
+2V for a period less than 20ns.
Table 2. Absolute Maximum Ratings
(1)
2/13
M87C257
Mode
E
G
A9
ASV
PP
Q0 - Q7
Read (Latched Address)
V
IL
V
IL
X
V
IL
Data Out
Read (Applied Address)
V
IL
V
IL
X
V
IH
Data Out
Output Disable
V
IL
V
IH
X
X
Hi-Z
Program
V
IL
Pulse
V
IH
X
V
PP
Data In
Verify
V
IH
V
IL
X
V
PP
Data Out
Program Inhibit
V
IH
V
IH
X
V
PP
Hi-Z
Standby
V
IH
X
X
X
Hi-Z
Electronic Signature
V
IL
V
IL
V
ID
V
IL
Codes
Note: X = V
IH
or V
IL
, V
ID
= 12V
0.5V
Table 3. Operating Modes
Identifier
A0
Q7
Q6
Q5
Q4
Q3
Q2
Q1
Q0
Hex Data
Manufacturer's Code
V
IL
0
0
1
0
0
0
0
0
20h
Device Code
V
IH
1
0
0
0
0
0
0
0
80h
Table 4. Electronic Signature
be used to gate data to the output pins, inde-
pendent of device selection. Assuming that the
addresses are stable (AS = V
IH
) or latched (AS =
V
IL
), the address access time (t
AVQV
) is equal to the
delay from E to output (t
ELQV
). Data is available at
the output after delay of t
GLQV
from the falling edge
of G, assuming that E has been low and the ad-
dresses have been stable for at least t
AVQV
-t
GLQV
.
The M87C257 reduces the hardware interface in
multiplexed address-data bus systems. The proc-
essor multiplexed bus (AD0-AD7) may be tied to
the M87C257's address and data pins. No sepa-
rate address latch is needed because the
M87C257 latches all address inputs when AS is
low.
Standby Mode
The M87C257 has a standby mode which reduces
the active current from 30mA to 100
A (Address
Stable). The M87C257 is placed in the standby
mode by applying a CMOS high signal to the E
input. When in the standby mode, the outputs are
in a high impedance state, independent of the G
input.
Two Line Output Control
Because EPROMs are usually used in larger mem-
ory arrays, this product features a 2 line control
function which accommodates the use of multiple
memory connection. The two line control function
allows:
a. the lowest possible memory power dissipation,
b. complete assurance that output bus contention
will not occur.
For the most efficient use of these two control lines,
E should be decoded and used as the primary
device selecting function, while G should be made
a common connection to all devices in the array
and connected to the READ line from the system
control bus. This ensures that all deselected mem-
ory devices are in their low power standby mode
and that the output pins are only active when data
is desired from a particular memory device.
3/13
M87C257
AI01822
3V
High Speed
0V
1.5V
2.4V
Standard
0.4V
2.0V
0.8V
Figure 3. AC Testing Input Output Waveform
AI01823
1.3V
OUT
CL = 30pF or 100pF
CL = 30pF for High Speed
CL = 100pF for Standard
CL includes JIG capacitance
3.3k
1N914
DEVICE
UNDER
TEST
Figure 4. AC Testing Load Circuit
High Speed
Standard
Input Rise and Fall Times
10ns
20ns
Input Pulse Voltages
0 to 3V
0.4V to 2.4V
Input and Output Timing Ref. Voltages
1.5V
0.8V and 2V
Table 5. AC Measurement Conditions
Symbol
Parameter
Test Condition
Min
Max
Unit
C
IN
Input Capacitance
V
IN
= 0V
6
pF
C
OUT
Output Capacitance
V
OUT
= 0V
12
pF
Note: 1. Sampled only, not 100% tested.
Table 6. Capacitance
(1)
(T
A
= 25
C, f = 1 MHz )
System Considerations
The power switching characteristics of Advance
CMOS EPROMs require careful decoupling of the
devices. The supply current, I
CC
, has three seg-
ments that are of interest to the system designer:
the standby current level, the active current level,
and transient current peaks that are produced by
the falling and rising edges of E. The magnitude of
this transient current peaks is dependent on the
capacitive and inductive loading of the device at the
output. The associated transient voltage peaks can
be suppressed by complying with the two line
output control and by properly selected decoupling
capacitors. It is recommended that a 0.1
F ceramic
capacitor be used on every device between V
CC
and V
SS
. This should be a high frequency capacitor
of low inherent inductance and should be placed
as close to the device as possible. In addition, a
4.7
F bulk electrolytic capacitor should be used
between V
CC
and V
SS
for every eight devices. The
bulk capacitor should be located near the power
supply connection point. The purpose of the bulk
capacitor is to overcome the voltage drop caused
by the inductive effects of PCB traces.
4/13
M87C257
Symbol
Parameter
Test Condition
Min
Max
Unit
I
LI
Input Leakage Current
0V
V
IN
V
CC
10
A
I
LO
Output Leakage Current
0V
V
OUT
V
CC
10
A
I
CC
Supply Current
E = V
IL
, G = V
IL
,
I
OUT
= 0mA, f = 5MHz
30
mA
I
CC1
Supply Current
(Standby) TTL
E = V
IH
, ASV
PP
= V
IH
, Address Switching
10
mA
E = V
IH
, ASV
PP
= V
IL
, Address Stable
1
mA
I
CC2
Supply Current (Standby)
CMOS
E
V
CC
0.2V, ASV
PP
V
CC
0.2V,
Address Switching
6
mA
E
V
CC
0.2V, ASV
PP
= V
SS
,
Address Stable
100
A
I
PP
Program Current
V
PP
= V
CC
100
A
V
IL
Input Low Voltage
0.3
0.8
V
V
IH
(2)
Input High Voltage
2
V
CC
+ 1
V
V
OL
Output Low Voltage
I
OL
= 2.1mA
0.4
V
V
OH
Output High Voltage
I
OH
= 1mA
V
CC
0.8V
V
Notes: 1. V
CC
must be applied simultaneously with or before V
PP
and removed simultaneously or after V
PP
.
2. Maximum DC voltage on Output is V
CC
+0.5V.
Table 7. Read Mode DC Characteristics
(1)
(T
A
= 0 to 70
C, 40 to 85
C, 40 to 105
C or 40 to 125
C; V
CC
= 5V
5% or 5V
10%; V
PP
= V
CC
)
Symbol
Alt
Parameter
Test
Condition
M87C257
Unit
-45
(3)
-60
-70
-80
Min Max Min Max Min Max Min Max
t
AVQV
t
ACC
Address Valid to
Output Valid
E = V
IL
, G = V
IL
45
60
70
80
ns
t
AVASL
t
AL
Address Valid to
Address Strobe Low
7
7
7
7
ns
t
ASHASL
t
LL
Address Strobe High
to Address Strobe Low
35
35
35
35
ns
t
ASLAX
t
LA
Address Strobe Low to
Address Transition
20
20
20
20
ns
t
ASLGL
t
LOE
Address Strobe Low to
Output Enable Low
20
20
20
20
ns
t
ELQV
t
CE
Chip Enable Low to
Output Valid
G = V
IL
45
60
70
80
ns
t
GLQV
t
OE
Output Enable Low to
Output Valid
E = V
IL
25
30
35
40
ns
t
EHQZ
(2)
t
DF
Chip Enable High to
Output Hi-Z
G = V
IL
0
25
0
30
0
30
0
40
ns
t
GHQZ
(2)
t
DF
Output Enable High to
Output Hi-Z
E = V
IL
0
25
0
30
0
30
0
40
ns
t
AXQX
t
OH
Address Transition to
Output Transition
E = V
IL
,
G = V
IL
0
0
0
0
ns
Notes: 1. V
CC
must be applied simultaneously with or before V
PP
and removed simultaneously or after V
PP
.
2. Sampled only, not 100% tested.
3. In case of 45ns speed see High Speed AC measurement conditions.
Table 8A. Read Mode AC Characteristics
(1)
(T
A
= 0 to 70
C, 40 to 85
C, 40 to 105
C or 40 to 125
C; V
CC
= 5V
5% or 5V
10%; V
PP
= V
CC
)
5/13
M87C257
Symbol
Alt
Parameter
Test
Condition
M87C257
Unit
-90
-10
-12
-15/-20
Min Max Min Max Min Max Min Max
t
AVQV
t
ACC
Address Valid to
Output Valid
E = V
IL
, G = V
IL
90
100
120
150
ns
t
AVASL
t
AL
Address Valid to
Address Strobe Low
7
7
7
7
ns
t
ASHASL
t
LL
Address Strobe High
to Address Strobe Low
35
35
35
35
ns
t
ASLAX
t
LA
Address Strobe Low to
Address Transition
20
20
20
20
ns
t
ASLGL
t
LOE
Address Strobe Low
to Output Enable Low
20
20
20
20
ns
t
ELQV
t
CE
Chip Enable Low to
Output Valid
G = V
IL
90
100
120
150
ns
t
GLQV
t
OE
Output Enable Low to
Output Valid
E = V
IL
40
40
50
60
ns
t
EHQZ
(2)
t
DF
Chip Enable High to
Output Hi-Z
G = V
IL
0
40
0
30
0
40
0
40
ns
t
GHQZ
(2)
t
DF
Output Enable High to
Output Hi-Z
E = V
IL
0
40
0
30
0
40
0
40
ns
t
AXQX
t
OH
Address Transition to
Output Transition
E = V
IL
, G = V
IL
0
0
0
0
ns
Notes: 1. V
CC
must be applied simultaneously with or before V
PP
and removed simultaneously or after V
PP
.
2. Sampled only, not 100% tested.
Table 8B. Read Mode AC Characteristics
(1)
(T
A
= 0 to 70
C, 40 to 85
C, 40 to 105
C or 40 to 125
C; V
CC
= 5V
5% or 5V
10%; V
PP
= V
CC
)
AI00931
tAXQX
tEHQZ
DATA OUT
A0-A14
E
G
Q0-Q7
tASLAX
tGHQZ
tGLQV
tELQV
VALID
Hi-Z
tAVQV
tASLGL
tASHASL
tAVASL
ASVPP
Figure 5. Read Mode AC Waveforms
6/13
M87C257
Symbol
Parameter
Test Condition
Min
Max
Unit
I
LI
Input Leakage Current
V
IL
V
IN
V
IH
10
A
I
CC
Supply Current
50
mA
I
PP
Program Current
E = V
IL
50
mA
V
IL
Input Low Voltage
0.3
0.8
V
V
IH
Input High Voltage
2
V
CC
+ 0.5
V
V
OL
Output Low Voltage
I
OL
= 2.1mA
0.4
V
V
OH
Output High Voltage TTL
I
OH
= 1mA
V
CC
-0.8V
V
V
ID
A9 Voltage
11.5
12.5
V
Note: 1. V
CC
must be applied simultaneously with or before V
PP
and removed simultaneously or after V
PP
.
Table 9. Programming Mode DC Characteristics
(1)
(T
A
= 25
C; V
CC
= 6.25V
0.25V; V
PP
= 12.75V
0.25V)
Symbol
Alt
Parameter
Test Condition
Min
Max
Unit
t
AVEL
t
AS
Address Valid to Chip Enable Low
2
s
t
QVEL
t
DS
Input Valid to Chip Enable Low
2
s
t
VPHEL
t
VPS
V
PP
High to Chip Enable Low
2
s
t
VCHEL
t
VCS
V
CC
High to Chip Enable Low
2
s
t
ELEH
t
PW
Chip Enable Program Pulse Width
95
105
s
t
EHQX
t
DH
Chip Enable High to Input Transition
2
s
t
QXGL
t
OES
Input Transition to Output Enable Low
2
s
t
GLQV
t
OE
Output Enable Low to Output Valid
100
ns
t
GHQZ
t
DFP
Output Enable High to Output Hi-Z
0
130
ns
t
GHAX
t
AH
Output Enable High to Address Transition
0
ns
Note: 1. V
CC
must be applied simultaneously with or before V
PP
and removed simultaneously or after V
PP
Table 10. Programming Mode AC Characteristics
(1)
(T
A
= 25
C; V
CC
= 6.25V
0.25V; V
PP
= 12.75V
0.25V)
Programming
When delivered (and after each erasure for UV
EPROM), all bits of the M87C257 are in the "1"
state. Data is introduced by selectively program-
ming "0"s into the desired bit locations. Although
only "0"s will be programmed, both "1"s and "0"s
can be present in the data word. The only way to
change a "0" to a "1" is by die exposition to ultra-
violet light (UV EPROM). The M87C257 is in the
programming mode when V
PP
input is at 12.75V, G
is at V
IH
and E is pulsed to V
IL
. The data to be
programmed is applied to 8 bits in parallel to the
data output pins. The levels required for the ad-
dress and data inputs are TTL. V
CC
is specified to
be 6.25 V
0.25 V.
7/13
M87C257
tAVEL
VALID
AI00557
A0-A14
Q0-Q7
ASVPP
VCC
G
DATA IN
DATA OUT
E
tQVEL
tVPHEL
tVCHEL
tEHQX
tELEH
tGLQV
tQXGL
tGHQZ
tGHAX
PROGRAM
VERIFY
Figure 6. Programming and Verify Modes AC Waveforms
PRESTO II Programming Algorithm
PRESTO II Programming Algorithm allows to pro-
gram the whole array with a guaranteed margin, in
a typical time of 3.5 seconds. Programming with
PRESTO II involves the application of a sequence
of 100
s program pulses to each byte until a correct
verify occurs (see Figure 7). During programming
and verify operation, a MARGIN MODE circuit is
automatically activated in order to guarantee that
each cell is programmed with enough margin. No
overprogram pulse is applied since the verify in
MARGIN MODE provides necessary margin to
each programmed cell.
Program Inhibit
Programming of multiple M87C257s in parallel with
different data is also easily accomplished. Except
for E, all like inputs including G of the parallel
M87C257 may be common. A TTL low level pulse
applied to a M87C257's E input, with V
PP
at 12.75V,
will program that M87C257. A high level E input
inhibits the other M87C257s from being pro-
grammed.
Program Verify
A verify (read) should be performed on the pro-
grammed bits to determine that they were correctly
programmed. The verify is accomplished with G at
V
IL
, E at V
IH
, V
PP
at 12.75V and V
CC
at 6.25V.
AI00760B
n = 0
Last
Addr
VERIFY
E = 100
s Pulse
++n
= 25
++ Addr
VCC = 6.25V, VPP = 12.75V
FAIL
CHECK ALL BYTES
1st: VCC = 6V
2nd: VCC = 4.2V
YES
NO
YES
NO
YES
NO
Figure 7. Programming Flowchart
8/13
M87C257
Electronic Signature
The Electronic Signature (ES) mode allows the
reading out of a binary code from an EPROM that
will identify its manufacturer and type. This mode
is intended for use by programming equipment to
automatically match the device to be programmed
with its corresponding programming algorithm. The
ES mode is functional in the 25
C
5
C ambient
temperature range that is required when program-
ming the M87C257.
To activate the ES mode, the programming equip-
ment must force 11.5V to 12.5V on address line A9
of the M87C257, with V
CC
= V
PP
= 5V. Two identifier
bytes may then be sequenced from the device
outputs by toggling address line A0 from V
IL
to V
IH
.
All other address lines must be held at V
IL
during
Electronic Signature mode. Byte 0 (A0=V
IL
) repre-
sents the manufacturer code and byte 1 (A0=V
IH
)
the device identifier code. When A9 = V
ID
, AS need
not be toggled to latch each identifier address. For
the SGS-THOMSON M87C257, these two identi-
fier bytes are given in Table 4 and can be read-out
on outputs Q0 to Q7.
ERASURE OPERATION (applies for UV EPROM)
The erasure characteristics of the M87C257 is such
that erasure begins when the cells are exposed to
light with wavelengths shorter than approximately
4000 . It should be noted that sunlight and some
type of fluorescent lamps have wavelengths in the
3000-4000 range. Research shows that constant
exposure to room level fluorescent lighting could
erase a typical M87C257 in about 3 years, while it
would take approximately 1 week to cause erasure
when exposed to direct sunlight. If the M87C257 is
to be exposed to these types of lighting conditions
for extended periods of time, it is suggested that
opaque labels be put over the M87C257 window to
prevent unintentional erasure. The recommended
erasure procedure for the M87C257 is exposure to
short wave ultraviolet light which has wavelength
2537. The integrated dose (i.e. UV intensity x
exposure time) for erasure should be a minimum
of 15 W-sec/cm
2
. The erasure time with this dos-
age is approximately 15 to 20 minutes using an
ultraviolet lamp with 12000
W/cm
2
power rating.
The M87C257 should be placed within 2.5 cm (1
inch) of the lamp tubes during the erasure. Some
lamps have a filter on their tubes which should be
removed before erasure.
9/13
M87C257
ORDERING INFORMATION SCHEME
Note: 1. High Speed, see AC Characteristics section for further information.
For a list of available options (Speed, V
CC
Tolerance, Package, etc...) refer to the current Memory Shortform
catalogue.
For further information on any aspect of this device, please contact the SGS-THOMSON Sales Office
nearest to you.
Speed
-45
(1)
45 ns
-60
60 ns
-70
70 ns
-80
80 ns
-90
90 ns
-10
100 ns
-12
120 ns
-15
150 ns
-20
200 ns
V
CC
Tolerance
X
5%
blank
10%
Package
F
FDIP28W
C
PLCC32
Temperature Range
1
0 to 70
C
6
40 to 85
C
7
40 to 105
C
3
40 to 125
C
Option
X
Additional
Burn-in
TR
Tape & Reel
Packing
Example: M87C257 -70 X C 1 X
10/13
M87C257
FDIP28W - 28 pin Ceramic Frit-seal DIP, with window
FDIPW-a
A2
A1
A
L
B1
B
e1
D
S
E1
E
N
1
C
eA
e3
Symb
mm
inches
Typ
Min
Max
Typ
Min
Max
A
5.71
0.225
A1
0.50
1.78
0.020
0.070
A2
3.90
5.08
0.154
0.200
B
0.40
0.55
0.016
0.022
B1
1.17
1.42
0.046
0.056
C
0.22
0.31
0.009
0.012
D
38.10
1.500
E
15.40
15.80
0.606
0.622
E1
13.05
13.36
0.514
0.526
e1
2.54
0.100
e3
33.02
1.300
eA
16.17
18.32
0.637
0.721
L
3.18
4.10
0.125
0.161
S
1.52
2.49
0.060
0.098
7.11
0.280
4
15
4
15
N
28
28
FDIP28W
Drawing is not to scale
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M87C257
PLCC32 - 32 lead Plastic Leaded Chip Carrier, rectangular
PLCC
D
Ne
E1 E
1 N
D1
Nd
CP
B
D2/E2
e
B1
A1
A
Symb
mm
inches
Typ
Min
Max
Typ
Min
Max
A
2.54
3.56
0.100
0.140
A1
1.52
2.41
0.060
0.095
B
0.33
0.53
0.013
0.021
B1
0.66
0.81
0.026
0.032
D
12.32
12.57
0.485
0.495
D1
11.35
11.56
0.447
0.455
D2
9.91
10.92
0.390
0.430
E
14.86
15.11
0.585
0.595
E1
13.89
14.10
0.547
0.555
E2
12.45
13.46
0.490
0.530
e
1.27
0.050
N
32
32
Nd
7
7
Ne
9
9
CP
0.10
0.004
PLCC32
Drawing is not to scale
12/13
M87C257
Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsibility for the
consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No
license is granted by implication or otherwise under any patent or patent rights of SGS-THOMSON Microelectronics. Specifications mentioned
in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied.
SGS-THOMSON Microelectronics products are not authorized for use as critical components in life support devices or systems without express
written approval of SGS-THOMSON Microelectronics.
1996 SGS-THOMSON Microelectronics - All Rights Reserved
SGS-THOMSON Microelectronics GROUP OF COMPANIES
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M87C257
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