74VHCT138A
3 TO 8 LINE DECODER (INVERTING)
PRELIMINARY DATA
March 2000
s
HIGH SPEED: t
PD
= 7.6 ns (TYP.) at V
CC
= 5V
s
LOW POWER DISSIPATION:
I
CC
= 4
A (MAX.) at T
A
= 25
o
C
s
COMPATIBLE WITH TTL OUTPUTS:
V
IH
= 2V (MIN), V
IL
= 0.8V (MAX)
s
POWER DOWN PROTECTION ON INPUTS &
OUTPUTS
s
SYMMETRICAL OUTPUT IMPEDANCE:
|I
OH
| = I
OL
= 8 mA (MIN)
s
BALANCED PROPAGATION DELAYS:
t
PLH
t
PHL
s
OPERATING VOLTAGE RANGE:
V
CC
(OPR) = 4.5V to 5.5V
s
PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 138
s
IMPROVED LATCH-UP IMMUNITY
s
LOW NOISE: V
OLP
= 0.8V (Max.)
DESCRIPTION
The 74VHCT138A is an advanced high-speed
CMOS 3 TO 8 LINE DECODER (INVERTING)
fabricated with sub-micron silicon gate and
double-layer metal wiring C
2
MOS technology.
If the device is enabled, 3 binary select inputs (A,
B and C) determine which one of the outputs will
go low. If enable input G1 is held low or either
G2A or G2B is held high, the decoding function is
inhibited and all the 8 outputs go to high.
Three enable inputs are provided to ease
cascade connection and application of address
decoders for memory systems.
Power down protection is provided on all inputs
and outputs and 0 to 7V can be accepted on
inputs with no regard to the supply voltage. This
device can be used to interface 5V to 3V.
All inputs
and
outputs are
equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
PIN CONNECTION AND IEC LOGIC SYMBOLS
SOP
TSSOP
ORDER CODES
PACKAGE
T UBE
T & R
SOP
74VHCT138AM
74VHCT138AMTR
TSSOP
74VHCT138ATTR
1/8
INPUT EQUIVALENT CIRCUIT
LOGIC DIAGRAM
PIN DESCRIPTION
PIN No
SYMBOL
NAME AND FUNCT ION
1, 2, 3
A, B, C
Address Inputs
4, 5
G2A, G2B
Enable Inputs
6
G1
Enable Input
15, 14, 13,
12, 11, 10,
9, 7
Y0 to Y7
Outputs
8
GND
Ground (0V)
16
V
CC
Positive Supply Voltage
TRUTH TABLE
INPUT S
OUTPUTS
ENABL E
SELECT
G2B
G2A
G 1
C
B
A
Y0
Y1
Y2
Y3
Y4
Y5
Y6
Y7
X
X
L
X
X
X
H
H
H
H
H
H
H
H
X
H
X
X
X
X
H
H
H
H
H
H
H
H
H
X
X
X
X
X
H
H
H
H
H
H
H
H
L
L
H
L
L
L
L
H
H
H
H
H
H
H
L
L
H
L
L
H
H
L
H
H
H
H
H
H
L
L
H
L
H
L
H
H
L
H
H
H
H
H
L
L
H
L
H
H
H
H
H
L
H
H
H
H
L
L
H
H
L
L
H
H
H
H
L
H
H
H
L
L
H
H
L
H
H
H
H
H
H
L
H
H
L
L
H
H
H
L
H
H
H
H
H
H
L
H
L
L
H
H
H
H
H
H
H
H
H
H
H
L
X:Don't Care
Thislogic diagram has notbe used to estimate propagation delays
74VHCT138A
2/8
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Valu e
Uni t
V
CC
Supply Voltage
4.5 to 5.5
V
V
I
Input Voltage
0 to 5.5
V
V
O
Output Voltage (see note 1)
0 to 5.5
V
V
O
Output Voltage (see note 2)
0 to V
CC
V
T
op
Operating Temperature
-40 to +85
o
C
dt/dv
Input Rise and Fall Time (see note 3) (V
CC
= 5.0
0.5V)
0 to 20
ns/V
1) V
CC
=0
2) High or Low State
3)V
IN
from0.8V to 2 V
ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
Val ue
Unit
V
CC
Supply Voltage
-0.5 to +7.0
V
V
I
DC Input Voltage
-0.5 to +7.0
V
V
O
DC Output Voltage (see note 1)
-0.5 to +7.0
V
V
O
DC Output Voltage (see note 2)
-0.5 to V
CC
+ 0.5
V
I
IK
DC Input Diode Current
- 20
mA
I
OK
DC Output Diode Current
20
mA
I
O
DC Output Current
25
mA
I
CC
or I
GND
DC V
CC
or Ground Current
50
mA
T
stg
Storage Temperature
-65 to +150
o
C
T
L
Lead Temperature (10 sec)
300
o
C
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these condition is not implied.
1) V
CC
=0
2) High or Low State
DC SPECIFICATIONS
Symb ol
Parameter
T est Cond ition s
Val ue
Un it
V
CC
(V)
T
A
= 25
o
C
-40 to 85
o
C
Min.
Typ .
Max.
Min .
Max.
V
IH
High Level Input
Voltage
4.5 to 5.5
2
2
V
V
IL
Low Level Input
Voltage
4.5 to 5.5
0.8
0.8
V
V
OH
High Level Output
Voltage
4.5
I
O
=-50
A
4.4
4.5
4.4
V
4.5
I
O
=-8 mA
3.94
3.8
V
OL
Low Level Output
Voltage
4.5
I
O
=50
A
0.0
0.1
0.1
V
4.5
I
O
=8 mA
0.36
0.44
I
I
Input Leakage Current
0 to 5.5
V
I
= 5.5V or GND
0.1
1.0
A
I
CC
Quiescent Supply
Current
5.5
V
I
= V
CC
or GND
4
40
A
I
CC
Additional Worst Case
Supply Current
5.5
One Input at 3.4V,
other input at V
CC
or
GND
1.35
1.5
mA
I
OPD
Output Leakage
Current
0
V
OUT
= 5.5V
0.5
5.0
A
74VHCT138A
3/8
CAPACITIVE CHARACTERISTICS
Symb ol
Parameter
T est Cond ition s
Val ue
Un it
T
A
= 25
o
C
-40 to 85
o
C
Min.
Typ .
Max.
Min .
Max.
C
IN
Input Capacitance
4
10
10
pF
C
PD
Power Dissipation
Capacitance (note 1)
49
pF
1) C
PD
isdefined as the value of the IC'sinternal equivalent capacitance which is calculated fromthe operating current consumption without load. (Referto
Test Circuit).Average operating current can be obtained by the following equation. I
CC
(opr) = C
PD
V
CC
f
IN
+ I
CC
AC ELECTRICAL CHARACTERISTICS (Input t
r
= t
f
=3 ns)
Symb ol
Parameter
Test Co nditi on
Val ue
Un it
V
CC
(V)
C
L
(pF )
T
A
= 25
o
C
-40 to 85
o
C
Min.
Typ .
Max.
Min .
Max.
t
PLH
t
PHL
Propagation Delay
Time A, B, C to Y
5.0
(*)
15
7.6
10.4
1.0
12.0
ns
5.0
(*)
50
8.1
11.4
1.0
13.0
t
PLH
t
PHL
Propagation Delay
Time G1 to Y
5.0
(*)
15
6.6
9.1
1.0
10.5
ns
5.0
(*)
50
7.1
10.1
1.0
11.5
t
PLH
t
PHL
Propagation Delay
Time G2A, G2B to Y
5.0
(*)
15
7.0
9.6
1.0
11.0
ns
5.0
(*)
50
7.5
10.6
1.0
12.0
(*) Voltage range is 5V
0.5V
TEST CIRCUIT
C
L
= 15/50 pF or equivalent (includes jig and probe capacitance)
R
T
= Z
OUT
of pulse generator (typically 50
)
74VHCT138A
4/8
WAVEFORM 2: PROPAGATION DELAYS FOR NON-INVERTING OUTPUTS (f=1MHz; 50% duty cycle)
WAVEFORM 1: PROPAGATION DELAYS FOR INVERTING OUTPUTS (f=1MHz; 50% duty cycle)
74VHCT138A
5/8
PDF 
ZIP