CXA1977R

48 pin LQFP (Plastic)

E94326-PS

10-bit 20MSPS A/D Converter

Description

The CXA1977R is a 10-bit 20MSPS 2-step parallel

type A/D converter for video signal processing.

This A/D converter operates on +5V power

supplies. The analog signal can be converted to the

digital signal by using this IC in conjunction with the

Sample-and-hold IC.

Features

· Maximum operating speed : 20MSPS (Min.)

· Resolution

: 10-bit

· Low power dissipation

: 160mW (Typ.)

· Wide-band analog input

: 10MHz

· Low input capacitance

: 50pF (Typ.)

· Built-in digital correction

(Compensation within ±16LSB)

· TTL input

· TTL output

· Output code : binary/2'S complement/1'S complement

Block Diagram

Function

10-bit 20MSPS 2-step parallel type A/D converter

Structure

Bipolar silicon monolithic IC

Applications

High resolution video signal processing

Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.

N.C.

VINL

VINH

N.C.

AGND

UNDER

OVER

DGND1

ENABLE

CLK

MINV

LINV

N.C.

DGND2

DGND1

N.C.

(
L

SB)

ND1

(
M

SB)

MATRIX

CORRECTION

H-COMPARATOR

OVER/UNDER

OUTPUT BUFFER

FINE OUTPUT

BUFFER

COARSE OUTPUT

BUFFER

-
C

PAR

-
E

NCO

RDE

K BU

H-ENCODER

CXA1977R

Absolute Maximum Ratings (Ta = 25°C)

· Supply voltage

DVcc1

0 to +6

DVcc2

0 to +6

DVcc3

0 to +6

AVcc

0 to +6

· Analog input voltage

VINH

AGND to AVcc + 0.3

VINL

AGND to AVcc + 0.3

· Reference voltage

VREFT

AGND to AVcc + 0.3

VREFB

AGND to AVcc + 0.3

· Digital input voltage

CLK

DGND1 0.5 to DVcc1

MINV

DGND1 0.5 to DVcc1

LINV

DGND1 0.5 to DVcc1

ENABLE

DGND1 0.5 to DVcc1

· Digital output voltage

DGND1 0.5 to +3.6

(Vo: The voltage is applied to the output pin for high impedance output.)

· Storage temperature

Tstg

65 to 150

°C

· Allowable power dissipation

950

(On a fiber-glass epoxy board: 40mm

40mm, t = 0.8mm)

Recommended Operating Conditions

Min.

Typ.

Max.

Unit

· Supply voltage

DVcc1

+4.6

+5.25

DVcc2

+4.6

+5.25

DVcc3

+4.6

+5.25

AVcc

+4.6

+5.25

AGND

DGND1

DGND2

· Analog input voltage

VINH

VINL

· Reference voltage

VREFT

+3.9

+4.1

VREFB

+1.9

+2.1

· Digital input voltage

+0.8

· Clock width

PWH

PWL

· Operating temperature

Topr

+85

°C

CXA1977R

Pin Description

This input can invert
output form of D0 to
D8. In open
condition, this pin
turns to high level
input. (For details,
refer to the Output
Formula Chart.)

Digital output
D0 (LSB) to
D9 (MSB)

Underflow output

This input can invert
output form of D9
(MSB). In open
condition, this pin
turns to high level
input. (For details,
refer to the Output
Formula Chart.)

3-state control.
Turns to enable
when low is input.
In open condition,
this pin turns to high
level input.

Pin No.

Symbol

I/O

Pin voltage

Equivalent circuit

Description

200k

DGND1

DGND2

D0 to

D5 to

UNDER

OVER

ENABLE

MINV

LINV

400k

100k

DGND2

DGND1

1 to 5

8 to 12

6, 14,

16, 48

ENABLE

MINV

LINV

AGND

DGND2

D0 to D9

TTL

UNDER

OVER

DGND1

+5V

(typ.)

GND

+5V

(typ.)

GND

TTL

Overflow output

Digital power supply

Digital ground

Digital power supply

Digital negative
power supply

Analog negative
power supply

CXA1977R

Power save input.
Power save
condition is entered
when high level is
input. In open
condition, this pin
turns to high level
input.

TTL

Clock input

CLK

TTL

ENABLE

MINV

LINV

400k

100k

DGND2

DGND1

20k

30k

DGND1

DGND2

CLK

VREFT

VREF1

VREF2

VREF3

VREFB

VREFTS

AGND

VREFBS

130

Reference voltage
sense (Top)

Reference voltage
force (Top)

Reference voltage
force (Bottom)

Reference voltage
sense (Bottom)

VREFTS

VREFT

VREF1

VREF2

VREF3

VREFB

VREFBS

+4V

+3.5V

+3.0V

+2.5V

+2V

Pin No.

Symbol

I/O

Pin voltage

Equivalent circuit

Description

CXA1977R

Analog input
(Lower comparator
input)

VINL

+2V to +4V

VINL

VREF

AGND

11.2k

Analog input
(Upper comparator
input)

Analog power supply

Open.
Not connected to
internal circuit, but
connection to DGND
(digital ground) is
recommended.

Open.
Not connected to
internal circuit, but
connection to AGND
(analog ground) is
recommended.

VINH

+2V to +4V

+5V (Typ.)

7, 13,
19, 27

N.C.

28, 36,
37, 38,
41, 43

N.C.

VINH

VREF

AGND

26k

Pin No.

Symbol

I/O

Pin voltage

Equivalent circuit

Description

CXA1977R

Item

Symbol

Min.

Typ.

Max.

Unit

Measurement conditions

Resolution

= +2 to +4V

Electrical Characteristics

(Ta = 25°C, DV

1, 2, 3, AV

= +5V, AGND, DGND1, 2 = 0V, V

REFB

= +2V, V

REFT

= +4V)

DC characteristics

Integral linearity error

Differential linearity error

Analog input

Analog input current

Analog input capacitance

Analog input band width

Reference voltage input

Reference current

Reference resistance

Offset voltage

Reference voltage

Digital input

Digital input voltage

Digital input current

Digital input characteristics

Switching characteristics

Maximum operating speed

Clock pulse width

Sampling delay

Output delay time

3-state output disable time

3-state output enable time

= +2 to +2.5V

= +2.5 to +4V

= +4V

= +3V + 0.07Vrms

1dB

DL1

DL2

REF

REF1

REF2

REF3

IH1

IL1

IH2

IL2

PWH

PWL

DLH

DHL

PHZ

PLZ

PZH

PZL

= 5.25V

= 2.7V

= 0.5V

= 2.7V

= 0.5V

CL = 20pF

bit

2.0

+2.0

LSB

0.8

+0.8

LSB

µA

MHz

120

200

280

3.5

3.0

2.5

0.8

+10

µA

200

µA

+10

µA

MSPS

250

400

500

CXA1977R

+1 < E

+2 (LSB) is two and under.

CLK input

MINV, LINV, ENABLE, and PS inputs

Refer to Timing Diagram (1)

Refer to Timing Diagram (2)

The load is a bi-state totem-pole output delay time test load circuit.

The load is a 3-state output test load circuit.

When PS and ENABLE inputs are in high level.

Digital output

Digital output voltage

Leak current during output off

Dynamic characteristics

Differential gain error

Differential phase error

SNR

Power supply

1 current

2 current

3 current

current

Power dissipation Pd = A + B

A = (I

DVCC

1 + I

DVCC

2 + I

DVCC

+ I

AVCC

)

B = | I

REF

= 300µA

= +500µA

1, 2 = 5.25V, V

= 3.6V

1, 2 = 4.6V

2.7

3.4

0.5

0.3

µA

deg

NTSC 40IRE mod. ramp,
Fc = 14.3MSPS

Fc = 20MSPS

FIN = 1kHz

Fc = 20MSPS

FIN = 1MHz

Fc = 20MSPS

FIN = 2MHz

Fc = 20MSPS

FIN = 7.5MHz

During power save

= +5V

During power save

3 = +5V

During power save

2 = +5V

During power save

1 = +5V

SNR

6.0

4.3

0.05

8.1

0.34

0.5

9.9

7.3

0.16

14.7

0.55

3.2

160

14.0

12.0

0.30

21.1

1.13

6.0

239

µA

DVCC

AVCC

Item

Symbol

Min.

Typ.

Max.

Unit

Measurement conditions

CXA1977R

Bi-state Totem-pole Output Delay Time Test Load Circuit

3-state Output Test Load Circuit

Note 1) C

includes probe capacitance and parasitic capacitance in Test Board.

Note 2) All diodes are IS2076.

Error Rate Test Circuit

Test point

Output from the IC under test

= 20pF

Note 1)

Test point

Output from the IC under test

= 20pF

Note 1)

3.9k

Note 2)

SG1

CXA1977R

SG2

DIVIDER

LATCH

ADDER

A + B

= C

LATCH

A > C

COMPA-

RATOR

COUNTER

/2) 1kHz

CLK

(Threshold level)

DIP SW

Test condition

PZL

PZH

PLZ

PHZ

Open

CXA1977R

Notes on Operation

1. Analog ground (AGND)

Keep analog ground surface on PCB as wide as possible with impedance and resistance as low as

possible.

2. Digital ground (DGND1, DGND2)

Upon mounting to PCB keep ground surface as wide as possible with impedance and resistance as low as

possible.

Moreover, a common analog and digital ground immediately near ADC will help obtain characteristics

smoothly.

3. Digital positive power supply (DVcc1, DVcc2, DVcc3)

Connect to the digital ground with a ceramic capacitor over 0.1µF and as close to the pins as possible.

Insert a ceramic capacitor between DVcc2 and DGND1 of TTL output power supply as shortly as possible

because noise tends to occur.

4. Analog positive power supply (AVcc)

Connect to the analog ground on PCB with a ceramic capacitor over 0.1µF as close to the pin as possible.

5. Reference voltage (VREFTS, VREFT, VREF1, VREF2, VREF3, VREFB, VREFBS)

These pins provide reference voltage to upper and lower comparators. Voltage between VREFT and

VREFB corresponds to input dynamic range.

There is a 200

resistance between VREFT and VREFB. By applying 2V to both pins a current of about

10mA flows. When the reference voltage is made unstable by the clock, ADC characteristics are adversely

affected. Connect VREFT and VREFB to the analog ground on PCB by means of a tantalum capacitor

over 10µF and a ceramic capacitor over 0.1µF respectively. Also, connect each of VREF1, VREF2 and

VREF3 to the analog ground on PCB using a ceramic capacitor over 0.1µF. This will provide stability to the

characteristics of high frequency. Strictly speaking on reference voltage VREFT side and VREFB side

there is a respective about 10mV offset.

When there is no problem with the usage of those offset voltages, voltage is applied directly to VREFT,

VREFB. In case the reference voltage is to be strictly applied, adjust to obtain an offset voltage of 0V,

keeping VREFTS and VREFBS as sense pins and VREFT and VREFB as force pins to form a feedback

loop circuit.

For details, see the Standard Circuit.

6. Analog input (VINH, VINL)

VINH is the input pin for the upper comparator while VINL is the input pin for the lower comparator.

Keep the input signal level within the level between VREFT and VREFB.

As this IC's analog input capacitance stands at about 50pF, it is necessary to drive with an buffer amplifier

having sufficient driving capability. Also, when driving is done with the buffer amplifier of a low output

impedance, as A/D converter input capacitance is large, ringing is generated and settling time grows

longer. Here a small resistance of about 5 to 30

is connected in series between the buffer amplifier and

each of A/D converter's VINH and VINL, as a dumping resistance. This eliminates ringing and shortens

settling time. Also keep wiring between buffer amplifier and A/D converter as short as possible.

CXA1977R

7. Clock input (CLK)

TTL input. Clock line wiring should be the shortest possible while distanced from other signal lines to avoid

affecting them.

This IC is 2-step parallel type A/D converter. Accordingly an external sample-and-hold circuit (SH) is

necessary. However the timing between this SH circuit output waveform (A/D converter analog input

waveform) and the A/D converter clock timing requires attention. In the relation between A/D converter

clock and the A/D converter analog input signal, with the timing T

of the rising edge of A/D converter

clock, the upper comparator compares the input signal and the reference voltage to latch the results. After

that, with the timing T

of the falling edge of A/D converter clock, the lower comparator compares the input

signal and reference signal to latch the results. (Strictly speaking, the sampling delay

is in T

and the

sampling delay

is in T

In this A/D converter, the lower comparator features a length of ±32mV (±16LSB) redundance in relation to

the upper comparator. At the timing when the lower comparator compares input signal and reference

signal to latch at the timing T

, it is necessary to have the SH output settling performed. But at the timing

when the upper comparator compares input signal and reference voltage to latch at the timing T

, as long

as the SH output is within the ±32mV range to the final settling value, digital correction applies, A/D

conversion precisely occurs. As seen from the above, A/D converter clock rise and fall timing versus SH

output waveform should be duly considered. For the clock high level time

PWH

and low level time

PWL

, set

to a value in excess of the time indicated for the respective operating conditions.

Output data is synchronously with the clock rising edge.

For details on timing, refer to the Timing Chart.

8. MINV input (MINV)

Digital output polarity inversion control pin of D9 (MSB).

TTL input. At open, turns to high level input.

For correspondence with analog input voltage and output data code, refer to the Output Formula Chart.

9. LINV input (LINV)

Digital output polarity inversion control pin of D8 to D0 (LSB).

TTL input. At open, turns to high level input.

For correspondence with analog input voltage and output data code, refer to the Output Formula Chart.

10. Output enable (ENABLE)

3-state control pin of digital output (D0 to D9, UNDER, OVER)

TTL input. At open, turns to high level input. At that time digital output turns all to high impedance.

11. Power save input (PS)

Power save control pin of internal circuit.

TTL input. At open, turns to high level input.

To set to power save mode, turn both PS and ENABLE to high level input.

CXA1977R

12. Digital output (D0 to D9)

Output pin of D9 (MSB) to D0 (LSB).

TTL output.

Output data polarity inversion is executed by means of MINV and LINV signals, and they can output in

binary, 1'S complement and 2'S complement.

Also, by turning ENABLE signal to high level, the output can be turned into high impedance output.

However, when the output level is for high impedance output or is in power save mode, the voltage of 3.6V

or more must not be applied to prevent the distruction of IC.

For correspondence with analog input voltage and output data code, refer to the Output Formula Chart. For

the timing, refer to the Timing Chart.

13. Overflow output (OVER)

When the input signal exceeds VREFT, overflow signal is output.

MINV and LINV have no effect on this pin.

Also by turning ENABLE signal to high level, the output can be turned into high impedance output.

However, when the output level is for high impedance output or is in power save mode, the voltage of 3.6V

or more must not be applied to prevent the distruction of IC.

For correspondence with analog input voltage and output data code, refer to the Output Formula Chart.

For the timing, refer to the Timing Chart.

14. Underflow output (UNDER)

When the input signal turns below VREFB, underflow signal is output.

MINV and LINV have no effect on this pin.

Also by turning ENABLE signal to high level, the output can be turned into high impedance output.

However, when the output level is for high impedance output or is in power save mode, the voltage of 3.6V

or more must not be applied to prevent the distruction of IC.

For correspondence with analog input voltage and output data code, refer to the Output Formula Chart.

For the timing, refer to the Timing Chart.

CXA1977R

15. TTL to CMOS interface

In general, V

of TTL is approximately 3.7V without load, and it is guaranteed to be 2.7V (Min.). However,

it is not enough for V

of TTL to drive V

of CMOS,because V

of CMOS is 3.5V (Min.)

TTL

CMOS

(Min.) = 2.7V

(Min.) = 3.5V (= 0.7V

)

(Max.) = 0.5V

(Max.) = 1.5V (= 0.3V

)

When TTL output of ADC is made a connection with CMOS logic circuit, pull-up resistance (Rp) is used.

(See chart below). The value of Rp is usually from a few thousand ohm to scores of thousand ohm. The Rp

(min.) is decided by Supply voltage of CMOS (V

) and I

of ADC (= +500µA), while the Rp (max.) is

decided by required propagation delay (positive edge) and load capacitance. When Vcc is larger than V

it is necessary to pay attention to input equivalent circuit of CMOS, because it may happen that V

goes

over the absolute maximum ratings of CMOS and it brings about LATCH-UP to CMOS circuit.

CMOS

ADC

CXA1977R

Output Formula Chart

ENABLE

MINV

LINV

OUTPUT

1 (OPEN)

OF 9 8 7 6 5 4 3 2 1 0 UF

(MSB) (LSB)

1 0 0 0 0 0 0 0 0 0 0 0

0 0 0 0 0 0 0 0 0 0 1 0

0 0 0 0 0 0 0 0 0 1 0 0

0 0 0 0 0 0 0 0 0 1 1 0

0 1 0 0 0 0 0 0 0 0 0 0

0 1 1 1 1 1 1 1 0 1 1 0

0 1 1 1 1 1 1 1 1 0 0 0

0 1 1 1 1 1 1 1 1 0 1 0

0 1 1 1 1 1 1 1 1 1 0 0

0 1 1 1 1 1 1 1 1 1 1 1

000

(OPEN)

512

1019

1020

1021

1022

1023

1 (OPEN)

OF 9 8 7 6 5 4 3 2 1 0 UF

(MSB) (LSB)

1 0 1 1 1 1 1 1 1 1 1 0

0 0 1 1 1 1 1 1 1 1 0 0

0 0 1 1 1 1 1 1 1 0 1 0

0 0 1 1 1 1 1 1 1 0 0 0

0 1 1 1 1 1 1 1 1 1 1 0

0 1 0 0 0 0 0 0 1 0 0 0

0 1 0 0 0 0 0 0 0 1 1 0

0 1 0 0 0 0 0 0 0 1 0 0

0 1 0 0 0 0 0 0 0 0 1 0

0 1 0 0 0 0 0 0 0 0 0 1

1 (OPEN)

OF 9 8 7 6 5 4 3 2 1 0 UF

(MSB) (LSB)

1 1 0 0 0 0 0 0 0 0 0 0

0 1 0 0 0 0 0 0 0 0 1 0

0 1 0 0 0 0 0 0 0 1 0 0

0 1 0 0 0 0 0 0 0 1 1 0

0 0 0 0 0 0 0 0 0 0 0 0

0 0 1 1 1 1 1 1 0 1 1 0

0 0 1 1 1 1 1 1 1 0 0 0

0 0 1 1 1 1 1 1 1 0 1 0

0 0 1 1 1 1 1 1 1 1 0 0

0 0 1 1 1 1 1 1 1 1 1 1

OF 9 8 7 6 5 4 3 2 1 0 UF

(MSB) (LSB)

1 1 1 1 1 1 1 1 1 1 1 0

0 1 1 1 1 1 1 1 1 1 0 0

0 1 1 1 1 1 1 1 1 0 1 0

0 1 1 1 1 1 1 1 1 0 0 0

0 0 1 1 1 1 1 1 1 1 1 0

0 0 0 0 0 0 0 0 1 0 0 0

0 0 0 0 0 0 0 0 0 1 1 0

0 0 0 0 0 0 0 0 0 1 0 0

0 0 0 0 0 0 0 0 0 0 1 0

0 0 0 0 0 0 0 0 0 0 0 1

0: VOLTAGE LEVEL-LOW

OF: OVER FLOW

1: VOLTAGE LEVEL-HIGH

UF: UNDER FLOW

Z: HIGH

IMPEDANCE

CXA1977R

Timing Chart (1)

is the timing of latching result for the comparator of V

and V

REF

in the upper comparators.

is the timing of latching result for the comparator of V

and V

REF

in the lower comparators.

Timing Chart (2)

Notes) Waveform 1 indicates the output waveform when internal conditions are set to obtain a low level

output, with the exception of when output is disabled by means of the ENABLE signal.

Waveform 2 indicates the output waveform when internal conditions are set to obtain a high level

output, with the exception of when output is disabled by means of the ENABLE signal.

DHL

DLH

1/F

PWL

PWH

N + 1

N + 2

1.5V

DATA

N 1

DATA N

DATA N + 1

Sample-and-hold output

A/D clock

A/D digital output

1.5V

0.3V

1.5V

PLZ

4.5V

PHZ

1.5V

PZL

PZH

1.5V

ENABLE signal
(Low-level enabling)

Waveform 1

Note)

Waveform 2

Note)

Output waveform of 3-state

enable and disable time

(

Enable time = t

PZL

PZH

disable time = t

PLZ

PHZ

)

1.5V

CXA1977R

Standard Circuit

ENABLE

CLK

MINV

LINV

N.C.

DGND2

DGND1

N.C.

D0 (LSB)

DGND1

N.C.

D9 (MSB)

35 34

UNDER

OVER

R2 50

VIN

0.1µ

VREFB

VREFT

0.1µ

10µ

C13

0.1µ

C14

0.1µ

C10

10µ

C12

0.1µ

VREFT

ENABLE

CLK

MINV

LINV

C11

0.1µ

N.C.

VINL

VINH

N.C.

AGND

UNDER

OVER

DGND1

N.C.

VREFBS

VREFB

VREF3

VREF2

VREF1

VREFT

VREFTS

N.C.

10 11

R1 50

Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for
any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.

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