Description
The CXA1866Q is a 6-bit ultra-high-speed flash
A/D converter IC capable of digitizing analog
signals at the maximum rate of 140MSPS. The
digital input level is compatible with ECL
100K/10KH/10K.
Features
Ultra-high-speed operation with maximum
conversion rate of 140MSPS
Low input capacitance: 7pF
Wide analog input bandwidth: 210MHz
Low power consumption: 325mW
Low error rate
Excellent temperature characteristics
1 : 2 demultiplexed output (TTL level)
Block Diagram
Structure
Bipolar silicon monolithic IC
Applications
Magnetic recording (PRML)
Communications (QPSK, QAM)
Liquid crystal display
1
CXA1866Q
E93Z35B77
6-bit 140MSPS Flash A/D Converter
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
48 pin QFP (Plastic)
V
RTS
V
IN
V
RBS
P1D5 (MSB)
P1D4
P1D3
P1D2
P1D1
P1D0 (LSB)
P2D5 (MSB)
P2D4
P2D3
P2D2
P2D1
P2D0 (LSB)
Reference Resistance Chain
COMPARATOR
6bit Latch
CLatchA
TTLOUT
V
RB
INV
CCLK
6
CLatchB
DV
CC
2
DGND1
DGND2
AGND
DV
EE
AV
EE
V
RT
DGND3
DV
CC
1
NCCLK
DCLK
NDCLK
6
6
CD
CD
CD; Clock Driver
11
12
16
20
21
23
25
26
27
41
42
45
46
47
48
2
3
4
5
6
7
30
35 34
31
32
33
15
19
22
For the availability of this product, please contact the sales office.
2
CXA1866Q
P2D0 (LSB)
P2D4
P2D5 (MSB)
NDCLK
DCLK
P2D3
P2D2
P2D1
DGND3
DV
CC
2
DGND3
P1D0 (LSB)
INV
NCCLK
CCLK
P1D1
P1D2
P1D5 (MSB)
P1D4
P1D3
DGND3
DV
CC
2
DGND3
AV
EE
V
RBS
V
RB
AGND
V
IN
AGND
V
RT
V
RTS
AV
EE
DGND2
DGND1
DV
EE
DV
CC
2
DGND3
DV
CC
2
DV
CC
2
DV
CC
1
DV
CC
1
DV
EE
DGND2
DGND1
CXA1866Q
(Top View)
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
36 35 34
31
32
33
40
39
38
37
41
42
43
44
45
46
47
48
2
3
4
5
6
7
8
9 10 11 12
1
Absolute Maximum Ratings (Ta = 25C)
Supply voltage
AV
EE
, DV
EE
7.0 to +0.5
V
DV
CC
1
0.5 to +7.0
V
Analog input voltage
V
IN
2.7 to +0.5
V
Reference input voltage
V
RT
, V
RB
2.7 to +0.5
V
I V
RT
V
RB
I
2.5
V
Digital input voltage
DIN
2
4.0 to +0.5
V
I CCLK NCCLK I, I DCLK NDCLK I
2.5
V
Digital output current
ID0 to ID6
30 to +30
mA
Storage temperature
Tstg
65 to +150
C
Ambient operating temperature
Ta
20 to +75
C
Allowable power dissipation
P
D
750
mW
Recommended Operating Conditions
Min.
Typ.
Max.
Supply voltage
AV
EE
, DV
EE
5.5
5.2
4.75
V
AV
EE
DV
EE
0.05
0
0.05
V
AGND DGND
3
0.05
0
0.05
V
DV
CC
1
4.75
5.0
5.25
V
Reference input voltage
V
RT
0.1
0
0.1
V
V
RB
2.2
2.0
0.8
V
Analog input voltage
V
IN
V
RB
V
RT
Digital input voltage
DIN (H)
1.1
V
DIN (L)
1.5
V
CCLK, NCCLK frequency
Fcclk
140
MHz
DCLK, NDCLK frequency
Fdclk
70
MHz
CCLK, NCCLK duty
Dcclk
40
50
60
%
DCLK, NDCLK duty
Ddclk
40
50
60
%
CCLK-DCLK time difference
4
tdcd
T
PWL
+ 2
0
T
PWH
+ 1
ns
Operating temperature
Ta
20
+75
C
1
DV
CC
= DV
CC
1, DV
CC
2
3
DGND = DGND1, DGND2, DGND3
2
D
IN
= CCLK, NCCLK, DCLK, NDCLK, INV
4
Refer to the Timing Chart 1 for T
PWL
, T
PWH
.
Pin Configuration.
Pins without names are NC pins
(not connected).
3
CXA1866Q
Pin Description and I/O Pin Equivalent Circuit
Comparator 1
Comparator 2
Comparator 31
Comparator 32
Comparator 63
V
RB
V
RBS
V
RTS
V
RT
V
IN
AV
EE
AGND
CCLK
(DCLK)
NCCLK
(NDCLK)
DV
EE
DGND1
r
r
r
r
r
500
500
r
1.3V
DCLK inversion clock input.
This is an ECL level input. When left
open, this input goes to the ECL
threshold potential (1.3V). Only
DCLK input can be used for operation
with the NDCLK input left open, but
complementary input is recommended
to attain fast and stable operation.
DCLK clock input.
This is the 1:2 DMPX latch clock; input
a clock of 1/2 frequency of CCLK.
Data are output from DMPX port 1
and port 2 synchronously with the
rising edge of this signal. This is an
ECL level input.
CCLK inversion clock input.
This is an ECL level input. When left
open, this input goes to the ECL
threshold potential (1.3V). Only
CCLK input can be used for operation
with the NCCLK input left open,but
complementary input is recommended
to attain fast and stable operation.
CCLK clock input.
This is the conversion clock, and is an
ECL level input.
Analog input.
The input range is 2Vp-p.
Bottom reference voltage input (= 2V).
This is the bottom reference voltage
supplied to the internal resistance
chain. The external input can be set in
accordance with the peak value on the
minus side of the input analog signal
amplitude.
V
RT
sense output.
This is the voltage sense pin for V
RT
.
V
RB
sense output.
This is the voltage sense pin for V
RB
.
Top reference voltage input (= 0V).
This is the top reference voltage supplied
to the internal resistance chain. The
external input can be set in accordance
with the peak value on the plus side of
the input analog signal amplitude.
Pin
No.
Symbol
21
V
RT
22
V
RTS
16
V
RB
15
V
RBS
19
V
IN
26
CCLK
I/O
I
O
I
O
I
I
I
I
I
Standard
voltage
level
0V
0V
2V
2V
V
RTS
to
V
RBS
ECL
ECL
ECL
ECL
25
NCCLK
11
DCLK
12
NDCLK
Equivalent circuit
Description
4
CXA1866Q
Digital output polarity inversion input.
This is an ECL level input.
This input inverts the polarity of the
digital outputs P1D0 to P1D5, and
P2D0 to P2D5. (Refer to the Output
Code Table.)
When left open, this signal is
maintained at the low level.
These pins are for the 6 bits of digital
output data for DMPX port 1. P2D5 is
the MSB, and P2D0 is the LSB.
These are TTL level outputs.
These pins are for the 6 bits of digital
output data for DMPX port 2. P2D5 is
the MSB, and P2D0 is the LSB.
These are TTL level outputs.
+5V power supply for TTL level
internal circuit.
+5V power supply for TTL level
output buffers (P1D0 to P2D5).
Ground for DV
EE
digital circuit.
Ground for DVcc1 digital circuit.
Ground for DVcc2 digital circuit.
Ground for AV
EE
analog circuit .
Used as the ground for the
comparator input buffers, latches, etc.
Separated from DGND.
5.2V power supply for digital circuit.
Connected internally with AV
EE
.
(Resistance is 4 to 6
.)
5.2V power supply for analog circuit.
Connected internally with DV
EE
.
(Resistance is 4 to 6
.)
27
INV
30
P1D0
31
P1D1
32
P1D2
33
P1D3
34
P1D4
35
P1D5
2
P2D0
3
P2D1
4
P2D2
5
P2D3
6
P2D4
7
P2D5
38, 47
DV
CC
1
9, 28, 37,
43, 48
DV
CC
2
39, 46 DGND1
40, 45
DGND2
1, 8, 29,
36, 42
DGND3
17, 20 AGND
41, 44 DV
EE
14, 23 AV
EE
I
O
--
--
--
--
--
--
--
--
ECL
TTL
+5.0V
+5.0V
0V
0V
0V
0V
5.2V
5.2V
DGND1
DV
EE
INV
r
r
r
500
r
1.3V
1.3V
DV
CC
2
DGND2
P1D0 to D5
P2D0 to D5
100K
DV
CC
1
DGND3
Pin
No.
Symbol
I/O
Standard
voltage
level
Equivalent circuit
Description
5
CXA1866Q
Electrical Characteristics
(Ta = 25C, AV
EE
= DV
EE
= 5.2V, DV
CC
= 5V, V
RT
= 0V, V
RB
= 2V)
Item
Resolution
DC characteristics
Integral linearity error
Differential linearity error
No missing code
Analog input
Analog input capacitance
Analog input resistance
Input bias current
Reference input
Reference resistance
Reference resistance
current
Offset voltage
V
RT
V
RB
Digital input
Logic high level
Logic low level
Logic high current
Logic low current
Input capacitance
Switching characteristics
Maximum conversion
frequency
Aperture jitter
Sampling delay
Digital output
Logic high level
Logic low level
Output delay
Output rising time
Output falling time
Dynamic characteristics
Analog amplitude
input bandwidth
S/N ratio
Error rate
Power supply
Supply current
Power consumption
Symbol
n
EIL
EDL
CIN
RIN
IIN
RREF
Iref
EOT
EOB
VIH
VIL
IIH
IIL
FC
Taj
Tds
VOH
VOL
tdo
tr
tf
Finb
SNR1
SNR2
SNR3
ICC
IEE
Pd
Min.
200
1.13
0
50
140
2.7
2.0
210
60
Typ.
6
Guaranteed
7
225
9
3.5
5.0
1.0
1.2
1.2
36
34
32
10
9
20
40
325
Max.
0.2
0.2
110
25
25
1.50
50
50
0.5
8.0
32
Unit
bits
LSB
LSB
pF
k
A
mA
mV
mV
V
V
A
A
pF
MSPS
ps
ns
V
V
ns
ns
ns
MHz
dB
dB
dB
TPS
1
mA
mA
mW
Conditions
Fc = 140MHz
Fc = 140MHz
V
IN
= 1V + 0.07Vrms, DC
V
IN
70MHz
2V
V
IN
0V
2V
V
IN
0V
VIH = 0.8V
VIL = 1.6V
Error rate1E-9 TPS
1
IOUT = 2mA
IOUT = 1mA
ZL = 25pF
ZL = 25pF, 0.5V to 2.4V
ZL = 25pF, 0.5V to 2.4V
V
IN
= 2Vp-p,
p-p value = 3dB down input frequency
Fc = 140MHz, Fin = 1MHz
Fc = 140MHz, Fin = 35MHz
Fc = 140MHz, Fin = 70MHz
Fc = 140MHz, error > 4LSB
DV
CC
= +5V
AV
EE
= DV
EE
= 5.2V
1
TPS: Times Per Sample
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