CXA1784AS

E95430A5Z-PK

US Audio Multiplexing Decoder

Description

The CXA1784AS is an IC designed as a decoder

for the Zenith TV Multi-channel System and also

corresponds with I

C BUS. Functions include stereo

demodulation, SAP (Separate Audio Program)

demodulation, dbx noise reduction and sound

processor. Various kinds of filters are built in while

adjustment, mode control and sound processor

control are all executed through I

C BUS.

Features

· Audio multiplexing decoder, dbx noise reduction

decoder and sound processor are all included in a

single chip. Almost any sort of signal processing is

possible through this IC.

· All adjustments are possible through I

C BUS to

allow for automatic adjustment.

· Various built-in filter circuits greatly reduce external

parts.

· There are two systems for both inputs and outputs,

and each mode control is possible.

Standard I/O Level

· Input level

COMPIN (Pin 17)

245 mVrms

AUXIN-L/R (Pins 38 and 37)

490 mVrms

· Output level

TVOUT-L/R (Pins 35 and 34)

490 mVrms

LSOUT-L/R (Pins 6 and 5)

490 mVrms

Pin Configuration (Top View)

Absolute Maximum Ratings (Ta=25°C)

· Supply voltage

· Operating temperature

Topr

20 to +75

°C

· Storage temperature

Tstg

65 to +150

°C

· Allowable power dissipation

2.2

Range of Operating Supply Voltage

9±0.5

Applications

TV, VCR and other decoding systems for US audio

multiplexing TV broadcasting

Structure

Bipolar silicon monolithic IC

Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.

42 pin SDIP (Plastic)

TVOUT-L

TVOUT-R

ITIME

VCATC

VCAWGT

VEOUT

VETC

VEWGT

SAPOUT

GND

NOISETC

VCAIN

SAPIN

SDA

SCL

DGND

SAD

VGR

IREF

MAININ

PLINT

STFIL

COMPIN

SAPTC

SUBOUT

STIN

MAINOUT

BASSL2

TRER

TREL

SURROUT

LSOUT-R

LSOUT-L

BASSL1

BASSR2

BASSR1

AUXIN-L

AUXIN-R

SURRTC

For the availability of this product, please contact the sales office.

CXA1784AS

Block Diagram

VGR

IREF

SAD

DGND

SCL

SDA

SAPOUT

SAPIN

STIN

VEWGT

VETC

VEOUT

VCAIN

VCAWGT

VCATC

MAININ

MAINOUT

SUBOUT

PLINT

STFIL

I
N

I
SET

SAPT

T-

OGIC

I
X

BPF

SAPVC

OIS

SAPI

SAPF

"
P

ES"

I
N

"
SAPL

SAPVD

"
SAP"

"
N

I
SE"

I
N

SAPVC

SAPL

NRS

/
F

SAPC

EXT

/
EXT

/
M

I
D

EBAN

SPEC

"
SAPVC

(
+

4dB

)

S I

/
F

(
+

6dB

)

VOL-L

VOL-R

VOL-S

LSOUT-L

LSOUT-R

SURROUT

I
X

SURR-VOL

VOL-L

VOL-R

TREB

BASS

URRO

UND

EVO

TREBLE

BASS

SURR

PREVOL

BASS

AUXIN-R

AUXIN-L

T-

URRT

BASSL

BASSR

-R

)

CXA1784AS

Symbol

Equivalent circuit

Description

No.

voltage

Pin Description

(Ta = 25 °C, V

= 9 V)

BASSL2

BASSL1

BASSR2

BASSR1

TRER

TREL

SURROUT

LSOUT-R

LSOUT-L

4.0

BASS filter pin. (Left channel)

(Connect a 15 nF capacitor

between Pins 1 and 42.)

The cutoff frequency is

determined by the built-in

resistor and the external

capacitance.

BASS filter pin. (Right

channel) (Connect a 15 nF

capacitor between Pins 41

and 40.)

The cutoff frequency is

determined by the built-in

resistor and the external

capacitance.

TREBLE filter pin. (Right

channel)

(Connect a 6.8 nF capacitor

between this pin and GND.)

TREBLE filter pin. (Left

channel)

(Connect a 6.8 nF capacitor

between this pin and GND.)

(L - R) signal output pin.

LSOUT right channel output

pin.

LSOUT left channel output

pin.

500

13.2k

10.7k

8.57k

6.89k

5.66k

4.44k

3.67k

15.3k

500

4.2k

3.42k

2.73k

2.2k

1.8k

1.42k

1.17k

4.88k

500

CXA1784AS

Symbol

Equivalent circuit

Description

No.

voltage

SDA

SCL

DGND

SAD

VGR

1.3V

Serial data I/O pin.

> 3.0 V

< 1.5 V

Serial clock input pin.

> 3.0 V

< 1.5 V

Digital block GND.

Slave address control switch.

The slave address is selected

by changing the voltage

applied to this pin.

Band gap reference output

pin. (Connect a 10 µF

capacitor between this pin

and GND.)

7.5k

4.5k

7.5k

35µ

2.1V

7.5k

35µ

2.1V

19.5k

40k

80k

10k

11k

9.7k

19.4k

2.06k

147

11k

CXA1784AS

Symbol

Equivalent circuit

Description

No.

voltage

IREF

MAININ

MAINOUT

PLINT

1.3V

4.0V

6.3V

Set the filter and VCO

reference current. The

reference current is adjusted

with the BUS DATA based on

the current which flows to this

pin. (Connect a 62 k

(±1%)

resistor between this pin and

GND.)

Input the (L + R) signal from

MAINOUT (Pin 14).

(L + R) signal output pin.

Pilot cancel circuit loop filter

integrating pin.

(Connect a 1 µF capacitor

between this pin and GND.)

40k

30k

30p 1.8k

16k

6.3k

147

30k

15k

30k

147

23k

47k

10µ

147

15k

200µ

147

15k

26µ

15k

10k

20k

50µ

20k

CXA1784AS

Symbol

Equivalent circuit

Description

No.

voltage

STFIL

COMPIN

SAPTC

SUBOUT

5.3V

4.0V

4.5V

4.0V

Stereo block PLL loop filter

integrating pin.

Audio multiplexing signal

input pin.

Set the time constant for the

SAP carrier detection circuit.

(Connect a 4.7 µF capacitor

between this pin and GND.)

(L - R) signal output pin.

147

150k

75k

12k

500

11k

27.66k

34.86k

27.66k

34.86k

24.06k

27.66k

147

10k

50µ

147

500

14.4k

500

10P

Vcc

CXA1784AS

Symbol

Equivalent circuit

Description

No.

voltage

STIN

SAPIN

NOISETC

GND

SAPOUT

4.0V

3.0V

4.0V

Input the (L - R) signal from

SUBOUT (Pin 19).

Input the (SAP) signal from

SAPOUT (Pin 24).

Supply voltage pin.

Set the time constant for the

noise detection circuit.

(Connect a 4.7 µF capacitor

and a 200 k

resistor

between this pin and GND.)

Analog block GND.

SAP FM detector output pin.

Variable de-emphasis

integrating pin.

(Connect a 2700 pF

capacitor and a 3.3 k

resistor in series between

this pin and GND.)

23k

147

47k

20k

11.7k

23k

147

47k

3.3k

Vcc

10k

Vcc

24k

10µ

500

Vcc

500

50µ

17k

7.4k

147

7.5k

147

CXA1784AS

Symbol

Equivalent circuit

Description

No.

voltage

VEWGT

VETC

VEOUT

VCAIN

4.0V

1.7V

4.0V

Weight the variable de-

emphasis control effective

value detection circuit.

(Connect a 0.047 µF

capacitor and a 3 k

resistor

in series between this pin and

GND.)

Determine the restoration

time constant of the variable

de-emphasis control effective

value detection circuit. (The

specified restoration time

constant can be obtained by

connecting a 3.3 µF capacitor

between this pin and GND.)

Variable de-emphasis output

pin.

(Connect a 4.7 µF non-polar

capacitor between Pins 29

and 30.)

VCA input pin.

Input the variable de-

emphasis output signal from

Pin 29 via a coupling

capacitor.

Vcc

36k

2.9V

500

147

500

30k

8µ

50µ

20k

7.5µ

50µ

Vcc

10k

500

20k

47k

CXA1784AS

Symbol

Equivalent circuit

Description

No.

voltage

VCAWGT

VCATC

ITIME

TVOUT-R

TVOUT-L

4.0V

1.7V

1.3V

4.0V

Weight the VCA control

effective value detection

circuit.

(Connect a 1 µF capacitor

and a 3.9 k

resistor in series

between this pin and GND.)

Determine the restoration

time constant of the VCA

control effective value

detection circuit.

(The specified restoration

time constant can be

obtained by connecting a 10

µF capacitor between this pin

and GND.)

Set the reference current for

the effective value detection

timing current. The reference

current is adjusted with the

BUS DATA "SPECTRAL"

based on the current which

flows to this pin.

The timing current determines

the restoration time constant

of the detection circuit and

the variable de-emphasis

characteristics.

(Connect a 43 k

(±1%)

resistor between this pin and

GND.)

TVOUT right channel output

pin.

TVOUT left channel output

pin.

30k

36k

2.9V

500

500 147

40k

50µ

8µ

50µ

20k

7.5µ

40k

30k

30p 1.8k

2.6V

25k

147

20k

40k 10k

47k

500

CXA1784AS

Symbol

Equivalent circuit

Description

No.

voltage

AUXIN-R

AUXIN-L

SURRTC

4.0V

Right channel external input

pin.

Left channel external input

pin.

Set the central frequency of

the SURROUND circuit phase

shifter.

The frequency is determined

by the built-in resistor and the

external capacitance.

(Connect a 0.022 µF capacitor

between this pin and GND.)

27.6k

47k

147

23k

19.6k

20k

24k

500

23k

40k

CXA1784AS

Electrical Characteristics

COMPIN input level

(100% modulation level)

No.

Item

Current consumption

Main output level

Main de-emphasis frequency

characteristic

Main LPF frequency

characteristic

Main distortion

Main overload distortion

Main S/N

Sub output level

Sub LPF frequency

characteristic

Sub distortion

Sub overload distortion

Sub S/N

Sub pilot leak

Stereo ON level

Stereo ON/OFF hysteresis

Symbol

Icc

Vmain

FCdeem

FCmain

THDm

THDmmax

SNmain

Vsub

FCsub

THDsub

THDsmax

SNsub

PCsub

THst

HYst

Mode

MONO

Input pin

Min.

440

-1.2

-3.0

150

-3.0

-9.0

2.0

Typ.

490

-1.0

0.1

0.15

190

-0.5

0.1

0.2

-30

-6.0

4.0

Max.

540

1.0

0.5

230

1.0

2.0

-22

-3.0

8.0

Unit

mVrms

Input signal

No signal

Mono 1kHz 100% mod.

Pre-em. on

Mono 5kHz 30% mod.

Pre-em. on

Mono 12kHz 30% mod.

Pre-em.on

Mono 1kHz 100% mod.

Pre-em. on

Mono 1kHz 200% mod.

Pre-em off

Mono 1kHz,

Pre-em on

SUB (L-R), 1kHz,

100% mod., NR OFF

SUB (L-R) 12kHz,

30% mod., NR OFF

SUB (L-R) 1kHz,

100% mod., NR OFF

SUB (L-R), 1kHz,

200% mod., NR OFF

SUB (L-R) 1kHz,

NR OFF

PILOT (f

) 0dB

Change

PILOT (f

) Level

Measurement

conditions

20 log ('5k'/'1k')

20 log

('12k'/'1k')

20 log

('100%'/'0%')

20 log

('12k'/'1k')

20 log

('100%'/'0%')

20 log

('out'/'in')

0dB=49mVrms

20 log (`on

level'/'off level')

Filter

15kLPF

BPF

Output pin

34/35

BUS

RETURN

(Ta = 25°C, Vcc = 9V)

INSW1 = 1

INSW2 = 0

= 490mVrms

= 980mVrms

= 98mVrms

= 294mVrms

INSW1 = 0

INSW2 = 1

= 100mVrms

= 200mVrms

= 20mVrms

= 60mVrms

INSW1 = 0, = 1

INSW2 = 0, = 1

= 245mVrms

= 490mVrms

= 49mVrms

= 147mVrms

Main (L + R) (Pre-Emphasis : OFF)

SUB (L R) (dbx-TV :OFF)

Pilot

SAP Carrier

= 15.734kHz

CXA1784AS

No.

Item

SAP output level

SAP LPF frequency

characteristic

SAP distortion

SAP S/N

SAP soft mute

dbx out noise level

SAP ON level

SAP ON/OFF hysteresis

ST separation 1 L

ST separation 1 R

ST separation 2 L

ST separation 2 R

TVOUT output level

TVOUT

cross talk

TVOUT

muted amount

Symbol

Vsap1

Vsap2

FCsap

THDsap1

THDsap2

SNsap

Smute

Ndbx

THsap

HYsap

STLsep1

STRsep1

STLsep2

STRsep2

Vtv

CTtv1

CTtv2

MUtv1

MUtv2

Mode

SAP

EXT

INT

EXT

INT

EXT

Input pin

37/38

Min.

150

370

-3.0

-8.5

-12.0

2.0

-0.5

Typ.

190

490

2.5

0.6

-7.0

-75

-9.0

4.0

-75

-80

Max.

230

610

2.5

6.0

1.5

-5.5

-54

-6.0

6.0

0.5

-59

-70

Unit

mVrms

dBm

Input signal

SAP 1kHz 100% mod.

NR OFF

SAP 1kHz 100% mod.

NR ON

SAP 10kHz, 30% mod.

NR OFF

SAP 1kHz 100% mod.

NR OFF

SAP 1kHz 100% mod.

NR ON

SAP 1kHz, NR OFF

SAP 1kHz, 100% mod.

NR OFF

No signal

Change

SAP Carrier (5f

) Level

ST-L 300Hz 30% mod.

NR ON

ST-R 300Hz 30% mod.

NR ON

ST-L 3kHz 30% mod.

NR ON

ST-R 3kHz 30% mod.

NR ON

Sine wave 1kHz,

490mVrms

Sine wave 1kHz,

490mVrms

MONO 1kHz, 100%,

Pre-em. on

MONO 1kHz, 100%,

Pre-em. on

Sine wave 1kHz,

490mVrms

Measurement

conditions

20 log

('10k'/'1k')

20 log

('100%'/'0%')

0dB=147mVrms

20 log(`on

level'/'off level')

0dB=490mVrms

EXT

INT

0dB=490mVrms

INT

EXT

20 log (M1="0"/M1="1")

Filter

15kLPF

1kBPF

Output pin

34/35

BUS

RETURN

34/35

CXA1784AS

No.

Item

TVOUT DC offset

TVOUT distortion

TVOUT S/N

TVOUT overload distortion

LSOUT output level

LSOUT cross talk

LSOUT muted amount

LSOUT DC offset

LSOUT distortion

LSOUT S/N

LSOUT overload distortion

BASS maximum value

BASS minimum value

TREBLE maximum value

TREBLE minimum value

Volume minimum value

SURROUT volume minimum

value

Symbol

OStv

THDtv

SNtv

THDtvmax

Vls1

Vls2

CTls1

CTls2

MUls

OSls

THDls

SNls

THDlsmax

TBmax

TBmin

TTmax

TTmin

VOLmin

SVOLmin

Mode

INT

EXT

INT

EXT

INT

EXT

INT

EXT

Input pin

37/38

Min.

-25

-0.9

-25

-13

Typ.

0.01

0.1

-75

-80

0.01

0.1

-12

-80

Max.

0.5

1.0

0.9

-59

-70

0.5

1.0

-11

-70

Unit

Input signal

No signal

Sine wave 1kHz,

490mVrms

Sine wave 1kHz,

490mVrms/No signal

Sine wave 1kHz,

2Vrms

MONO 1kHz

100%, Pre-em. on

Sine wave 1kHz,

490mVrms

Sine wave 1kHz,

490mVrms

MONO 1kHz

100%, Pre-em. on

Sine wave 1kHz,

490mVrms

No signal

Sine wave 1kHz,

490mVrms

Sine wave 1kHz,

490mVrms

Sine wave 1kHz,

2Vrms

Sine wave 100Hz,

245mVrms

Sine wave 100Hz,

245mVrms

Sine wave 10kHz,

245mVrms

Sine wave 10kHz,

245mVrms

Sine wave 1kHz,

490mVrms

Sine wave 1kHz,

490mVrms

Measurement

conditions

Mute (M1=0)/DC difference

when there is no signal

20 log ('490mVrms'/'No

signal')

0dB=490mVrms

EXT

INT

0dB=490mVrms

INT

EXT

20 log (M2="0"/M2="1")

Mute (M2=0)/DC difference

when there is no signal

20 lgo ('490mVrms'/'No

signal')

BASS="F"

0dB=245mVrms

BASS="0"

0dB=245mVrms

TREBLE="F"

0dB=245mVrms

TREBLE="0"

0dB=245mVrms

VOL-L="0", VOL-R="0"

0dB=490mVrms

VOL-SURR="0"

0dB=490mVrms

Filter

15kLPF

1kBPF

15kLPF

1kBPF

Output pin

34/35

5/6

CXA1784AS

C BUS block items (SDA, SCL)

C BUS load conditions:

Pull-up resistor 4 k

(Connect to +5 V)

Load capacity 200 pF (Connect to GND)

C BUS Control Signal

High level input voltage

Low level input voltage

High level input current

Low level input current

Low level output voltage SDA (Pin 7) during 3 mA inflow

Maximum inflow current

Input capacitance

Maximum clock frequency

Minimum waiting time for data change

Minimum waiting time for start of data transfer

Low level clock pulse width

High level clock pulse width

Minimum waiting time for start preparation

Minimum data hold time

Minimum data preparation time

Rise time

Fall time

Minimum waiting time for stop preparation

SCL

BUF

:STA

LOW

HIGH

:STA

:DAT

:STO

3.0

4.7

4.0

4.7

4.0

4.7

250

4.7

5.0

1.5

0.4

100

300

µA

kHz

µs

SDA

SCL

BUF

;STA

LOW

;DAT

HIGH

;STA

;STO

;DAT

No.

Item

Symbol

Min.

Typ.

Max.

Unit

CXA1784AS

Electrical Characteristics Measurement Circuit

TVOUT-L

TVOUT-R

ITIME

VCATC

VCAWGT

VEOUT

VETC

VEWGT

SAPOUT

GND

NOISETC

VCAIN

SAPIN

SDA

SCL

DGND

SAD

VGR

IREF

MAININ

PLINT

STFIL

COMPIN

SAPTC

SUBOUT

STIN

MAINOUT

I C BUS DATA

DGND

220

C13

10µ

62k

METAL ±1

C16

4.7µ

C18

1µ

C20

0.47µ

2.2k

C21

0.22µ

C23

4.7µ

C25

4.7µ

C27

4.7µ

SIGNAL

GENERATOR

GND

C28

4.7µ

C26

4.7µ

3.3k

2700p

C24

0.047µ

C22

3.3µ

C19

TANTALUM

C17

4.7µ

1µ

C15

10µ

C14

TANTALUM

43k

METAL ±1

C12

4.7µ

3.9k

C11

4.7µ

BUFF

FILTERS

MEASURES

15kHz LPF

BPF

1kHz BPF

AUXIN-R

LSOUT-L

AUXIN-L

LSOUT-R

SURRTC

SURROUT

BASSR1

TREL

BASSR2

TRER

BASSL1

BASSL2

15n

6.8n

200k

C10

4.7µ

SIGNAL

GENERATOR

SIGNAL

GENERATOR

4.7µ

0.022µ

15n

4.7µ

6.8n

C29

100µ

GND

CXA1784AS

C BUS Register Data Standard Setting Values

Classification A: Adjustment

U: User control

S: Proper to set

T: Test

ATT

STVCO

SAPVCO

SAPLPF

STLPF

SPECTRAL

WIDEBAND

TEST-DA

TEST1

PRE-VOL

VOL-L

VOL-R

VOL-SURR

TREBLE

BASS

SURR

NRSW

FOMO

EXT1

EXT2

EXTFOMO

INSW1

INSW2

SAPC

Center point

Normal mode

F=0dB

3F=0dB

7 or 8=0dB

Surround OFF

According to the modecontrol table

TV decoder output selection

External forced MONO OFF

Mute OFF

Fixed by the set specifications

Adjustment point

Standard setting value

Number Classifi- Standard

Contents

Setting value when electrical

of bits

cation

setting

characteristics are measured

CXA1784AS

List of Adjustment Contents

This is the case when standard input level is 245mVrms. When this level is 100mVrms or

490mVrms, input signal during adjustment is varied according to the ratio of these level.

MAIN VCA

ST VCO

SAP VCO

ST & dbx

FILTER

SAP

FILTER

Low frequency

ST separation

High frequency

ST separation

ATT

STVCO

SAPVCO

STLPF

SAPLPF

WIDEBAND

SPECTRAL

COMPIN

(Pin 17)

None

COMPIN

(Pin 17)

COMPIN

(Pin 17)

COMPIN

(Pin 17)

COMPIN

(Pin 17)

COMPIN

(Pin 17)

100Hz

245mVrms

None

(78.67k)

147mVrms

9.4kHz

600mVrms

88kHz

110mVrms

ST-L 30%

300Hz

ST-L 30%

3kHz

TVOUT-L output

level

TVOUT-R output

frequency

STA7

(SAPVCO1)

STA8

(SAPVCO2)

STA3

(STLPF)

STA4

(SAPLPF)

TVOUT-R output

level

TVOUT-R output

level

Adjust as close to 490 mVrms

as possible

Adjust as close to 62.936 kHz as

possible

Adjust to the center of the

SAPVCO1 = 0, SAPVCO2 = 1

condition

Adjust to the center of the

STLPF = 1 condition

Adjust to the center of the

SAPLPF = 1 condition

Minimize the output level

TEST-DA=1

TEST1=1

Adjustment

Input pin

Input

Measurement

Adjustment contents

Test mode

item

data

signal data

setting

CXA1784AS

Adjustment Method

(Input signal level is the case when standard input signal level is 245mVrms)

ATT adjustment

1. TEST BIT is set to "TEST1 = 0" and "TEST-DA = 0".

2. Input a 100 Hz, 245 mVrms sine wave signal to COMPIN and monitor the TVOUT-L output level.

Then, adjust the "ATT" data for ATT adjustment so that the TVOUT-L output goes to the standard

value.

3. Adjustment range:

±30%

Adjustment bits:

4 bits

Stereo VCO adjustment

1. TEST BIT is set to "TEST1 = 0" and "TEST-DA = 1".

2. Monitor the TVOUT-R output (4f

free running) frequency in a no input state, and adjust "STVCO"

adjustment data so that this frequency is as close to 4f

(62.936 kHz) as possible.

3. Adjustment range:

±20%

Adjustment bits:

6 bits

SAPVCO adjustment

1. TEST BIT is set to "TEST1 = 0" and "TEST-DA = 0".

2. Input a 5f

(SAP carrier , 78.67 kHz) , 147 mVrms sine wave signal to COMPIN. While monitoring the

STATUS FLAG (STA7, STA8) condition, adjust "SAPVCO" adjustment data.

3. Adjustment range:

±20%

Adjustment bits:

4 bits

Align SAPVCO with the center of the STA7 = 0 and STA8 = 1 (adjustment OK) condition range.

Stereo block dbx filter adjustment

1. TEST BIT is set to "TEST1 = 1" and "TEST-DA = 0".

2. Input a 9.4 kHz, 600 mVrms sine wave signal to COMPIN. While monitoring the STATUS FLAG

(STA3) condition, adjust the "STLPF" adjustment data.

3. Adjustment range:

±20%

Adjustment bits:

6 bits

Align STLPF with the center of the STA3 = 1 (adjustment OK) condition range.

1
0

Control data
"SAPVCO"

Measurement data
STA7 "SAPVCO1"

STA8 "SAPVCO2"

Adjustment point

1
0

Control data
"STLPF"

Measurement data
STA3 "STLPF"

CXA1784AS

SAP block filter adjustment

1. TEST BIT is set to "TEST1 = 1" and "TEST-DA = 0".

2. Input a 88 kHz, 110 mVrms sine wave signal to COMPIN. While monitoring the STATUS FLAG (STA4)

condition, vary and adjust the "SAPLPF" adjustment data.

3. Adjustment range:

±20%

Adjustment bits:

4 bits

Align SAPLPF with the center of the STA4 = 1 (adjustment OK) condition range.

Separation adjustment

1. TEST BIT is set to "TEST1 = 0" and "TEST-DA = 0".

2. Set the unit to stereo mode and input the left channel only signal (modulation factor 30%, frequency

300 Hz NR-ON) to COMPIN. At this time, adjust the "WIDEBAND" adjustment data to reduce TVOUT-

R output to the minimum.

3. Next, set the frequency only of the input signal to 3 kHz and adjust the "SPECTRAL" adjustment data

to reduce TVOUT-R output to the minimum.

4. Then, the adjustments in 2 and 3 above are performed to optimize the separation.

5. "WIDEBAND"

"SPECTRAL"

Adjustment range:

±30%

Adjustment range: ±15%

Adjustment bits:

6 bits

Adjustment bits:

6 bits

Adjustment point

1
0

Control data
"SAPLPF"

Measurement data
STA4 "SAPLPF"

CXA1784AS

Description of Operation

The US audio multiplexing system possesses the base band spectrum shown in Fig. 1.

Fig. 1. Base band spectrum

Fig. 2. Overall block diagram (See Fig. 3 for the dbx-TV block)

Fig 3. dbx-TV block

PEAK DEV

kHz

L+R

50-15kHz

L-R

dbx-TV

AM-DSB-SC

SAP

dbx-TV NR

FM 10kHz

50-10kHz

TELEMETRY

FM 3kHz

=15.734kHz

6.5f

PILOT

(COMPIN)

STEREO LPF

PLL

(VCO 8f

)

0°

90°

0°

C BUS

DECODER
MODE
CONTROL

PILOT

DET

MVCA

PILOT

CANCEL

MAIN LPF DE.EM

(MAIN OUT)

L+R

4.7µ

(MAIN IN)

L-R (DSB)

DET

INJ.

LOCK

SUBVCA

SUB LPF

WIDEBAND (SUBOUT) (ST IN)

4.7µ

NR SW

dbx-TV

BLOCK

MATRIX

(Lch)

(Rch)

MODE

CONTROL

(SAP IN)

4.7µ

SAP(FM)

DET

SAP LPF

C BUS

DECODER
MODE
CONTROL

SAP BPF

(SAP OUT)

L-R

NOISE

DET

C BUS

DECODER

SAP

DET

NR SW

FIXED

DEEMPHASIS

VARIABLE

DEEMPHASIS (VE OUT)

(VCA

IN)

MATRIX

4.7µ

HPF

LPF

RMS

DET

RMS

DET

VCA

CXA1784AS

Fig. 4. Sound processor block

(1) L + R (MAIN)

After the audio multiplexing signal input from COMPIN (Pin 17) passes through MVCA, the SAP signal

and telemetry signal are suppressed by STEREO LPF. Next, the pilot signals are canceled. Finally, the

L - R signal and SAP signal are removed by MAIN LPF, and frequency characteristics are flattened

(de-emphasized) and input to the matrix.

(2) L - R (SUB)

The L - R signal follows the same course as L + R before the pilot signal is canceled. L - R has no

carrier signal, as it is a suppressed-carrier double-sideband amplitude modulated signal (DSB-AM

modulated). For this reason, the pilot signal is used to regenerate the carrier signal (quasi-sine wave)

to be used for the demodulation of the L - R signal. In the last stage, the residual high frequency

components are removed by SUB LPF and the L - R signal is input to the dbx-TV block via the NRSW

circuit after passing through SUBVCA.

(3) SAP

SAP is an FM signal using 5f

as a carrier as shown in the Fig. 1. First, the SAP signal only is

extracted using SAP BPF. Then, this is subjected to FM detection. Finally, residual high frequency

components are removed and frequency characteristics flattened using SAP LPF, and the SAP signal

is input to the dbx-TV block via the NRSW circuit. When there is no SAP signal, the Pin 24 output is

soft muted.

(4) Mode discrimination

Stereo discrimination is performed by detecting the pilot signal amplitude. SAP discrimination is

performed by detecting the 5f

carrier amplitude. NOISE discrimination is performed by detecting the

noise near 25 kHz after FM detection of SAP signal.

(5) dbx-TV block

Either the SAP signal or L - R signal input respectively from ST IN (Pin 20) or SAP IN (Pin 25) is

selected by the mode control and input to the dbx-TV block.

The input signal then passes through the fixed de-emphasis circuit and is applied to the variable de-

emphasis circuit. The signal output from the variable de-emphasis circuit passes through an external

capacitor and is applied to VCA (voltage control amplifier). Finally, the VCA output is converted from a

current to a voltage using an operational amplifier and then input to the matrix.

(Lch) (Rch)

(AUXIN-L)

(AUXIN-R)

from MATRIX

(LSOUT-R)

(LSOUT-L)

(SURROUT)

SW1

(TVOUT-L)(TVOUT-R)

SW2

SURROUND

PREVOL

BASS

TREBLE

VOL-L

VOL-R

VOL-S

CXA1784AS

The variable de-emphasis circuit transmittance and VCA gain are respectively controlled by Each of

effective value detection circuits. Each of the effective value detection circuits passes the input signal

through a predetermined filter for weighting before the effective value of the weighted signal is

detected to provide the control signal.

(6) Matrix, SW1, SW2

The signals (L + R, L - R, SAP) input to "MATRIX" become the outputs for the ST-L, ST-R, MONO and

SAP signals according to the BUS data and whether there is ST/SAP discrimination.

"SW1" and "SW2" switch the "MATRIX" output signal, external input signal (input to AUXIN-L, R (Pins

38 and 37)) and external forced MONO.

Signals selected by "SW1" are output to TVOUT.

Signals selected by "SW2" pass through the sound processor and are output to LSOUT.

(7) Sound processor block

The sound processor block contains "PREVOL", "BASS/TREBLE" tone control functions,

"SURROUND" (quasi-surround function) and "VOLUME".

BASS:

±12 dB (±1.7 dB/STEP at 100 Hz)

TREBLE:

±12 dB (±1.7 dB/STEP at 10 kHz)

VOLUME: 0 to -80 dB (-1.25 dB/STEP)

"PREVOL" controls the input signal level of the sound processor block. When turning on the bass

boost, treble boost or surround, attenuate the input signal to the sound processor block using

"PREVOL" so that the signal is not dissipated inside the processor.

PREVOL: 0 to -13.75 dB (-1.25 dB/STEP)

(8) Surround

At "SURROUND", the L and R differential components are phase-shifted and these components are

added to the left and right channels.

When surround is OFF (SURR = 0)

Inputs are output as is.

{

Lout = Lin

Rout = Rin

When surround is ON (SURR = 1)

Lout = Lin-

1-j

(Lin-Rin)

{

1+j

Rout = Rin+

1-j

(Lin-Rin)

1+j

{

R = 24 k

(IC on-chip)

C = 0.022 µF (Externally attached to Pin 39)

(Lin, Lout) and (Rin, Rout) indicate the left- and right- channel I/O of the surround circuit.

CXA1784AS

(9) Others

"MVCA" is a VCA which adjusts the input signal level to the standard level of this IC.

Standard input level can be selected by INSW1 or INSW2.

"Bias" supplies the reference voltage and reference current to the other blocks. The current flowing to

the resistor connecting IREF (Pin 12) and ITIME (Pin 33) with GND become the reference current.

Standard input and output levels

1 MONO, 25kHz Deviation, Pre-Em. off

2 MONO, 25kHz Deviation, Pre-Em. on

3 VOLUME MAX, PREVOL MAX

Input pin

COMPIN

AUXIN

INSW1

INSW2

Input level

245mVrms

490mVrms

100mVrms

490mVrms

TVOUT output level

490mVrms

LSOUT output level

490mVrms

CXA1784AS

Register Specifications

Slave address

: Don't Care

Status Registers

When TEST1 = 0

When TEST1 = 1

STA1

STA2

STA3

STA4

STA5

STA6

STA7

STA8

BIT7

BIT6

BIT5

BIT4

BIT3

BIT2

BIT1

BIT0

POWER

STEREO

SAP

NOISE

SAP VCO1

SAP VCO2

ON RESET

STA1

STA2

STA3

STA4

STA5

STA6

STA7

STA8

BIT7

BIT6

BIT5

BIT4

BIT3

BIT2

BIT1

BIT0

POWER

STEREO

STLPF

SAPLPF

ON RESET

SAD pin

SLAVE RECEIVER

SLAVE TRANSMITTER

GND

80H

81H

8AH

8BH

SUB ADDRESS

MSB

LSB

0000

0001

0010

0011

0100

0101

0110

0111

1000

1001

1010

1011

1100

DATA

BIT7

BIT6

BIT5

BIT4

BIT3

BIT2

BIT1

BIT0

INSW2

INSW1

TEST-DA

TEST1

ATT (4)

INPUT LEVEL adj

STVCO (6) STEREO VCO adj

(SAPVCO (4) SAP VCO adj)

(SAPLPF (4) SAP FILTER adj)

STLPF (6) ST FILTER adj

SPECTRAL (6)

WIDEBAND (6)

EXTFOMO

EXT1

EXT2

NRSW

FOMO

SAPC

SURR

PR-VOL (4) Pre vol cont.

VOL-L (6) Lch vol cont.

VOL-R (6) Rch vol cont.

VOL-SURR (6) Surr vol cont.

TREBLE (4)

BASS (4)

CXA1784AS

Description of Registers

Control registers

Classification U: User control

A: Adjustment

S: Proper to set

T: Test

ATT

STVCO

SAPVCO

SAPLPF

STLPF

SPECTRAL

WIDEBAND

TEST-DA

TEST1

PRE-VOL

VOL-L

VOL-R

VOL-SURR

TREBLE

BASS

SURR

NRSW

FOMO

EXT1

EXT2

EXTFOMO

INSW1

INSW2

SAPC

Number of bits

Classification

Contents

Input level adjustment

STEREO VCO free running frequency adjustment

SAP VCO free running frequency adjustment

SAP filter adjustment

STEREO and dbx filter adjustment

Adjustment of stereo separation (3 kHz)

Adjustment of stereo separation (300 Hz)

Turn to DAC test mode and STVCO adjustment mode by

means of TEST-DA = 1.

Turn to test mode by means of TEST = 1. (Adjustment of

STLPF and SAPLPF)

Input signal level control of sound processor block

LSOUT-L output signal level control

LSOUT-R output signal level control

SURROUT output signal level control

LSOUT output treble control

LSOUT output bass control

Selection of quasi-surround function ON/OFF (0: OFF, 1:

ON)

Selection of the output signal (Stereo mode, SAP mode)

Turn to forced MONO by means of FOMO = 1. (Left channel

only is MONO during SAP output.)

Selection of TV mode or external input mode for TVOUT

output

Selection of TV mode or external input mode for LSOUT

output

Forced MONO for external input (1: forced MONO ON)

Selection of TVOUT mute ON/OFF

(0: mute ON, 1: mute OFF)

Selection of LSOUT mute ON/OFF

(0: mute ON, 1: mute OFF)

Select of standard input level.

Selection of SAP mode or L + R mode according to the

presence of SAP broadcasting

CXA1784AS

Status registers

Description of Control Registers

ATT (4):

Adjust the signal level input to COMPIN (Pin 17) to the standard input level.

Variable range of the input signal:

standard input level -5.0 dB to +3.0 dB

0 = Level min.

F = Level max.

STVCO (6):

Adjust STEREO VCO free running frequency (fo).

Variable range:

fo ±20%

0 = Free running frequency min.

3F= Free running frequency max.

SAPVCO (4):

Adjust SAPVCO free running frequency (fo).

Variable range:

fo ±20%

0 = Free running frequency min.

F = Free running frequency max.

SAPLPF (4):

Adjust the filter fo of the SAP block.

Variable range:

fo ±20%

0 = Frequency min.

F = Frequency max.

STLPF (6):

Adjust the filter fo of the ST and dbx blocks.

Variable range:

fo ±20%

0 = Frequency min.

3F= Frequency max.

SPECTRAL (6): Perform high frequency (fs = 3 kHz) separation adjustment.

0 = Level max.

3F= Level min.

WIDEBAND (6): Perform low frequency (fs = 300 Hz) separation adjustment.

0 = Level min.

3F= Level max.

PONRES

STEREO

SAP

NOISE

STLPF

SAPLPF

SAPVCO1

SAPVCO2

Number of bits

Contents

POWER ON RESET detection;

1: RESET

Stereo discrimination of the COMPIN input signal;

1: Stereo

SAP discrimination of the COMPIN input signal;

1: SAP

Noise level discrimination of the SAP signal;

1: Noise

Status of STEREO filter adjustment;

1: OK range

Status of SAP filter adjustment;

1: OK range

Status 1 of SAP VCO free running frequency adjustment;0: OK range

Status 2 of SAP VCO free running frequency adjustment;1: OK range

CXA1784AS

TEST1 (1):

Set filter adjustment mode.

0 = Normal mode

1 = STLPF (STA3) and SAPLPF (STA4) adjustment mode

In addition, the following outputs are present at Pins 35 and 34.

TVOUT-L (Pin 35):

SAP BPF OUT

TVOUT-R (Pin 34):

NR BPF OUT

TEST-DA (1):

Set DAC output test mode and STVCO adjustment mode.

0 = Normal mode

1 = DAC output test mode and STVCO adjustment mode

In addition, the following outputs are present at Pins 35 and 34.

TVOUT-L (Pin 35):

DA control DC level

TVOUT-R (Pin 34):

STEREO VCO oscillation frequency (4fH)

PRE-VOL (4):

Input signal level control of sound processor block

When turning on the bass boost, treble boost or surround, attenuate the input signal to the

sound processor block using "PREVOL" so that the signal is not dissipated inside the

processor.

4 = Volume Min. (-13.75 dB)

F = Volume Max. (0 dB)

-1.25 dB/STEP

VOL-L (6):

LSOUT-L output signal level control

0 = Volume Min. (-80 dB)

3F= Volume Max. (0 dB)

-1.25 dB/STEP

VOL-R (6):

LSOUT-R output signal level control

0 = Volume Min. (-80 dB)

3F= Volume Max. (0 dB)

-1.25 dB/STEP

VOL-SURR (6):

SURROUT output signal level control

0 = Volume Min. (-80 dB)

3F= Volume Max. (0 dB)

-1.25 dB/STEP

TREBLE (4):

LSOUT output treble control

0 = Treble Min.

7 & 8 = Treble Center (0 dB)

F = Treble Max.

BASS (4):

LSOUT output bass control

0 = Bass Min.

7 & 8 = Bass Center (0 dB)

F = Bass Max.

CXA1784AS

SURR (1):

Surround function selection

0 = Surround OFF

1 = Surround ON

NRSW (1):

Select stereo mode or SAP mode

0 = Stereo mode

1 = SAP mode

FOMO (1):

Select forced MONO mode

0 = Normal mode

1 = Forced MONO mode

SAPC (1):

Select the SAP signal output mode

When there is no SAP signal, the conditions for selecting SAP output are selected by

SAPC.

0 = L + R output is selected

1 = SAP output is selected

INSW1 (1) &

Select standard input level of COMPIN(Pin 17)

INSW2 (1):

Standard input level

INSW1 = 0 , INSW2 = 0

}

245mVrms

= 1 ,

= 1

INSW1 = 1 , INSW2 = 0

490mVrms

INSW1 = 0 , INSW2 = 1

100mVrms

EXT1 (1):

Select TV mode or external input mode for TVOUT output.

0 = TV mode

1 = External input mode

EXT2 (1):

Select TV mode or external input mode for LSOUT output.

0 = TV mode

1 = External input mode

EXT-FOMO (1): Turn external input to forced MONO.

0 = Normal mode

1 = External input is forced MONO.

Input the same signal to both AUXIN-L and AUXIN-R.

M1 (1):

Mute the TVOUT-L and TVOUT-R output.

0 = Mute ON

1 = Mute OFF

M2 (1):

Mute the LSOUT-L and LSOUT-R output.

0 = Mute ON

1 = Mute OFF

CXA1784AS

Description of Mode Control

Priority ranking: M1/M2 > EXT1/EXT2 > TEST-DA > TEST1 > (NRSW & FOMO & SAPC)

Mode control

NRSW

FOMO

SAPC

M1/M2

EXT1/EXT2

TEST1

TEST-DA

SAPC=0

"Select dbx input and TV decoder output"

Conditions: FOMO = 0

NRSW = 0 (MONO or ST output)

· During ST input:

left channel:L,

right channel: R

· During other input:

left channel:L + R,

right channel: L + R

NRSW = 1 (SAP output)

· When there is "SAP" during SAP

discrimination

- left channel: SAP, right channel: SAP

· When there is "No SAP", output is the

same as when NRSW = 0.

"Forced MONO"

FOMO = 1

· During SAP output: left channel: L + R, right channel: SAP

· During ST or MONO output: left channel: L + R, right channel: L + R

Change the selection conditions for "MONO or ST output" and "SAP output".

SAPC = 0:

Switch to SAP output when there is SAP discrimination.

Do not switch to SAP output when there is no SAP discrimination.

SAPC = 1:

Switch to SAP output regardless of whether there is SAP discrimination.

"MUTE"

M1 = 0: TVOUT output is muted.

M2 = 0: LSOUT output is muted.

"TV mode/external input mode selection"

EXT1 = 0:

Set TVOUT output to TV mode.

EXT1 = 1:

Set TVOUT output to external input mode.

EXT2 = 0:

Set LSOUT output to TV mode.

EXT2 = 1:

Set LSOUT output to external input mode.

"TEST1"

TEST1 = 1

Return adjustment data with STATUS REGISTER as an adjustment mode.

In addition, outputs are as follows.

left channel: SAP BPF OUT

right channel: NR BPF OUT

"TEST-DA"

TEST-DA = 1

Used to adjust the D/A TEST and STVCO.

left channel: D/A output

right channel: STVCO oscillation frequency (4f

)

SAPC=1

"Select dbx input and TV decoder output"

Conditions: FOMO = 0

NRSW = 0 (MONO or ST output)

As on the left

NRSW = 1 (SAP output)

· Regardless of the presence of SAP

discrimination,

dbx input: "SAP"

left channel: SAP, right channel: SAP

However, when there is no SAP, SAPOUT

output is soft muted (-7 dB)

CXA1784AS

Decoder Output and Mode Control Table 1 (SAPC = 1)

Note

(SAP) : The SAPOUT output signal is soft muted (approximately -7 dB).

The signal is soft muted when NOISE = 1.

: Don't care.

1): SAP or NOISE discrimination may be made during MONO or STEREO input when the noise

is inputted in the weak electric field.

"NOISE" status rises earlier than "SAP" status when the amount of noise is increased to COMPIN.

Input signal mode

Mode detection

Mode control

dbx

Output

SAP

NOISE

NRSW

FOMO

SAPC

input

Lch

Rch

MUTE

L+R

SAP

MONO

SAP

L+R

SAP

MUTE

L+R

(SAP)

L+R

(SAP)

L-R

MUTE

L+R

L-R

STEREO

MUTE

L+R

SAP

L+R

SAP

(SAP)

L+R

(SAP)

MUTE

L+R

MUTE

L+R

MONO & SAP

SAP

L+R

SAP

(SAP)

L+R

(SAP)

L-R

MUTE

L+R

STEREO & SAP

SAP

L+R

SAP

(SAP)

L+R

(SAP)

CXA1784AS

Decoder Output and Mode Control Table 2 (SAPC = 0)

Note

(SAP) : The SAPOUT output signal is soft muted (approximately -7 dB).

The signal is soft muted when NOISE = 1.

: Don't care.

1): SAP or NOISE discrimination may be made during MONO or STEREO input when the noise

is inputted in the weak electric field.

"NOISE" status rises earlier than "SAP" status when the amount of noise is increased to COMPIN.

Input signal mode

Mode detection

Mode control

dbx

Output

SAP

NOISE

NRSW

FOMO

SAPC

input

Lch

Rch

MUTE

L+R

MUTE

L+R

MONO

MUTE

L+R

(SAP)

L+R

(SAP)

L-R

MUTE

L+R

L-R

STEREO

MUTE

L+R

L-R

MUTE

L+R

(SAP)

L+R

(SAP)

MUTE

L+R

MUTE

L+R

SAP

MONO & SAP

SAP

L+R

SAP

MUTE

L+R

MUTE

L+R

(SAP)

L+R

(SAP)

L-R

MUTE

L+R

SAP

STEREO & SAP

SAP

L+R

SAP

L-R

MUTE

L+R

(SAP)

L+R

(SAP)

CXA1784AS

Mode Control Table 3

C BUS Signal

There are two I

C signals, SDA (Serial DATA) and SCL (Serial CLOCK) signals. SDA is a bidirectional

signal.

· Accordingly there are 3 values outputs, H, L and HIZ.

· I

C transfer begins with Start Condition and ends with Stop Condition.

SDA

SCL

Start Condition S

Stop Condition P

HIZ

EXT1

EXT2

EXTFOMO

TV OUT-L

TV mode L channel

EXT mode L channel

TV mode L channel

EXT mode L channel

MUTE

Selected according to

the EXT1, EXT2,

EXTFOMO conditions

TV OUT-R

TV mode R channel

EXT mode R channel

EXT mode L channel

TV mode R channel

EXT mode R channel

EXT mode L channel

MUTE

Selected according to

the EXT1, EXT2,

EXTFOMO conditions

LS OUT-L

TV mode L channel

EXT mode L channel

Selected according to

the EXT1, EXT2,

EXTFOMO conditions

MUTE

LS OUT-R

TV mode R channel

EXT mode R channel

EXT mode L channel

EXT mode R channel

EXT mode L channel

Selected according to

the EXT1, EXT2,

EXTFOMO conditions

MUTE

CXA1784AS

· I

C data Write (Write from I

C controller to the IC)

Data can be transferred in 8-bit units to be

set as required.

Sub address is incremented automatically.

· I

C data Read (Read from the IC to I

C controller)

· Read timing

Data Read is performed during SCL rise.

Address

SCL

ACK

DATA

ACK

SDA

H during Read

HIZ

DATA

IC output SDA

SCL

MSB

LSB

ACK

Read timing

ACK

DATA

HIZ

DATA(n)

DATA(n+1)

ACK

DATA(n+2)

HIZ

LSB

MSB

Address

SDA

SCL

MSB

L during Write

MSB

LSB

HIZ

ACK

Sub Address

ACK

CXA1784AS

Input level vs. Distortion characteristics 1 (MONO)

Distortion (%)

1.0

0.1

Standard level (100%)

Input signal: MONO (Pre-emphasis on), 1 kHz
0 dB = 100% modulation level
V

= 9 V, 30 kHz using LPF

Measurement point: TVOUT-L/R

Input level vs. Distortion characteristics 2 (Stereo)

Distortion (%)

1.0

Input level (dB)

Standard level (100%)

Input signal: Stereo L = -R
(dbx-TVNR ON), 1 kHz
0 dB = 100% modulation level
V

= 9 V, 30 kHz using LPF, ST mode

Measurement point: TVOUT-L/R

Input level vs. Distortion characteristics 3 (SAP)

Distortion (%)

1.0

Input level (dB)

Standard level (100%)

Input signal: SAP (dbx-TVNR ON)
1 kHz, 0 dB = 100% modulation
level
V

= 9 V, 30 kHz using LPF, SAP mode

Measurement point: TVOUT-L/R

Input level (dB)

CXA1784AS

Frequency (kHz)

Gain (dB)

Stereo LPF frequency characteristics

100

70 100

Gain (FC main and FC sub) (dB)

100

120

SAP frequency characteristics and group delay

Group delay (µ

100

Gain

Group delay

3.8f

6.2f

Frequency (kHz)

Main LPF and Sub LPF frequency characteristics

Gain (dB)

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: CXA1784AS

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: CXA1784AS