Description

The CXA1386P/K are 8-bit high-speed flash A/D

converter ICs capable of digitizing analog signals at
the maximum rate of 75MSPS. The digital I/O levels
of these A/D converters are compatible with the
ECL 100K/10KH/10K.

The CXA1386P/K is pin-compatible with the

earlier models CXA1056P/K, CXA1016P/K,
respectively.

They can be replaced by the

CXA1386P/K without any design changes, in most
cases. Compared with the earlier models, these
new models have been greatly improved in
performance, by incorporating advanced process,
new circuit design and carefully considered layout.

Features
· Differential linearity error: ±1/2LSB or less
· Integral linearity error: ±1/2LSB or less
· High-speed operation with maximum conversion

rate of 75MSPS (Min.)

· Wide analog input bandwidth: 150MHz (Min. for

full-scale input)

· Low Power consumption: 580mW (Typ.)
· Single power supply: 5.2V
· Low input capacitance: 17pF (Typ.)
· Built-in integral linearity conpensation circuit
· Low error rate
· Operable at 50% clock duty cycle
· Good temperature characteristics
· Capable of driving 50

loads

Pin Configuration

Pins with name are NC pins (not connected).

Structure

Bipolar silicon monolithic IC

Applications

· Digital oscilloscopes

· HDTV (high-definition TVs)

· Other apparatus requiring high-speed A/D

conversion

CXA1386P/K

E90114C54-ST

8-bit 75MSPS Flash A/D Converter

Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.

CXA1386K

44 pin LCC (Ceramic)

CXA1386P

28 pin DIP (Plastic)

CXA1386P

CLK

AGND

CLK

LINV

DGND

(LSB) D0

DGND

MINV

(MSB) D7

(LSB) D0

8 9 10 11 12 13 14 15 16 17

CXA1386K

(MSB) D7

DGND2

38 37 36 35 34 33 32 31 30 29

CLK

MINV

DGND1

DGND2

LINV

DGND1

AGND

CXA1386P/K

Absolute Maximum Ratings (Ta = 25°C)

· Supply voltage

, DV

7 to +0.5

· Analog input voltage

2.7 to +0.5

· Reference input voltage

, V

2.7 to +0.5

I V

2.5

· Digital input voltage

CLK, CLK, MINV, LINV

4 to +0.5

I CLK CLK I

2.7

· V

pin input current

VRM

3 to +3

· Digital output current

to ID

30 to 0

· Storage temperature

Tstg

65 to +150

°C

Recommended Operating Conditions

Min.

Typ.

Max.

Unit

· Supply voltage

, DV

5.5

5.2

4.95

0.05

+0.05

AGND DGND

0.05

+0.05

· Reference input voltage

0.1

+0.1

2.2

2.0

1.8

· Analog input voltage

· Pulse width of clock

PW1

6.6

PW0

6.6

· Operating temperature

Tc (CXA1386K)

+100

°C

Ta (CXA1386P)

+75

°C

CXA1386P/K

Block Diagram

255

126

127

128

129

191

192

193

254

CLOCK

DRIVER

r/2

D7 (MSB)

D0 (LSB)

OGIC

MINV

CLK

LINV

Comparator

CXA1386P/K

Pin Description and I/O pin Equivalent circuit

Anlog GND.
Used as GND for input
buffers and latches of
comparators.
Isolated from DGND or
DGND 1/2.

19, 21,

23, 25

31, 33,

35, 37

AGND

18, 26,

3, 12

DGND

CLK

ECL

27, 28,
40, 41,

5.2V

Analog V

5.2V (Typ.).
Internally connected
with DV

(resistance: 4 to 6

Ceramic chip
capacitors of at least
0.1µF should be used
to connect to AGND
and be placed near
the pins.

CLK input

Input complementary
to CLK.
With open connection,
kept at threshold
voltage (1.3V).
Device is operable
without CLK input, but
use of complementary
inputs of CLK and CLK
is recommended to
obtain the stable high-
speed operation.

Digital GND (Used for
internal circuits and
output transistors)

Pin No

DIP

LCC

Symbol

I/O

Standard

voltage

level

Equivalent circuit

Description

DGND (DGND1)

CLK

5, 19

DGND1

Digital GND (Used for
internal circuits)

6, 16

DGND2

Digital GND (Used for
output buffers)

CXA1386P/K

2, 13

4, 20

5.2V

Digital V

Internally connected
with AV

(resistance: 4 to 6

)

Ceramic chip
capacitors of at least
0.1µF should be used
to connect to DGND
and be placed near the
pins.

LSB of data outputs.
External pull-down
resistor is required.

Data outputs.
External pull-down
resistors are required.

MSB of data outputs.
External pull-down
resistor is required.

Input pin for D0 (LSB)
to D6 output polarity
inversion (see output
code table).
With open connection,
kept at "L" level.

Input pin for D7 (MSB)
output polarity
inversion (see output
code table).
With open connection,
kept at "L" level.

MINV

ECL

LINV

ECL

DGND (DGND2)

LINV

MINV

1.3V

DGND (DGND1)

Pin No

DIP

LCC

Symbol

I/O

Standard

voltage

level

Equivalent circuit

Description

CXA1386P/K

Reference voltage
(bottom)
Typically 2V
A ceramic capacitor of
at least 0.1µF and a
tantalus capacitor of at
least 10µF should be
used to connect to
AGND and be placed
near the pins.

Reference voltage mid
point be used as a pin
for integral linearity
compensation

Reference voltage
(top) Typically 0V
When a voltage
different from AGND is
applied to this pin, a
ceramic capacitor of at
least 0.1µF and a
tantalus capacitor of at
least 10µF should be
used to connect to
AGND and be placed
near the pins.

Unused pins
No internal connections
have been made to
these pins.
Connecting them to
AGND or DGND on PC
board is recommended.

1, 2,

7, 17,

18, 24,
25, 29,

30, 38
39, 43

Pin No.

DIP

LCC

Symbol

I/O

Standard

voltage

level

Equivalent circuit

Description

Comparator

127

Comparator

128

Comparator

129

Comparator

130

Comparator

255

r/2

Analog input pins.
These two pins must
be connected
externally, since they
are not internally
connected.
See Application Note
for precautions.

20, 24

32, 36

AGND

CXA1386P/K

Electrical Characteristics

(Ta = 25°C, AV

= DV

= 5.2V, V

= 0V, V

= 2V)

Item

Resolution

DC characteristics

Integral linearity error
Differential linearity error

Analg input

Analog input capacitance
Analog input resistance
Input bias current

Reference inputs

Reference resistance
Offset voltage

Digital inputs

Logic H level
Logic L level
Logic H current
Logic L current
Input capacitance

Switching characteristics

Maximum conversion rate
Aperture jitter
Sampling delay
Output delay
H pulse width of clock
L pulse width of clock

Digital outputs

Logic H level
Logic L level
Output rising time
Output falling time

Dynamic characteristics

Input bandwidth

S/N ratio

Error rate

Differential gain error
Differential phase error

Power supply

Supply current
Power consumption

REF

Fc
Taj
Tds
Tdo
T

PW1

PW0

Tr
Tf

DG
DP

Fc = 75MSPS
Fc = 75MSPS

= 1V + 0.07Vrms

= 1V

Input connected to 0.8V
Input connected to 1.6V

Error rate 10

TPS

= 620

to DV

= 620

to DV

= 620

to DV

, 20% to 80%

= 620

to DV

, 80% to 20%

= 2Vp-p

Input frequency at 3dB

Input = 1MHz, FS
Clock = 75MHz
Input = 18.75MHz, FS
Clock = 75MHz
Input = 18.749MHz, FS
Error > 16LSB
Clock = 75MHz
NTSC 40IRE mod. ramp,
Fc = 75MSPS

8
0

1.13

4.0
6.6
6.6

1.03

150

±0.3
±0.3

390

110

18
10

3.0
6.5

0.9
2.1

1.0
0.5

104

580

±0.5
±0.5

200

155

32
24

1.50

50
50

9.0

1.62

bits

LSB
LSB

µA

mV
mV

V
V

µA
µA

MSPS

ps
ns
ns
ns
ns

V
V

ns
ns

MHz

TPS

deg

Symbol

Condition

Min.

Typ.

Max.

Unit

{
{

}

{

TPS: Times Per Sample

Pd = I

· V

REF

)

CXA1386P/K

Output Code Table

0
1

127
128

254
255

0 0 0 ······ 0 0

0 0 0 ······ 0 0
0 0 0 ······ 0 1

:
:

0 1 1 ······ 1 1
1 0 0 ······ 0 0

:
:

1 1 1 ······ 1 0
1 1 1 ······ 1 1

1 1 1 ······ 1 1

1 0 0 ······ 0 0

1 0 0 ······ 0 0
1 0 0 ······ 0 1

:
:

1 1 1 ······ 1 1
0 0 0 ······ 0 0

:
:

0 1 1 ······ 1 0
0 1 1 ······ 1 1

0 1 1 ······ 1 1

0 1 1 ······ 1 1
0 1 1 ······ 1 0

:
:

0 0 0 ······ 0 0
1 1 1 ······ 1 1

:
:

1 0 0 ······ 0 1
1 0 0 ······ 0 0

1 0 0 ······ 0 0

1 1 1 ······ 1 1

1 1 1 ······ 1 1
1 1 1 ······ 1 0

:
:

1 0 0 ······ 0 0
0 1 1 ······ 1 1

:
:

0 0 0 ······ 0 1
0 0 0 ······ 0 0

0 0 0 ······ 0 0

Step

MINV 1
LINV 1

D7 D0

0
1

1
0

0
0

= 0V, V

= 2V

Timing diagram

Tds

80%

20%

80%

N + 1

20%

N 1

Tdo

Tpw0

Tpw1

N + 1

N + 2

Analog input

CLK

Digital output

CXA1386P/K

Electrical Characteristics Test Circuit

Maximum conversion rate test circuit

Comparator

A > B

Pulse

Counter

CXA1386

P/K

Signal

Source

ECL

Latch

ECL

Latch

1/4

Signal

Source

CLK

1kHz

2Vp-p Sin Wave

CLK

DATA 16

Differential gain error test circuit

Differential phase error test circuit

DUT

CXA1386

P/K

ECL

Latch

10bit

D/A

Vector

Scope

Delay

Amp

NTSC

Signal

Source

SG (CW)

CLK

DG.DP

(CX20202A-1)

Integral linearity error test circuit

Differential linearity error test circuit

DUT

CXA1386

P/K

A < B A > B

Comparator

A1
A0

B1
B0

Buffer

Controller

DVM

"1"

"0"

00000000

11111110

CLK (75MHz)

S1: ON when A < B
S2: ON when A > B

CXA1386P/K

Power Supply Current Test Circuit

Analog input bias current test circuit

CXA1386P

5.2V

8 9 10 11 12 13 14 15 16 17

CXA1386K

38 37 36 35 34 33 32 31 30 29

5.2V

Sampling delay test circuit

Aperture jitter test circuit

Aperture jitter test method

CXA1386

P/K

OSC1

: Variable

OSC2

Logic

Analizer

37.5MHz

Amp

ECL
Buffer

CLK

1024

samples

(LSB)

CLK

129

128
127
126

125

Aperture jitter

Where

(unit: LSB) is the deviation of the output codes when the input

frequency is exactly the same as the clock and is sampled at the

largest slew rate point.

Taj =

/ =

/( ),

256

Aperture jitter is defined as follows:

CXA1386P/K

8bit 75MSPS ADC and DAC Evaluation Board

It is necessary to equip "the CXA1396D/P EVALUATION BOARD WITH DAC" with "A1396D A1386P

ADAPTER" in order to evaluate CXA1386P.

In addition to indispensable features such as the reference voltage generator, this tool equips two sets of

analog inputs (the direct input and the buffer amplifier input), the input voltage offset generator, the clock

decimator, the output data latches, the 10-bit high-speed DAC, and the 20-pin cable connector for digital

outputs. This evaluation board provides full performance of the CXA1386P and it is designed to facilitate

evaluation.

Features

Resolution: 8bits

Maximum conversion rate: 75MSPS

Supply voltage: +5.0V, 5.2V, 2.0V

Two analog inputs (Direct input, buffer amplifier input)

Clock level converter: Sine wave to ECL level signal

Reference voltage adjustment circuit for the A/D converter

Built-in clock frequency decimation circuit: (1/1 to 1/16)

Fig. 1. Block Diagram

BUFFER

DATA

LATCH

LINV MINV

Vin

CLK

CXA1386P

Vin

OFFSET

DECIMATOR

D/A

CONVERTER

VRB

SW3

CLK

SW1

SW2

5.2V (A)

(2k)

AMP.IN

DIR.IN

CLK

240

0.1µ

(1k)

to D

)

DIGITAL OUT

(CONNECTOR)

to D

)

2 (CLK.CLK)

CLK

D/A OUT

1/1 to 1/16

X (2)

5.2V (D)

DGND

2V (D)

5.2V (A)

AGND

+5V

CXA1386P/K

Supply Current

Item

Min.

Typ.

Max.

Unit

5.2V
+5.0V
2.0V

0.85

0.45

1.0

0.6

(Note: Supply current 2.0V is the value when Rn10, Rn11 and Rn12 are not mounted.)

Analog Input (DIR. IN, AMP. IN)

Item

Min.

Typ.

Max.

Unit

Input voltage (DIR. IN)

(AMP. IN)

Input impedance

2.0
0.5

+0.5

V
V

(

: Adjustable by VR1)

Clock Input (CLK)

Item

Min.

Typ.

Max.

Unit

Input voltage
(Peak to Peak)
Input impedance

2.0

Vp-p

Digital Output (D0 to D7)

ECL 10KH level

Clock Output

ECL 10KH level, complementary output

Output Code Table

1 1 1 ······ 1 1
1 1 1 ······ 1 0

:
:

1 0 0 ······ 0 0
0 1 1 ······ 1 1

:
:

0 0 0 ······ 0 1
0 0 0 ······ 0 0

:
:
:
:
:
:
:
:

1 0 0 ······ 0 0
1 0 0 ······ 0 1

:
:

1 1 1 ······ 1 1
0 0 0 ······ 0 0

:
:

0 1 1 ······ 1 0
0 1 1 ······ 1 1

0 1 1 ······ 1 1
0 1 1 ······ 1 0

:
:

0 0 0 ······ 0 0
1 1 1 ······ 1 1

:
:

1 0 0 ······ 0 1
1 0 0 ······ 0 0

0 0 0 ······ 0 0
0 0 0 ······ 0 1

:
:

0 1 1 ······ 1 1
1 0 0 ······ 0 0

:
:

1 1 1 ······ 1 0
1 1 1 ······ 1 1

MINV

LINV

0
1

0
0

1
0

1
1

CXA1386P/K

Fig. 2. Timing Chart

N 1

N 2

N 1

Tdh

1.8ns

(Typ)

Tdh

1.8ns

(Typ)

N 2

N 4

N + 1

A/D input pin

PCB input pin

A/D clock

A/D output

PCB output pin

Vin

(DIR. IN, AMP. IN)

CLK

D7 to D0

(For 1/1 frequency division)

CLKN

CLK

(For 1/1 frequency division)

D7 to D0

DATA OUT

(For 1/2 frequency division)

CLKN

CLK

(For 1/2 frequency division)

Adjustment Methods and Notes on Operation

1) Vin Offset (VR1)

The volume to adjust the signal range (0V center assumed) with the A/D converter input range when a

waveform is input through AMP. IN.

2) A/D Full Scale (VR2)

The volume to adjust A/D converter VRB voltage.

3) Linearity (VR3)

The volume to adjust VRM (linearity) voltage.

4) D/A Full Scale (VR4)

The volume to adjust D/A output full scale (1V)

5) J1 (input selection)

A: Shorts to adjust VRM voltage.

B: Shorts to supply DC voltage to Vin.

C: Shorts to select AMP.IN input.

D: Shorts to select DIR. IN input.

6) SW1

The switch for LINV High/Low

7) SW2

The switch for MINV High/Low

8) SW3 (Decimation)

The switch to select clock frequency decimation.

Switch position: decimation ratio

0: 1/1

1: 1/2

2: 1/4

3: 1/8

4: 1/16

9) SW4 (D/A INV)

The switch for D/A converter output inversion.

10) Rn10, Rn11 and Rn12 are not mounted at shipment. They are not required during evaluation.

11) Waveform probe pins P5 and P8 through P28 are devised to facilitate GND connection in order to reduce

the distortion. As shown in the diagram below, the distance between the probe point and the GND is 300

mils, and there is

1.2mm throughhole at each. The signal and GND locations are suit for a Tektronix GND

tip (part number 013-1185-00).

12) D/A converter (IC13) input data (waveform probe pins P21 through P28) are the complementary signals of

the decimated A/D converter outputs. Those are inverted again in the D/A converter so that the direction of

reproduced waveform can agree with the A/D input signal converter.

13) The part number of the digital output connector is KEL 8830E-020-170S. A corresponding connector and

cable assembly is JUNKOSHA KB0020MCG50BI.

CXA1386P/K

[Jumper Poisition at shipment]

1.2mm

Probe point

GND

300mil

Fig. 3.

CXA1386P/K

Fig. 4. PCB Circuit Schematic

(D)

Rn11

DGND

CLK

DGND

DIGITAL OUT

CONNECTOR

KEL: 8830E-020-170S

(TOP VIEW)

Rn10

Rn11

Rn12

C52

0.1µ

DGND

2V (D)

C53

0.1µ

2V (D)

DGND

2V (D)

DGND

C51

0.1µ

P29

C54

33µ

DGND

2V (D)

P30

DGND

P31

C55

33µ

DGND

5.2V (D)

P32

C56

33µ

AGND

5.2V (A)

P33

AGND

P34

C57

33µ

AGND

+5V (A)

AGND

IC13 : CX20202A-1

MSB

LSB

CLKN

CLK

AGND2

REF

OUT

AGND1

DGND

INV

Rn9

Rn8

C44

0.1µ

DGND

2V (D)

C46

0.1µ

C47

0.1µ

5.2V (D)

DGND

D/A OUT

SW4

D/A INV

R23

3.2k

5.2V (D)

P23

P24

P25

P26

P27

P28

C45

0.1µ

DGND

2V (D)

5.2V (A)

AGND

R22

240

C50

33µ

C49

0.1µ

D/A Full Scale

C48

0.1µ

R21

VR4

IC14

TL431CP

Rn7

C43

0.1µ

DGND

Rn7

P19

P20

CLKN

CLK

AGND

DGND

AGND

Rn9

DGND

SW1

LINV

AGND

FERRITE

BEAD

AGND

1.3k

VR2

0.1µ

AGND

5.2V (A)

IC1-2

TL4558

2SA970

0.1µ

AGND

+5V (A)

A/D Full Scale

240

IC3

TL431CP

510

VR1

AGND

IC1-1

TL4558

AGND

DIR.IN

AMP.IN

AGND

C12

0.1µ

C11

0.1µ

1µ

3.3µ

22k

R5/11k

Vin Offset

240

R12

R11

R10

510

+5V (A)

5.2V (A)

DGND

CLK

IC9 : 10H176

DGND

C24 0.1µ

DGND

5.2V (D)

C26 0.1µ

DGND

5.2V (D)

Dout_

Cout_

Din

COM

Cout

Cin

Dout

Aout_

Bout_

Ain

Aout

Bout

Bin

IC12 : 10H101

Aout_

Bout_

Ain

Aout

Bout

Bin

Dout_

Cout_

Din

COM

Cout

Cin

Dout

IC11 : 10H101

C39 0.1µ

DGND

5.2V (D)

DGND

C41 0.1µ

DGND

5.2V (D)

DGND

Rn4

DGND

C36 0.1µ

2V (D)

Rn4

Rn6

DGND

C42 0.1µ

2V (D)

Rn6

Rn5

DGND

C40 0.1µ

2V (D)

Rn5

Rn3

DGND

C35 0.1µ

2V (D)

Rn3

Rn1

Aout_

Aout

Ain_

Ain

Bout_

Bout

Cout

Cout_

Cin

Cin_

Bin

Bin_

IC2 : 10H116

Cout_

CLK

Cin_

IC5 : 10H136

Enable_

IC7 : 10H164

Aout_

Aout

Ain_

Ain

Bout_

Bout

Cout

Cout_

Cin

Cin_

Bin

Bin_

IC8 : 10H116

0.1µ

C10

0.1µ

C14

0.1µ

C13

0.1µ

Rn1

DGND

5.2V

(D)

DGND

5.2V (D)

DGND

C22

0.1µ

DGND

5.2V (D)

DGND

C21

0.1µ

C37

0.1µ

DGND

C23

0.1µ

R14

2V (D)

DGND

2V (D)

DGND

5.2V (D)

C34

0.1µ

DGND

(D)

C38

0.1µ

Rn2

DGND

2V (D)

DGND

C31

0.1µ

R18

SW3

Decimation

C30

0.1µ

C29

0.1µ

DGND

R20

DGND

C37

0.1µ

CLKN

5.2V (D)

DGND

P11

P12

P18

R19

2V (D)

CLK

DGND

P13

CLK

IC4

CLC404AJP

R15

330

VRB

AGND

VIN

AGND

VRM

AGND

VIN

AGND

VRT

CXA1396D CXA1386P ADAPTER

CLK

CLKN

MINV

DGND1

DGND2

DGND1

LINV

P10

SW2

MINV

C24

0.1µ

C26

1µ

C25

0.1µ

FERRITE BEAD

IC10 : 10H176

C22 0.1µ

DGND

2V (D)

R17

R16

5.2V (D)

P17

P16

P15

P14

CLK

CLKN

C19

0.1µ

C20

AGND

C18

0.1µ

5.2V (A)

AGND

C17

0.1µ

AGND

VIN

5.2V (A)

AGND

C15

1µ

C16

0.1µ

R13

AGND

VRB

VRM

VR3

P21

P22

5.2V (D)

5.2V (A)

C25

0.1µ

C27

0.1µ

DGND

P17

Rn5

Linearity

CXA1386P/K

Characteristics Graphs

Fig 5. CXA1386P SNR vs. Input Frequency

Input Frequency [MHz]

100

SNR [dB]

CLK = 75MHz,
V

= 5.2V

Fig. 6. CXA1386P Effective Bits vs. Input Frequency

Input Frequency [MHz]

100

Effective Bits [bit]

4.0

5.0

6.0

7.0

8.0

CLK = 75MHz,
V

= 5.2V

Fig. 7. CXA1386P 2nd, 3rd Harmonic Distortion vs. Input Frequency

Input Frequency [MHz]

100

2nd, 3rd Harmonic Distortion [dB]

CLK = 75MHz,
V

= 5.2V

2nd Hmnc

3rd Hmnc

CXA1386P/K

CXA1396D CXA1386P ADAPTER (SCALE = 2/1)

55mm

35mm

CXA1386P ADAPTER

TOP VIEW

CXA1386P/K

Parts Layout

CXA1386P/K

1st layer Component plane (Top View)

4th layer Solder plane (Top view)

Printed Pattern

CXA1386P/K

2nd layer GND plane (Top View)

3rd layer Power supply plane (Top View)

CXA1386P/K

Package Outline

Unit: mm

CXA1386P

CXA1386K

SONY CODE

EIAJ CODE

JEDEC CODE

PACKAGE STRUCTURE

PACKAGE MATERIAL

LEAD TREATMENT

LEAD MATERIAL

PACKAGE WEIGHT

EPOXY RESIN

SOLDER PLATING

COPPER

DIP-28P-03

DIP028-P-0600-C

4.2g

28PIN DIP (PLASTIC) 600mil

37.8 0.1

+ 0.4

2.54

0.5 ± 0.1

1.2 ± 0.15

3.0 MIN

0.5 MIN

4.6 0.1

+ 0.4

15.24

13.0 0.1

+ 0.3

0.25 0.05

+ 0.1

0° to 15°

SONY CODE

EIAJ CODE

JEDEC CODE

PACKAGE MATERIAL

LEAD TREATMENT

LEAD MATERIAL

PACKAGE WEIGHT

CERAMIC

GOLD PLATING

PACKAGE STRUCTURE

44PIN LCC (CERAMIC) 1.8g

C1.016

C0.508

R0.2

12.7 ±

0.1

+ 0.35

16.51 0.25

1.27 ±

0.1

1.905 ±

0.25

12.5 ± 0.2

0.3

1.651 ±

0.18

1.951 ±

0.25

1.27

0.635 ±

0.07

PIN NO.1

INDEX

2.159 ± 0.5

LCC-44C-01

QFN044-C-S650-A

1.8g

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: CXA1386K

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: CXA1386K