SMSC DS SLC90E66

Rev. 07/10/2002

SLC90E66

PRELIMINARY

Victory66 Enhanced PCI South Bridge with Ultra

ATA/66 IDE Controller

FEATURES

Enhanced PCI South Bridge for Desktop, Mobile
and Embedded Applications
- Pin Compatible with Intel 82371EB PIIX4E

South Bridge

- High Performance OHCI USB Host Controller
- Ultra ATA/66 IDE Controller
- Enhanced Support for Mobile Applications
- Compatible with Full Line of Intel PCI-based

North Bridge Devices

- Programmable Support for Third Party North

Bridge Solutions

Supported Kits for Pentium

II and Pentium

III

Microprocessors
- VictoryBX-66 Chipset with Intel FW82443BX

(440BX) North Bridge

Integrated Ultra ATA/66 IDE Controller
- Supports "Ultra ATA/66" Synchronous DMA

Modes with Transfer Rate up to
66Mbytes/Second

- Independent Timing for up to Four Drives
- Supports PIO Mode 0 to 4, Multiword DMA

Mode 0, 1 and 2

- Integrated 32x32-bit Buffer For Each Channel
- Supports Glue-Less "Swap-Bay" Option with

Full Electrical Isolation

- Supports Both Legacy and PCI-Native Modes

Enhanced OHCI USB Host Controller
- Two USB 1.0 Ports for Serial Transfers at 12 or

1.5Mbit/Sec

- Supports Legacy Keyboard and Mouse

Software with USB Keyboard and Mouse

- Supports Wakeup From Power-on Suspend

Integrated Multifunction PCI-To-ISA Bridge
- Supports PCI up to 33 MHz
- Supports PCI Rev 2.1 Specification
- Programmable Special Cycle Support for

Compatibility with Non-Intel North Bridges

- Supports Full ISA or Extended I/O (EIO) Bus
- Supports Full Positive Decode or Subtractive

Decode of PCI

- Supports ISA/EIO At ¼ of PCI Frequency

Comprehensive BIOS support

Comprehensive Power Management Capability

for Mobile and Desktop Applications
- 3.3V Operation with 5V Tolerent Buffers
- Low Power for Mobile Applications
- Supports Power-On Suspend and Soft-Off for

Desktop Applications

- Comprehensive Suspend/Resume Logic for

Notebook Applications

- All Registers Readable/Restorable For Proper

Resume From 0V Suspend

- Global and Local Device Management
- Supports Thermal Alarm
- Support For External Microcontroller
- Full Support of Advanced Configuration and

Power Interface (ACPI) Rev. 1.0 Specification
and OS Directed Power Management

- Supports PCI CLKRUN Protocol

Enhanced DMA Controller
- Two 8237 DMA Controllers
- Supports PCI DMA with 3 PC/PCI Channels

and Distributed DMA Protocols

- Supports Type-F DMA with Deep 4-DW Buffer

Interrupt

Controller

- Two 8259 Interrupt Controllers
- Independently Programmable Edge/Level

Sensitivity

- Supports Serial Interrupt
- Supports Optional External I/O APIC

Integrated

8254

Timer

- System Timer, Refresh Request, Speaker

Tone Output

Integrated SMBus Host Controller
- Host Allows CPU to Communicate Via SMBus
- Slave Allows External SMBus Master to

Control Resume Events

Real Time Clock
- 256-Byte Battery Backup CMOS SRAM
- Date Alarm
- Two 8-Byte Lockout Ranges
- Relocatable RTC Index Base Address
- Can Be Disabled for Use With External RTC

324-ball Plastic Ball Grid Array (PBGA) Package

SMSC DS SLC90E66

Page 2

Rev. 07/10/2002

80 Arkay Drive

Hauppauge,

11788

(631)

435-6000

FAX (631) 273-3123

Circuit diagrams and other information relating to SMSC products are included as a means of illustrating typical applications. Consequently, complete
information sufficient for construction purposes is not necessarily given. Although the information has been checked and is believed to be accurate, no
responsibility is assumed for inaccuracies. SMSC reserves the right to make changes to specifications and product descriptions at any time without
notice. Contact your local SMSC sales office to obtain the latest specifications before placing your product order. The provision of this information does
not convey to the purchaser of the described semiconductor devices any licenses under any patent rights or other intellectual property rights of SMSC
or others. All sales are expressly conditional on your agreement to the terms and conditions of the most recently dated version of SMSC's standard
Terms of Sale Agreement dated before the date of your order (the "Terms of Sale Agreement"). The product may contain design defects or errors
known as anomalies which may cause the product's functions to deviate from published specifications. Anomaly sheets are available upon request.
SMSC products are not designed, intended, authorized or warranted for use in any life support or other application where product failure could cause
or contribute to personal injury or severe property damage. Any and all such uses without prior written approval of an Officer of SMSC and further
testing and/or modification will be fully at the risk of the customer. Copies of this document or other SMSC literature, as well as the Terms of Sale
Agreement, may be obtained by visiting SMSC's website at http://www.smsc.com. SMSC is a registered trademark of Standard Microsystems
Corporation ("SMSC"). Product names and company names are the trademarks of their respective holders.

SMSC DISCLAIMS AND EXCLUDES ANY AND ALL WARRANTIES, INCLUDING WITHOUT LIMITATION ANY AND ALL IMPLIED WARRANTIES
OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, TITLE, AND AGAINST INFRINGEMENT AND THE LIKE, AND ANY AND
ALL WARRANTIES ARISING FROM ANY COURSE OF DEALING OR USAGE OF TRADE.

IN NO EVENT SHALL SMSC BE LIABLE FOR ANY DIRECT, INCIDENTAL, INDIRECT, SPECIAL, PUNITIVE, OR CONSEQUENTIAL DAMAGES;
OR FOR LOST DATA, PROFITS, SAVINGS OR REVENUES OF ANY KIND; REGARDLESS OF THE FORM OF ACTION, WHETHER BASED ON
CONTRACT; TORT; NEGLIGENCE OF SMSC OR OTHERS; STRICT LIABILITY; BREACH OF WARRANTY; OR OTHERWISE; WHETHER OR
NOT ANY REMEDY OF BUYER IS HELD TO HAVE FAILED OF ITS ESSENTIAL PURPOSE, AND WHETHER OR NOT SMSC HAS BEEN
ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.

SMSC DS SLC90E66

Page 3

Rev. 07/10/2002

GENERAL DESCRIPTION

The Victory66 SLC90E66 Enhanced PCI South Bridge with Ultra ATA/66MHz IDE Controller is a multi-function PCI
device implementing a PCI-to-ISA bridge function, a PCI Ultra ATA/66 IDE controller function, a Universal Serial Bus
host/hub function, and an Enhanced Power Management function. As a PCI-to-ISA bridge, the SLC90E66 integrates
I/O functions found in a common ISA bridge chip, that includes two DMA controllers, two interrupt controllers, an 8254
timer, and a Real Time Clock. The DMA controllers support Type-F data transfers on each of the eight channels. The
SLC90E66 also supports PC/PCI and Distributed DMA protocols for PCI based DMA applications. The Interrupt
Controllers support Edge or Level sensitive programmable inputs and the use of an external I/O APIC and serial
interrupts. The SLC90E66 can be configured to provide chip select decoding for BIOS, RTC, keyboard controller,
external microcontroller, and two programmable chip selects. The SLC90E66 can be configured as a subtractive
decode bridge or as a positive decode bridge. This allows the use of a subtractive decode PCI-to-PCI bridge such as
that used in a PCI/ISA docking station environment.

The SLC90E66 supports two IDE channels for up to four IDE devices in either PIO or Bus Master mode. The
SLC90E66 also supports "Ultra ATA/66" synchronous DMA compatible devices for data transfer rates up to 66Mbytes
per second. The embedded 32 double word (32x32-bit)deep buffers allow zero wait state PCI burst transfer in either
direction.

The SLC90E66 integrates a USB host controller that is Open Host Controller Interface (OHCI) compatible. Two USB
ports are implemented in the root hub. The USB controller has been enhanced to support wake-up from a power-on
suspend (POS).

The SLC90E66 supports comprehensive power management, including full clock control, device power management
for up to 14 devices, global power management and suspend and resume logic with Power On Suspend, Suspend to
RAM or Suspend to Disk. It fully supports operating system directed power management via the Advanced
Configuration and Power Interface (ACPI) specification. System Management Bus (SMBus) host and slave interface
logic is integrated for communication with other on-board devices.

ORDERING INFORMATION

Order Number:

SLC90E66-UF

324-Ball BGA Package

SMSC DS SLC90E66

Page 5

Rev. 07/10/2002

TABLE OF CONTENTS

1.0 FUNCTIONAL OVERVIEW..............................................................................................................................13

2.0 SIGNAL

DESCRIPTION ..................................................................................................................................16

2.1 S

IGNALS

........................................................................................................................................................17

2.1.1 PCI

Bus

Interface .................................................................................................................................17

2.1.2 ISA/EIO

Interface Signals.....................................................................................................................19

2.1.3

Xbus Interface Signals ........................................................................................................................22

2.1.4 DMA

Signals ........................................................................................................................................23

2.1.5 Interrupt

Controller and APIC Signals ..................................................................................................24

2.1.6 CPU

Interface Signals ..........................................................................................................................25

2.1.7

Clocks ..................................................................................................................................................27

2.1.8 IDE

Signals ..........................................................................................................................................28

2.1.9 Universal

Serial Bus Signals ................................................................................................................32

2.1.10 Power

Management Signals ................................................................................................................32

2.1.11

General Purpose Input and Output Signals..........................................................................................35

2.1.12 Other

System and Test Signals............................................................................................................37

2.1.13 Power

and Ground Pins .......................................................................................................................37

2.2 P

OWER

LANES

..............................................................................................................................................38

2.2.1 Power

Sequencing Requirements ........................................................................................................38

3.0 REGISTER

SUMMARY ...................................................................................................................................39

3.1 PCI/ISA

RIDGE

EGISTER

APPING

...............................................................................................................39

3.1.1 PCI

Configuration

Registers (Function 0).............................................................................................39

3.1.2

IO Space Registers (Function 0) ..........................................................................................................40

3.2 IDE

ONTROLLER

EGISTER

APPING

ABLE

UNCTION

1) ..............................................................................43

3.2.1 PCI

Configuration

Registers (Function 1).............................................................................................43

3.2.2 IO

Space

Registers ..............................................................................................................................44

3.3 U

NIVERSAL

ERIAL

(USB)

ONTROLLER

EGISTER

APPING

ABLE

UNCTION

2) .......................................44

3.3.1 PCI

Configuration

Registers (Function 2).............................................................................................44

3.3.2

SB OpenHCI Memory Mapped Registers (Function 2).........................................................................45

3.4 P

OWER

ANAGEMENT

EGISTER

APPING

ABLE

UNCTION

3) ........................................................................45

3.4.1 PCI

Configuration

Registers (Function 3).............................................................................................45

3.4.2

Power Management IO Space Registers (Function 3) .........................................................................46

3.4.3

SMBus Controller IO Space Registers (Function 3) .............................................................................47

4.0

PCI/ISA BRIDGE PCI REGISTER DESCRIPTION (FUNCTION 0).................................................................48

4.1 PCI/ISA

RIDGE

PCI

ONFIGURATION

PACE

EGISTERS

(PCI

UNCTION

0) .....................................................48

4.1.1

VID - Vendor Identification Register (Function 0) .................................................................................48

4.1.2

DID - Device Identification Register (Function 0)..................................................................................48

4.1.3

PCICMD - PCI Command Register (Function 0) ..................................................................................48

4.1.4

PCISTS - PCI Device Status Register (Function 0)..............................................................................49

4.1.5

RID - Revision ID Register (Function 0) ...............................................................................................49

4.1.6

CLASSCODE - Class Code Register (Function 0) ...............................................................................50

4.1.7

HEDT - Header Type Register (Function 0) .........................................................................................50

4.1.8

IORT - ISA I/O Recovery Timer Register (Function 0) .........................................................................50

4.1.9

XBCS - X-Bus Chip Select Register (Function 0) .................................................................................51

4.1.10

nPIRQRC[A:D] - nPIRQx Route Control Registers (Function 0) ..........................................................53

4.1.11

SERIRQC - Serial IRQ Control Register (Function 0) ..........................................................................54

4.1.12

FDMA - Type-F DMA Control Register (Function 0).............................................................................54

4.1.13

IRQ8SR - IRQ8 Source Register (Function 0)......................................................................................55

4.1.14

TOM - Top of Memory Register (Function 0)........................................................................................55

4.1.15

MBDMA [1:0] - Motherboard Device DMA Control Registers (Function 0) ...........................................56

4.1.16

APICBASE - APIC Base Address Relocation Register (Function 0) ....................................................56

4.1.17

DLC - Deterministic Latency Control Register (Function 0)..................................................................57

4.1.18

PDMACFG - PCI DMA Configuration Register (Function 0).................................................................57

4.1.19

DDMABP - Distributed DMA Slave Base Pointer Registers (Function 0) .............................................59

4.1.20

GENCFG - General Configuration Register (Function 0) .....................................................................59

4.1.21

RTCCFG - Real Time Clock Configuration Register (Function 0) ........................................................62

4.1.22

RTCPBAL - RTC Index Primary Base Address Low Byte (Function 0) ................................................63

4.1.23

RTCPBAH - RTC Index Primary Base Address High Byte (Function 0)...............................................63

4.1.24

SBMISCL - South Bridge Miscellaneous Low Register (Function 0) ....................................................64

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