SMSC DS LAN83C183
Rev. 12/14/2000
LAN83C183
PRELIMINARY
10/100 Mbps TX/FX/10BT
Fast Ethernet Physical Layer Device (PHY)
Features
Single-Chip 100BASE-TX/FX/10BASE-T Fast
Ethernet Physical Layer Solution
Dual-Speed - 10/100 Mbits/sec
Half-Duplex And Full-Duplex Support
MII Interface to Ethernet Controller
MI Interface for Configuration and Status
Optional Repeater Interface
AutoNegotiation: 10/100, Full/Half-Duplex
Meets All Applicable IEEE 802.3 Standards
On-Chip Wave Shaping - No External Filters
Required
Adaptive Equalizer
Baseline Wander Correction
Interface to External 100BASE-T4 PHY
LED Outputs
Link
Activity
Collision
Full Duplex
10/100
User-Programmable
Many User Features and Options
Few External Components
3.3V Supply with 5V-Tolerant I/O
64-Pin TQFP Package (1.4-mm Body
Thickness)
GENERAL DESCRIPTION
The SMSC LAN83C183 is a highly integrated analog interface IC for twisted pair Ethernet applications.
The LAN83C183 can be configured for either 100-Mbps (100BASE-TX or 100 BASE-FX) or 10-Mbps
(10BASE-T) Ethernet operation. The 100BASE-FX is packaged in a 64-Pin TQFP pack-age.
The LAN83C183 consists of a 4B5B/Manchester encoder/decoder, scrambler/descrambler, transmitter
with wave shaping and output driver, twisted pair receiver with on-chip equalizer and baseline wander
correction, clock and data recovery, AutoNegotiation, controller interface (MII), and serial port (MI).
The addition of internal output waveshaping circuitry and on-chip filters eliminates the need for external
filters normally required in 100BASE-TX and 10BASE-T applications.
The LAN83C183 can automatically configure itself for 100- or 10-Mbps and full- or half-duplex operation
with the on-chip AutoNegotiation algorithm.
The eleven 16-bit registers of the LAN83C183 can be accessed through the Management Interface (MI)
serial port. These registers contain configuration inputs, status outputs, and device capabilities.
The LAN83C183 is ideal as a media interface for 100BASE-TX/10BASE-T adapter cards, PC Cards,
motherboards, mobile applications, repeaters, switching hubs, and external PHYs.
The LAN83C183 operates from a single 3.3V supply. All inputs and outputs are 5V-tolerant and can
directly interface to other 5V devices.
SMSC DS LAN83C183
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Rev. 12/14/2000
ORDERING INFORMATION
Order Number:
LAN83C183-JD
64-Pin TQFP Package
80 Arkay Drive
Hauppauge,
NY
11788
(631)
435-6000
FAX (631) 273-3123
Copyright SMSC 2004. All rights reserved.
Circuit diagrams and other information relating to SMSC products are included as a means of illustrating typical applications. Consequently, complete
information sufficient for construction purposes is not necessarily given. Although the information has been checked and is believed to be accurate, no
responsibility is assumed for inaccuracies. SMSC reserves the right to make changes to specifications and product descriptions at any time without
notice. Contact your local SMSC sales office to obtain the latest specifications before placing your product order. The provision of this information does
not convey to the purchaser of the described semiconductor devices any licenses under any patent rights or other intellectual property rights of SMSC
or others. All sales are expressly conditional on your agreement to the terms and conditions of the most recently dated version of SMSC's standard
Terms of Sale Agreement dated before the date of your order (the "Terms of Sale Agreement"). The product may contain design defects or errors
known as anomalies which may cause the product's functions to deviate from published specifications. Anomaly sheets are available upon request.
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or contribute to personal injury or severe property damage. Any and all such uses without prior written approval of an Officer of SMSC and further
testing and/or modification will be fully at the risk of the customer. Copies of this document or other SMSC literature, as well as the Terms of Sale
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ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
SMSC DS LAN83C183
3
Rev. 12/14/2000
Contents
Chapter 1
LAN83C183 Functional Description
1.1
OVERVIEW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
1.1.1
Channel Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
1.1.2
Data Paths . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
1.2
BLOCK DIAGRAM DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
1.2.1
Oscillator and Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
1.2.2
Controller Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
1.2.3
Encoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
1.2.4
Decoder. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
1.2.5
Scrambler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
1.2.6
Descrambler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
1.2.7
Twisted-Pair Transmitters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
1.2.8
Twisted-Pair Receivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
1.2.9
FX Transmitter and Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
1.2.10
Clock and Data Recovery. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
1.2.11
Link Integrity and AutoNegotiation . . . . . . . . . . . . . . . . . . . . . . . . . 31
1.2.12
Link Indication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
1.2.13
Collision. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
1.2.14
LED Drivers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
1.3
START OF PACKET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
1.3.1
100 Mbits/s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
1.3.2
10 Mbits/s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
1.4
END OF PACKET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
1.4.1
100 Mbits/s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
1.4.2
10 Mbits/s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
1.5
FULL/HALF DUPLEX MODE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
1.5.1
Forcing Full/Half Duplex Operation . . . . . . . . . . . . . . . . . . . . . . . . 41
1.5.2
Full/Half Duplex Indication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
1.5.3
Loopback. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
1.6
REPEATER MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
1.7
10/100 MBITS/S SELECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
1.7.1
Forcing 10/100 Mbits/s Operation . . . . . . . . . . . . . . . . . . . . . . . . . 42
1.7.2
Autoselecting 10/100 Mbits/s Operation. . . . . . . . . . . . . . . . . . . . . 42
1.7.3
10/100 Mbits/s Indication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
1.8
JABBER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
SMSC DS LAN83C183
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1.9
AUTOMATIC JAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
1.9.1
100 Mbits/s JAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
1.9.2
10 Mbits/s JAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
1.10
RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
1.11
POWERDOWN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
1.12
RECEIVE POLARITY CORRECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Chapter 2
Signal Descriptions
2.1
MEDIA INTERFACE SIGNALS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
2.2
CONTROLLER INTERFACE SIGNALS (MII) . . . . . . . . . . . . . . . . . . . . . . . . 47
2.3
MANAGEMENT INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
2.4
MISCELLANEOUS SIGNALS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
2.5
LEDS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
2.6
POWER SUPPLY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Chapter 3
Registers
3.1
BIT TYPES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
3.2
MI SERIAL PORT REGISTER SUMMARY. . . . . . . . . . . . . . . . . . . . . . . . . . 55
3.3
REGISTERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
3.3.1
Control Register (Register 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
3.3.2
Status Register (Register 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
3.3.3
PHY ID 1 Register (Register 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
3.3.4
PHY ID 2 Register (Register 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
3.3.5
AutoNegotiation Advertisement Register (Register 4) . . . . . . . . . . 61
3.3.6
AutoNegotiation Remote End Capability Register (Register 5) . . . 63
3.3.7
Configuration 1 Register (Register 16). . . . . . . . . . . . . . . . . . . . . . 64
3.3.8
Configuration 2 Register (Register 17). . . . . . . . . . . . . . . . . . . . . . 66
3.3.9
Status Output Register (Register 18) . . . . . . . . . . . . . . . . . . . . . . . 68
3.3.10
Interrupt Mask Register (Register 19) . . . . . . . . . . . . . . . . . . . . . . 69
3.3.11
Reserved Register (Register 20) . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Chapter 4
Management Interface
4.1
SIGNAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
4.2
GENERAL OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
4.3
MULTIPLE REGISTER ACCESS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
4.4
FRAME STRUCTURE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
4.5
REGISTER STRUCTURE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
4.6
INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Chapter 5
Specifications
5.1
ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
5.2
ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
5.2.1
Twisted-Pair DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
5.2.2
FX Characteristics, Transmit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
5.3
AC ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
5.3.1
25 MHz Input/Output Clock Timing Characteristics . . . . . . . . . . . . 90
SMSC DS LAN83C183
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Rev. 12/14/2000
5.3.2
Transmit Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
5.3.3
Receive Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
5.3.4
Collision and JAM Timing Characteristics . . . . . . . . . . . . . . . . . . . 97
5.3.5
Link Pulse Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 100
5.3.6
Jabber Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
5.4
LED DRIVER TIMING CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . 104
5.4.1
MI Serial Port Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . 105
5.5
PINOUTS AND PACKAGE DRAWINGS. . . . . . . . . . . . . . . . . . . . . . . . . . . 107
5.5.1
Pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
5.5.2
LAN83C183 Pin Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
5.6
MECHANICAL DRAWING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
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