The information provided herein is believed to be reliable at press time. Sirenza Microdevices assumes no responsibility for inaccuracies or ommisions. Sirenza Microdevices assumes no responsibility for the use of this information, and all such
information shall be entirely at the user's own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. Sirenza Microdevices
does not authorize or warrant any Sirenza Microdevices product for use in life-support devices and/or systems. Copyright 2005 Sirenza Microdevices, Inc. All worldwide rights reserved.
303 S. Technology Court,
Phone: (800) SMI-MMIC
http://www.sirenza.com
Broomfield, CO 80021
1 EDS-104668 Rev C
Preliminary
Sirenza Microdevices' SLD-3091FZ is a robust 30 Watt high performance
LDMOS transistor designed for operation from 10 to 2200MHz. It is an
excellent solution for applications requiring high linearity and efficiency at a
low cost. The SLD-3091FZ is typically used in power amplifiers, repeaters,
and radio amplifier applications. The power transistor is fabricated using
Sirenza's high performance XeMOS II
TM
process.
Key RF Specifications
Symbol
Parameter
Units
Min.
Typ.
Max.
Frequency
Frequency of Operation
MHz
10
-
2200
Gain
30 Watt CW, 915 MHz
dB
19
Efficiency
Drain Efficiency at 30 Watt CW, 915 MHz
%
45
IRL
Input Return Loss, 30 Watt Output Power, 915 MHz
dB
-15
Linearity
3
rd
Order IMD at 30 Watt PEP (Two Tone), 915 MHz
dBc
-28
1dB Compression (P
1dB
), 915 MHz
Watt
35
R
TH
Thermal Resistance (Junction-to-Case)
C/W
2.4
SLD-3091FZ
30 Watt Discrete LDMOS FET in Ceramic
Flanged Package
Product Features
Applications
30 Watt Output P
1dB
Single Polarity Supply Voltage
High Gain: 18 dB at 915 MHz
High Efficiency: 45% at 30W CW
XeMOS II LDMOS
Integrated ESD Protection, 1B
Base Station PA driver
Repeaters
Radio Amplifier
Military Communication
GSM, CDMA, RFID, Point-to-Point
Product Description
Pb
RoHS Compliant
&
Package
Green
Functional Schematic Diagram
Key DC Parameters
Symbol
Parameter
Unit
Min
Typ.
Max
g
m
Forward Transconductance @ 425mA I
DS
mA / V
1650
V
GS
Threshold
I
DS
=3mA
Volt
3.3
V
DS
Breakdown
1mA I
DS
current
Volt
65
C
iss
Input Capacitance (Gate to Source) V
GS
=0V, V
DS
=28V
pF
66
C
rss
Reverse Capacitance (Gate to Drain) V
GS
=0V, V
DS
=28V
pF
1.4
C
oss
Output Capacitance (Drain to Source) V
GS
=0V, V
DS
=28V
pF
30
R
DSon
Drain to Source Resistance, V
GS
=10V, V
DS
=250mV
0.2
Test Conditions V
DS
= 28.0V, I
DQ
= 300mA, T
Flange
= 25C
T
Case Flange = Ground
ESD
Protection
303 S. Technology Court
Phone: (800) SMI-MMIC
http://www.sirenza.com
Broomfield, CO 80021
2
EDS-104668 Rev C
Preliminary
SLD-3091FZ 30 Watt LDMOS FET
Caution: ESD Sensitive
Appropriate precaution in handling, packaging
and testing devices must be observed.
Note 1:
Gate voltage must be applied to the device concurrently or after
application of drain voltage to prevent potentially destructive
oscillations. Bias voltages should never be applied to the tran-
sistor unless it is properly terminated on both input and output.
Note 2:
The required V
GS
corresponding to a specific I
DQ
will vary from
device to device due to the normal die-to-die variation in thresh-
old voltage with LDMOS transistors.
Note 3:
The threshold voltage (V
GSTH
) of LDMOS transistors varies with
device temperature. External temperature compensation may
be required. See Sirenza application notes AN-067 LDMOS
Bias Temperature Compensation.
Absolute Maximum Ratings
Parameters
Value
Unit
Drain Voltage (V
DS
)
35
V
Gate Voltage (V
GS
)
20
V
RF Input Power
+36
dBm
Load Impedance for Continuous Operation Without
Damage
10:1
VSWR
Output Device Channel Temperature
+200
C
Lead Temperature During Solder Reflow
+270
C
Operating Temperature Range
-20 to +90
C
Storage Temperature Range
-40 to +100
C
Operation of this device beyond any one of these limits may cause perma-
nent damage. For reliable continuous operation see typical setup values
specified in the table on page one.
Quality Specifications
Parameter
Description
Rating
ESD Rating
Human Body Model
1B
Case Flange = Ground
ESD
Protection
Pin Diagram
Pin 1
Pin 2
Pin Description
Pin #
Function
Description
1
Gate
Transistor RF input and gate bias voltage. The gate bias voltage must be temperature compensated to maintain constant
bias current over the operating temperature range. Care must be taken to protect against video transients that exceed the
recommended maximum input power or voltage.
2
Drain
Transistor RF output and drain bias voltage. Typical voltage is 28V.
Flange
Source, Gnd
Exposed area on the bottom side of the package needs to be mechanically attached to the ground plane of the board for
optimum thermal and RF performance. See mounting instructions for recommendation.
303 S. Technology Court
Phone: (800) SMI-MMIC
http://www.sirenza.com
Broomfield, CO 80021
3
EDS-104668 Rev C
Preliminary
SLD-3091FZ 30 Watt LDMOS FET
Typical Performance Curves in 900 MHz Application Circuit
2 Tone Gain, Efficiency, Linearity and IRL vs Frequency
Vdd=28V, Idq=0.3A, Pout=30W PEP, Delta F=1 MHz
0
10
20
30
40
50
60
885
895
905
915
925
935
945
Frequency (MHz)
G
a
i
n
(
d
B
)
,
E
f
f
i
ci
e
n
cy (
%
)
-60
-50
-40
-30
-20
-10
0
IMD
(
d
B
c
)
, IR
L
(
d
B
)
Gain
Efficiency
IM3
IM5
IM7
IRL
2 Tone Gain, Efficiency, Linearity vs Pout
Vdd=28V, Idq=0.3A, Freq=912 MHz, Delta F=1 MHz
0
5
10
15
20
25
30
35
40
45
0
5
10
15
20
25
30
Pout (W PEP)
G
a
i
n
(
d
B
)
,
E
f
f
i
ci
e
n
cy
(
%
)
-70
-65
-60
-55
-50
-45
-40
-35
-30
-25
IM
D
(
d
B
c
)
Gain
Efficiency
IM3
IM5
IM7
CW Gain, Efficiency, IRL vs Frequency Vdd=28V, Idq=0.3A,
Pout=30W
0
10
20
30
40
50
60
885
895
905
915
925
935
945
Frequency (MHz)
G
a
i
n
(
d
B
)
,
E
f
f
i
ci
e
n
cy (
%
)
-30
-25
-20
-15
-10
-5
0
I
nput
R
e
t
u
r
n
Los
s
(
d
B
)
Gain
Efficiency
IRL
CW Gain, Efficiency vs Pout
Vdd=28V, Idq=0.3A, Freq=912 MHz
10
11
12
13
14
15
16
17
18
19
20
21
22
0
10
20
30
40
50
Pout (W)
Ga
i
n
(
d
B
)
0
5
10
15
20
25
30
35
40
45
50
55
60
E
ffi
ci
e
n
c
y (
%
)
Gain
Efficiency
303 S. Technology Court
Phone: (800) SMI-MMIC
http://www.sirenza.com
Broomfield, CO 80021
4
EDS-104668 Rev C
Preliminary
SLD-3091FZ 30 Watt LDMOS FET
Typical Performance Curves in 900 MHz Application Circuit over Temperature
IMD3 vs Pout over Temperature
Vdd=28V, Idq=300mA, Freq=912 MHz
-70
-65
-60
-55
-50
-45
-40
-35
-30
-25
-20
0
5
10
15
20
Pout (W avg)
IM
D
3
(d
B
c
)
t-=-25
t=25
t=-85
2 tone Efficiency vs Pout over Temperature
Vdd=28V, Idq=300mA, Freq=912 MHz
0
5
10
15
20
25
30
35
40
0
5
10
15
20
Pout (W avg)
E
f
f
i
ci
e
n
cy (
%
)
t-=-25
t=25
t=-85
Efficiency vs Pout over Temperature
Vdd=28V, Idq=300mA, Freq=912 MHz
0
10
20
30
40
50
0
10
20
30
40
Pout (W)
E
f
f
i
ci
ency (
%
)
t-=85
t=25
t=-25
CW Gain vs Pout over Temperature
Vdd=28V, Idq=300mA, Freq=920 MHz
13
14
15
16
17
18
19
20
21
22
0
10
20
30
40
Pout (W)
Ga
i
n
(
d
B
)
t-=85
t=25
t=-25
303 S. Technology Court
Phone: (800) SMI-MMIC
http://www.sirenza.com
Broomfield, CO 80021
5
EDS-104668 Rev C
Preliminary
SLD-3091FZ 30 Watt LDMOS FET
Impedance Data
Frequency (MHz)
Z
source
Z
load
850
0.9 - j 0.7
2.6 - j 0.5
895
0.8 - j 0.7
2.4 - j 0.4
960
0.7 - j 0.9
2.3 - j 0.1
Z
source
and Z
load
are the optimal impedances presented to the SLD-3091FZ
when operating at 28V, Idq=300mA, Pout=30 W PEP
Impedances Referenced to Wirebond/PCB Interface.
Zload
source
Z
Input
Matching
Network
Output
Matching
Network
Device
under test
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