Seiko Instruments Inc.
1
S70L41B is a fully integrated CMOS POCSAG (CCIR Radio Paging
code No.1) decoder and page controller for display pagers.The decoded
POCSAG data are transferred over a serial interface to a microcontroller
according to its commands for processing and subsequent storage and
display.
Its on chip buffer register allows the microcontroller to stay in subclock
(lower frequency) mode in receiving interrupt requests from S70L41B.
S70L41B also has an improved synchronization algorithm for efficient
power saving.
In addition to its conventional decoding and error correcting function, it
has a data conversion function for Chinese characters.
With 76.8kHz X'tal oscillator, the decoder can be applied to any one of
512,1200 and 2400 bps system by using its internal registers.
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Specifications
Characteristic
Value
Condition
Operating Voltage
Range
V
DD1
=0.9
2.2 V
V
DD2
=V
DD1
3.6 V
Average Current
Consumption with no page
6
Atyp.
15
Atyp.
V
DD1
=1.5 V
V
DD1
=2.0 V
Average Current
Consumption at Stop Mode
5
Atyp.
V
DD1
=1.5 V
Operating Temp. Range
-10
C
+50
C
PAGING DECODER
S-70L41B
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Features
Low voltage operation
0.9Vmin
Low current consumption
50
A max.
@
1.5V
8bit serial interface for a CPU with on-chip level shifters
Data conversion function (data lenghth of 4, 7 or 8 bits)
512/1200/2400bps register selectable
6 addresses and two frames (programmable
address assignment)
Programmable receiver warm-up's
Multistage warm-up's(BS1,2,3)
Stop (power-down) mode provided for clock
function only
Up to 2 bit random error correction
On-chip command decoder for CPU control
On-chip oscillator circuitry for 76.8kHz X'tal
20 pin TSSOP
Table 1
(Ta=25
C, 76.8 kHz X'tal used unless otherwise noted)
Rev.1.1
PAGING DECODER
S-70L41B
4
Seiko Instruments Inc.
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Pin Assignment
Pin No
Pin Name
Functions
L.S.
1
V
DD1
Positive power supply
2
SIGIN
Received data input
(Inverse or Noninverse register selectable)
No
3
BS3
Batterysaving signal output (for PLL)
No
4
BS2
Same as above (for quick charge)
No
5
BS1
Same as above (for RF and IF)
No
6
ACCL
Test clock input for acceleration
No
7
TEST
Test input (with pull-up). Sets BS1,2,3 "H" when "L" is input during resetting.
Enables test registers to be written by a uP.
No
8
X
IN
Oscillator circuit gate input
No
9
X
OUT
Oscillator circuit drain output
No
10
V
SS
Connects to gnd.
11
RESET
Hardware reset input (with pull-up)
No
12
CS
Chip select input for interfacing with a uP.
"L" input to this pin enables CPUDO terminal to indicate the status of the decoder.
Yes
13
CPUCK
Serial clock input from a uP.
Yes
14
CPUDI
Serial data input from a uP.
Yes
15
V
DD2
Positive power supply for the level shifters
16
ORNG
Receiver out of range indication output. Goes "L" when a certain amount of time
has passed after the SC code loss.
The time after missing SC code selectable by internal registers "OR0" and "OR1".
Yes
17
COUT
Oscillator clock output
Outputs osc. frequency (76.8kHz) or pseudo 32.768kHz with a duty ratio of 1/3 to
2/3. The frequency selected by the register "CSEL".
Pulled down to "L" when clock output is disabledby the "CDIS" register.
Yes
18
BUSY
Decoder busy indication output. While "L", no commands accepted, no data ready
to be output.
Yes
19
CPURQ
Interrupt request signal output to a uP.
Goes "L" on a page reception .
Yes
20
CPUDO
Serial data output to a uP.
Yes
Table 3
L.S. : Level Shifter
PAGING DECODER
S-70L41B
Seiko Instruments Inc.
5
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Pin Structural Configuration
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Input/Ouput Circuits
Pin #
Pin Name
I/O
Structure
PU/PD
Reset
Remarks
Circuit
1
V
DD1
2
SIGIN
CMOS
I1
3
BS3
O
CMOS
L
"H" @TEST="L"
O1
4
BS2
O
CMOS
L
Same as above
O1
5
BS1
O
CMOS
L
Same as above
O1
6
ACCL
I
CMOS
I1
7
TEST
I
CMOS
PU
Schmitt trigger
I3
8
XIN
I
9
XOUT
O
10
V
SS
11
RESET
CMOS
PU
Schmitt trigger
I3
12
CS
I
CMOS with L.S.
I1
13
CPUCK
I
CMOS with L.S.
I2
14
CPUDI
I
CMOS with L.S.
I1
15
V
DD2
16
ORNG
O
CMOS with L.S.
L
O2
17
COUT
O
CMOS with L.S.
L
O2
18
BUSY
O
CMOS with L.S.
H
O2
19
CPURQ
O
CMOS with L.S.
H
O2
20
CPUDO
O
CMOS with L.S.
OFF
O3
Table 4
(Notes)
PU : Pull-Up Resistor, PD : Pull-Down Resistor, L.S.: Level Shifter
V
SS
V
DD1
or V
DD2
I1
V
SS
I2
V
DD1
V
SS
V
DD2
O2
Level
Shifter
V
SS
V
DD2
Level
Shifter
Figure 1
Enable
Enable
I3
Level
Shifter
V
SS
V
DD1
or V
DD2
V
DD1
O1
O3
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