Seiko Instruments Inc.
1
64-bit THERMAL HEAD DRIVER
S-4621A
The S-4621A is a CMOS thermal print head driver containing a 64-bit shift
register and a latch. It can be used for general purpose because "H" or
"L" can be selected for the latch and the driver enable. It is ideal for the
bar-code printer and the thermal print head of high-speed printing
because of its large driver output current of 50 mA.
n
Features
Low current consumption : 0.4 mA typ.
Driver output current : 50 mA max.
(f
CLK
=5 MHz, SI: fixed)
64-bit shift register and latch are built in
High speed operation :
7 MHz (chip)
Driver enable
5 MHz (cascade connection)
Driver-off function when supply voltage falls
Driver output voltage :
36 V max.
Selectable H/L for latch and driver enable
n
Block Diagram
Figure 1
AEN
BEN
V
DD
LATCH
CONT
V
SS0
LA
LA
LA
D-FF
D-FF
LA
LA
SI
CLK
SO
V
SS0
V
DD
DO
1
DO
2
DO
3
DO
63
DO
64
V
SS1
D-FF
D-FF
D-FF
V
SS0
OLD
HIST
64-bit THERMAL HEAD DRIVER
S-4621A
2
Seiko Instruments Inc.
n
Operation
(1) Fundamental Operation
The 64-bit shift register reads the data input to SI at the rising edge of the CLOCK input. Please use HIST in low or
OPEN. The latch circuit operates depending on the levels of CONT and LATCH; it reads the data of the shift register
when teir levels are the same, and it holds the data of the shift register when they differ. The latch data is output to the
respective drivers when AEN is low and BEN is high. The driver output transistor turns ON when the latch data is high
turns OFF when low. Turning AEN high or BEN low makes all driver output transistor go off.
All driver output transistor go off when power supply voltage becomes lower than
V
DET
regardless of all input signals.
(2) Operation of Generating Historical Data
When HIST is high,OLD turns active. The data input to SI and the data input to OLD at the rising edge of the CLOCK
input are read at the shift resister as historical data by using logical circuit.
This is proceeded by AND of logical invert data of input data from OLD and input data from SI.
For example, when the last printed-data input to OLD and the up-data printed-data input to SI, historical data in the
figure2 in the below is read to the shift resister.
Table 1
Pattern 1
Pattern 2
Pattern 3
Pattern 4
the last printed-data(OLD)
l
l
the up-data printed-data(SI)
l
l
the historical data to the shift
resister
l
l
is HIGH
is LOW
this application example is advantage for the preliminary powering-on electricity data of heating elements since when
the last printed-data is
and the up-data printer-data is
l
, the historical data will be
l
.
64-bit THERMAL HEAD DRIVER
S-4621A
Seiko Instruments Inc.
3
n
Terminal Functions
(Refer to the dimensions for the pad arrangement)
Table 2
No.
Name
Functions
1 to 64
DO
1
to DO
64
( DO
n
)
Driver output terminals (Nch open-drain)
65, 66, 73, 74,
82, 83
V
SS1
GND for driver (0 V)
71, 80
V
DD
Positive power supply for logic (+5 V)
67, 75
V
SS0
GND for logic (0 V)
77
CLK
Clock input terminal for 64-bit shift register
81
SI
Serial data input terminal for 64-bit shift register
68
SO
Serial data output terminal for 64-bit shift register
69
LATCH
Data latch signal input terminal
When CONT="L" or open
LATCH="L": Reads the data of the shift register
LATCH="H": Holds the preceding data
When CONT="H"
LATCH="L": Holds the preceding data
LATCH="H": Reads the data of the shift register
72
CONT
Data latch signal control terminal : Selects "H" or "L" for LATCH (pull-
down resistor is built in)
76
AEN
Driver enable terminal : Outputs the latch data to the driver when low
(pull-up resistor is built in)
70
BEN
Driver enable terminal : Outputs the latch data to the driver when high
(pull-down resistor is built in)
79
OLD
Former column serial data input terminal (A pull-down resistor is built in)
78
HIST
Former column serial data input control terminal (A pull-down resistor is
built in)
HIST="H" : OLD terminal is active.
HIST="L" or open : Input from OLD terminal is not allowed.
64-bit THERMAL HEAD DRIVER
S-4621A
4
Seiko Instruments Inc.
n
Absolute Maximum Ratings
Table 3
n
DC Electrical Characteristics
Table 4
(Unless otherwise specified: V
DD
=5.0 V
10%, Ta=-10
C to 80
C)
1
CLK : f
CLK
=fmax duty 50%
T
SUD
=THD=100 nsec
SI, OLD, HIST : 1/2 fmax
LATCH : T
WLA
=100 nsec
Others : DC level
Parameter
Symbol
Ratings
Unit
Supply voltage
V
SS0,1
- V
DD
-0.4 to +7.0
V
Driver output voltage
V
DOH
36
V
Driver output current
I
DOL
50
mA
Input voltage
V
IN
V
SS0
-0.5 to V
DD
+0.5
V
Output voltage
V
OUT
V
SS0
-0.5 to V
DD
+0.5
V
Max. junction temperature
T
jMAX
125
C
Operating temperature range
T
opr
-10 to +80
C
Storage temperature range
T
stg
-40 to +125
C
Parameter
Sybl
Conditions
Min.
Typ.
Max.
Unit
Supply voltage
V
DD
4.5
5.0
5.5
V
High level input voltage
V
IH
1
0.7
V
DD
V
DD
V
Low level input voltage
V
IL
V
SS
0.3
V
DD
V
High level input current
I
IH
BEN,
CONT,OLD,HIST
55
A
0.5
A
Low level input current
I
IL
AEN
-55
A
-0.5
A
High level output voltage
V
OH
SO terminal, no load
4.45
V
Low level output voltage
V
OL
SO terminal, no load
0.05
V
High level output current
I
OH
SO terminal, V
OH
=V
DD
-0.4 V
-0.5
mA
Low level output current
I
OL
SO terminal, V
OL
=0.4 V
0.5
mA
High level driver output
voltage
V
DOH
Heat generator resistance:
500
min.
24
28
V
Low level driver output
voltage
V
DOL
I
DOL
=30 mA
0.7
1.5
V
Driver leakage current
I
LEAK
V
DOH
=28 V
Per 1-bit of driver output
1.0
A
V
DOH
=28 V
Per 64-bit of driver output
10
A
f
CLK
=2 MHz,SI : fixed
0.2
0.6
mA
Current consumption
I
DD
f
CLK
=5 MHz,SI : fixed
0.4
1.2
mA
f
CLK
=5 MHz, SI=1/2f
CLK
1.6
5.0
mA
Lower V
DD
detection voltage
V
DET
0.8
4.0
V
VDD=5.0 V
VIH=5.0 V
Ta=25
C
VDD=5.0 V
VIL=0 V
Ta=25
C
Ta=
25
C
64-bit THERMAL HEAD DRIVER
S-4621A
Seiko Instruments Inc.
5
n
AC Electrical Characteristics
Table 5
(
Unless otherwise specified:
V
DD
=5.0 V
10%, Ta=-10
C to 80
C)
Parameter
Symbol
Conditions
Min.
Typ.
Max.
Unit
CLK pulse width
t
WCLK
70
ns
Data setup time
t
SUD
V
IH
=V
DD
, V
IL
=V
SS0
40
ns
Data hold time
t
HD
V
IH
=V
DD
, V
IL
=V
SS0
40
ns
Latch pulse width
t
WLA
100
ns
Latch setup time
t
SULA
100
ns
CLK-SO propagation delay time
t
dSO
C
L
=3 pF
120
ns
EN-DOn propagation delay time
t
dDO
R
L
=1.0 k
, V
DOH
=24 V
10.5
s
DOn rise time
t
rDO
R
L
=1.0 k
, V
DOH
=24 V
2.0
6.0
s
DOn fall time
t
fDO
R
L
=1.0 k
, V
DOH
=24 V
3.5
10.0
s
Clock frequency
f
CLK
When cascade connection
5.0
MHz
Figure 3
CLK
SI
LATCH
SO
LATCH
AEN
BEN
DO
n
HIST
OLD
1/f
CLK
t
WCLK
t
SUD
t
HD
t
SULA
t
WLA
t
dSO
t
dDO
t
fDO
t
dDO
t
rDO
90%
50%
10%
64-bit THERMAL HEAD DRIVER
S-4621A
6
Seiko Instruments Inc.
n
Dimensions
n
Pad Coordinates
(The origin of the coordinate axes is the center of the chip)
Table 6
Unit:
m
Pad
No.
Name
X
Y
Pad
No.
Name
X
Y
Pad
No.
Name
X
Y
1
DO
1
-3465
257.5
29
DO
29
-385
257.5
57
DO
57
2695
257.5
2
DO
2
-3355
257.5
30
DO
30
-275
257.5
58
DO
58
2805
257.5
3
DO
3
-3245
257.5
31
DO
31
-165
257.5
59
DO
59
2915
257.5
4
DO
4
-3135
257.5
32
DO
32
-55
257.5
60
DO
60
3025
257.5
5
DO
5
-3025
257.5
33
DO
33
55
257.5
61
DO
61
3135
257.5
6
DO
6
-2915
257.5
34
DO
34
165
257.5
62
DO
62
3245
257.5
7
DO
7
-2805
257.5
35
DO
35
275
257.5
63
DO
63
3355
257.5
8
DO
8
-2695
257.5
36
DO
36
385
257.5
64
DO
64
3465
257.5
9
DO
9
-2585
257.5
37
DO
37
495
257.5
65
V
SS1
3455
-257.5
10
DO
10
-2475
257.5
38
DO
38
605
257.5
66
V
SS1
3335
-257.5
11
DO
11
-2365
257.5
39
DO
39
715
257.5
67
V
SS
2855
-257.5
12
DO
12
-2255
257.5
40
DO
40
825
257.5
68
SO
2455
-257.5
13
DO
13
-2145
257.5
41
DO
41
935
257.5
69
LATCH
2005
-257.5
14
DO
14
-2035
257.5
42
DO
42
1045
257.5
70
BEN
1605
-257.5
15
DO
15
-1925
257.5
43
DO
43
1155
257.5
71
V
DD
1135
-257.5
16
DO
16
-1815
257.5
44
DO
44
1265
257.5
72
CONT
685
-257.5
17
DO
17
-1705
257.5
45
DO
45
1375
257.5
73
V
SS1
60
-242.5
18
DO
18
-1595
257.5
46
DO
46
1485
257.5
74
V
SS1
-60
-242.5
19
DO
19
-1485
257.5
47
DO
47
1595
257.5
75
V
SS0
-460
-257.5
20
DO
20
-1375
257.5
48
DO
48
1705
257.5
76
AEN
-940
-257.5
21
DO
21
-1265
257.5
49
DO
49
1815
257.5
77
CLK
-1360
-257.5
22
DO
22
-1155
257.5
50
DO
50
1925
257.5
78
HIST
-1600
-257.5
23
DO
23
-1045
257.5
51
DO
51
2035
257.5
79
OLD
-2020
-257.5
24
DO
24
-935
257.5
52
DO
52
2145
257.5
80
V
DD
-2445
-257.5
25
DO
25
-825
257.5
53
DO
53
2255
257.5
81
SI
-2845
-257.5
26
DO
26
-715
257.5
54
DO
54
2365
257.5
82
V
SS1
-3335
-257.5
27
DO
27
-605
257.5
55
DO
55
2475
257.5
83
V
SS1
-3455
-257.5
28
DO
28
-495
257.5
56
DO
56
2585
257.5
7.25 mm
*
1
2
64
63
65
66
67
81
82
83
110
m
(0,0)
0.71 mm
*
Pad size : 80
m
80
m
(passivation opening)
Pad pitch : 110
m (driver output pad)
Chip thickness : 350
30
m
Before dicing
Figure 3
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