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Электронный компонент: SAB-C501G-1E24N

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Data Sheet 04.97
Microcomputer Components
C501
8-Bit CMOS Microcontroller
Edition 1997-04-01
Published by
Siemens AG,
Bereich Halbleiter, Marketing-
Kommunikation, Balanstrae 73,
81541 Mnchen
Siemens AG 1997.
All Rights Reserved.
Attention please!
As far as patents or other rights of third parties are concerned, liability is only assumed for components, not for applications, processes
and circuits implemented within components or assemblies.
The information describes the type of component and shall not be considered as assured characteristics.
Terms of delivery and rights to change design reserved.
For questions on technology, delivery and prices please contact the Semiconductor Group Offices in Germany or the Siemens Companies
and Representatives worldwide (see address list).
Due to technical requirements components may contain dangerous substances. For information on the types in question please contact
your nearest Siemens Office, Semiconductor Group.
Siemens AG is an approved CECC manufacturer.
Packing
Please use the recycling operators known to you. We can also help you get in touch with your nearest sales office. By agreement we will
take packing material back, if it is sorted. You must bear the costs of transport.
For packing material that is returned to us unsorted or which we are not obliged to accept, we shall have to invoice you for any costs in-
curred.
Components used in life-support devices or systems must be expressly authorized for such purpose!
Critical components
1
of the Semiconductor Group of Siemens AG, may only be used in life-support devices or systems
2
with the express
written approval of the Semiconductor Group of Siemens AG.
1 A critical component is a component used in a life-support device or system whose failure can reasonably be expected to cause the
failure of that life-support device or system, or to affect its safety or effectiveness of that device or system.
2 Life support devices or systems are intended (a) to be implanted in the human body, or (b) to support and/or maintain and sustain hu-
man life. If they fail, it is reasonable to assume that the health of the user may be endangered.
C501 Data Sheet
Revision History :
1997-04-01
Previous Releases :
11.92, 11.93, 08.94, 08.95, 10.96
Page
(previous
version)
Page
(new
version)
Subjects (changes since last revision)
general
C501G-1E OTP version included
4
5
5-7
11
8, 9, 10
13
14
-
15-18
17
-
-
41
-
4
5
5-7
11
8, 9, 10
13
14
15
16-18
17
25-28
31
41
43, 44
Ordering information resorted and C501G-1E types added
Table with literature hints added
Pin configuration logic symbol for pins EA/Vpp and ALE/PROG updated
Pin description for ALE/PROG and EA/Vpp completed
Port 1, 3, 2 pin description: "bidirectional" replaced by "quasi-
bidirectional"
Block diagram updated for C501G-1E
New design of register (PSW) description
"Memory organization" added
Actualized design of the SFR tables
Reset value of T2CON corrected
Description for the C501-1E OTP version added
DC characteristics for C501-1E added
Timing "External Clock Drive" now behind "Data Memory Cycle"
AC characteristics for C501-1E added

C501
Semiconductor Group
3
1997-04-01
8-Bit CMOS Microcontroller
Preliminary
C501
Fully compatible to standard 8051 microcontroller
Versions for 12/24/40 MHz operating frequency
Program memory : completely external (C501-L)
8K
8 ROM (C501-1R)
8K
8 OTP memory (C501-1E)
256
8 RAM
Four 8-bit ports
Three 16-bit timers / counters (timer 2 with up/down counter feature)
USART
Six interrupt sources, two priority levels
Power saving modes
Quick Pulse programming algorithm (C501-1E only)
2-Level program memory lock (C501-1E only)
P-DIP-40, P-LCC-44, and P-MQFP-44 package
Temperature ranges :
SAB-C501
T
A
: 0
C to 70
C
SAF-C501
T
A
: 40
C to 85
C
Figure 1
C501G Functional Units
MCA03238
Port 0
Port 1
Port 2
Port 3
RAM
256 x 8
CPU
T0
T1
USART
Power
Saving
8K x 8 OTP (C501-1E)
T2
Modes
8K x 8 ROM (C501-1R)
/O
/O
/O
/O
C501
Semiconductor Group
4
1997-04-01
The C501-1R contains a non-volatile 8K
8 read-only program memory, a volatile 256
8 read/
write data memory, four ports, three 16-bit timers counters, a seven source, two priority level
interrupt structure and a serial port. The C501-L is identical, except that it lacks the program
memory on chip. The C501-1E contains a one-time programmable (OTP) program memory on chip.
The term C501 refers to all versions within this specification unless otherwise noted. Further, the
term C501 refers to all versions which are available in the different temperature ranges, marked with
SAB-C501... or SAF-C501....
.
Ordering Information
Type
Ordering Code Package
Description
(8-Bit CMOS microcontroller)
SAB-C501G-LN
SAB-C501G-LP
SAB-C501G-LM
Q67120-C969
Q67120-C968
Q67127-C970
P-LCC-44
P-DIP-40
P-MQFP-44
for external memory (12 MHz)
SAB-C501G-L24N
SAB-C501G-L24P
SAB-C501G-L24M
Q67120-C1001
Q67120-C999
Q67127-C1014
P-LCC-44
P-DIP-40
P-MQFP-44
for external memory (24 MHz)
SAB-C501G-L40N
SAB-C501G-L40P
SAB-C501G-L40M
Q67120-C1002
Q67120-C1000
Q67127-C1009
P-LCC-44
P-DIP-40
P-MQFP-44
for external memory (40 MHz)
SAF-C501G-L24N
SAF-C501G-L24P
Q67120-C1011
Q67120-C1010
P-LCC-44
P-MQFP-44
for external memory (24 MHz)
ext. temp. 40 C to 85 C
SAB-C501G-1RN
SAB-C501G-1RP
SAB-C501G-1RM
Q67120-DXXX
Q67120-DXXX
Q67127-DXXX
P-LCC-44
P-DIP-40
P-MQFP-44
with mask-programmable ROM (12 MHz)
SAB-C501G-1R24N
SAB-C501G-1R24P
SAB-C501G-1R24M
Q67120-DXXX
Q67120-DXXX
Q67127-DXXX
P-LCC-44
P-DIP-40
P-MQFP-44
with mask-programmable ROM (24 MHz)
SAB-C501G-1R40N
SAB-C501G-1R40P
SAB-C501G-1R40M
Q67120-DXXX
Q67120-DXXX
Q67127-DXXX
P-LCC-44
P-DIP-40
P-MQFP-44
with mask-programmable ROM (40 MHz)
SAF-C501G-1R24N
SAF-C501G-1R24P
Q67120-DXXX
Q67120-DXXX
P-LCC-44
P-DIP-40
with mask-programmable ROM (24 MHz)
ext. temp. 40 C to 85 C
SAB-C501G-1EN
SAB-C501G-1EP
Q67120-C1054
Q67120-C1056
P-LCC-44
P-DIP-40
with OTP memory (12 MHz)
SAF-C501G-1EN
SAF-C501G-1EP
Q67120-C2002
Q67120-C2003
P-LCC-44
P-DIP-40
with OTP memory (12 MHz))
ext. temp. 40
C to 85
C
SAB-C501G-1E24N
SAB-C501G-1E24P
Q67120-C2005
Q67120-C2006
P-LCC-44
P-DIP-40
with OTP memory (24 MHz)
SAF-C501G-1E24N
SAF-C501G-1E24P
Q67120-C2008
Q67120-C2009
P-LCC-44
P-DIP-40
with OTP memory (24 MHz))
ext. temp. 40
C to 85
C
Semiconductor Group
5
1997-04-01
C501
Note:
Versions for extended temperature range 40
C to 110
C (SAH-C501G) on request.
The ordering number of ROM types (DXXX extensions) is defined after program release
(verification) of the customer.
Additional Literature
For further information about the C501 the following literature is available :
Figure 2
Pin Configuration P-LCC-44 Package (Top view)
Title
Ordering Number
C501 8-Bit CMOS Microcontroller User's Manual
B158-H6723-X-X-7600
C500 Microcontroller Family
Architecture and Instruction Set User's Manual
B158-H6987-X-X-7600
C500 Microcontroller Family - Pocket Guide
B158-H6986-X-X-7600
MCP03214
6
5
4
3
2
1 44 43 42 41 40
28
27
26
25
24
23
22
21
20
19
18
29
30
31
32
33
34
35
36
37
38
39
7
8
9
10
11
12
13
14
15
16
17
P1.5
P1.6
P1.7
RxD/P3.0
N.C.
TxD/P3.1
INT0/P3.2
INT1/P3.3
T0/P3.4
T1/P3.5
WR/P3.6
RD/P3.7
XTAL2
XTAL1
P2.0/A8
P2.1/A9
P2.2/A10
P2.3/A11
P2.5/A13
P2.6/A14
P2.7/A15
PSEN
ALE/PROG
EA/
P0.6/AD6
P0.5/AD5
P0.4/AD4
P0.3/AD3
P0.2/AD2
P0.1/AD1
P0.0/AD0
N.C
P1.3
P1.4
C501
N.C.
V
CC
V
SS
RESET
P0.7/AD7
P1.2
P1.0/T2
P1.1/T2EX
P2.4/A12
N.C.
V
PP
C501
Semiconductor Group
6
1997-04-01
Figure 3
Pin Configuration P-DIP-40 Package
(top view)
MCP03215
XTAL1
XTAL2
P2.5/A13
SS
V
28
1
27
2
26
3
25
4
24
5
23
6
22
7
21
8
9
10
11
12
13
14
P1.7
P0.7/AD7
RESET
RxD/P3.0
ALE/PROG
PSEN
P2.7/A15
P2.6/A14
T0/P3.4
T1/P3.5
P2.4/A12
WR/P3.6
P2.3/A11
P2.2/A10
P2.1/A9
P2.0/A8
P1.3
P1.2
T2EX/P1.1
V
CC
P0.4/AD4
P0.3/AD3
P0.1/AD1
29
30
31
32
33
34
35
36
40
39
38
37
20
19
18
17
16
15
C501
RD/P3.7
TxD/P3.1
INT1/P3.3
INT0/P3.2
P1.4
P1.5
P1.6
T2/P1.0
P0.0/AD0
P0.2/AD2
P0.6/AD6
P0.5/AD5
EA/
PP
V
Semiconductor Group
7
1997-04-01
C501
Figure 4
Pin Configuration P-MQFP-44 Package
(top view)
Figure 5
Logic Symbol
MCP03216
P1.5
P1.6
P1.7
RxD/P3.0
N.C.
TxD/P3.1
INT0/P3.2
INT1/P3.3
T0/P3.4
T1/P3.5
P2.5/A13
P2.6/A14
P2.7/A15
PSEN
ALE/PROG
EA/
P0.6/AD6
P0.5/AD5
P0.4/AD4
V
CC
V
SS
RESET
P0.7/AD7
C501
N.C.
22
34
21
35
20
36
19
37
18
38
17
39
16
40
15
41
14
42
13
43
23
24
25
26
27
28
29
30
31
32
44
12
33
10
9
8
7
6
5
4
3
2
1
11
P0.3/AD3
P0.2/AD2
P0.1/AD1
P0.0/AD0
N.C.
P1.0/T2
P1.1/T2EX
P1.2
P1.3
P1.4
WR/P3.6
RD/P3.7
XTAL2
XTAL1
N.C.
P2.0/A8
P2.1/A9
P2.2/A10
P2.3/A11
P2.4/A12
PP
V
MCL03217
8-Bit Digital
CC
V
V
SS
/O
C501
Port 0
Port 1
/O
8-Bit Digital
Port 2
/O
8-Bit Digital
Port 3
/O
8-Bit Digital
XTAL1
XTAL2
RESET
EA
ALE/PROG
PSEN
PP
V
/
C501
Semiconductor Group
8
1997-04-01
Table 1
Pin Definitions and Functions
Symbol
Pin Number
I/O*) Function
P-LCC-44 P-DIP-40 P-MQFP-44
P1.0 P1.7 29
2
3
18
1
2
4044,
13,
40
41
I/O
Port 1
is a quasi-bidirectional I/O port with
internal pull-up resistors. Port 1 pins that
have 1s written to them are pulled high by
the internal pullup resistors, and in that
state can be used as inputs. As inputs,
port 1 pins being externally pulled low will
source current (
I
IL
, in the DC character-
istics) because of the internal pull-up
resistors. Port 1 also contains the timer 2
pins as secondary function. The output
latch corresponding to a secondary
function must be pro-grammed to a one
(1) for that function to operate.
The secondary functions are assigned to
the pins of port 1, as follows:
P1.0
T2
Input to counter 2
P1.1
T2EX Capture - Reload trigger of
timer 2 / Up-Down count
*) I
= Input
O = Output
Semiconductor Group
9
1997-04-01
C501
P3.0 P3.7 11,
1319
11
13
14
15
16
17
18
19
1017
10
11
12
13
14
15
16
17
5, 713
5
7
8
9
10
11
12
13
I/O
Port 3
is a quasi-bidirectional I/O port with
internal pull-up resistors. Port 3 pins that
have 1s written to them are pulled high by
the internal pull-up resistors, and in that
state they can be used as inputs. As
inputs, port 3 pins being externally pulled
low will source current (
I
IL
, in the DC
characteristics) because of the internal
pull-up resistors. Port 3 also contains the
interrupt, timer, serial port 0 and external
memory strobe pins which are used by
various options. The output latch
corresponding to a secondary function
must be programmed to a one (1) for that
function to operate.
The secondary functions are assigned to
the pins of port 3, as follows:
P3.0
R
D
receiver data input (asyn-
chronous) or data input
output (synchronous) of
serial interface 0
P3.1
T
D
transmitter data output
(asynchronous) or clock
output (synchronous) of
the serial interface 0
P3.2
INT0
interrupt 0 input/timer 0
gate control
P3.3
INT1
interrupt 1 input/timer 1
gate control
P3.4
T0
counter 0 input
P3.5
T1
counter 1 input
P3.6
WR
the write control signal lat-
ches the data byte from
port 0 into the external
data memory
P3.7
RD
the read control signal
enables the external data
memory to port 0
*) I
= Input
O = Output
Table 1
Pin Definitions and Functions
(cont'd)
Symbol
Pin Number
I/O*) Function
P-LCC-44 P-DIP-40 P-MQFP-44
C501
Semiconductor Group
10
1997-04-01
XTAL2
20
18
14
XTAL2
Output of the inverting oscillator
amplifier.
XTAL1
21
19
15
XTAL1
Input to the inverting oscillator amplifier
and input to the internal clock generator
circuits.
To drive the device from an external
clock source, XTAL1 should be driven,
while XTAL2 is left unconnected. There
are no requirements on the duty cycle of
the external clock signal, since the input
to the internal clocking circuitry is divided
down by a divide-by-two flip-flop.
Minimum and maximum high and low
times as well as rise fall times specified
in the AC characteristics must be
observed.
P2.0 P2.7 2431
2128
1825
I/O
Port 2
is a quasi-bidirectional I/O port with
internal pull-up resistors. Port 2 pins that
have 1s written to them are pulled high
by the internal pull-up resistors, and in
that state they can be used as inputs. As
inputs, port 2 pins being externally pulled
low will source current (
I
IL
, in the DC
characteristics) because of the internal
pull-up resistors. Port 2 emits the high-
order address byte during fetches from
external program memory and during
accesses to external data memory that
use 16-bit addresses (MOVX @DPTR).
In this application it uses strong internal
pull-up resistors when issuing 1s. During
accesses to external data memory that
use 8-bit addresses (MOVX @Ri), port
2 issues the contents of the P2 special
function register.
*) I
= Input
O = Output
Table 1
Pin Definitions and Functions
(cont'd)
Symbol
Pin Number
I/O*) Function
P-LCC-44 P-DIP-40 P-MQFP-44
Semiconductor Group
11
1997-04-01
C501
PSEN
32
29
26
O
The Program Store Enable
output is a control signal that enables the
external program memory to the bus
during external fetch operations. It is
activated every six oscillator periods
except during external data memory
accesses. Remains high during internal
program execution.
RESET
10
9
4
I
RESET
A high level on this pin for two machine
cycles while the oscillator is running
resets the device. An internal diffused
resistor to
V
SS
permits power-on reset
using only an external capacitor to
V
CC
.
ALE/PROG 33
30
27
I/O
The
Address Latch Enable
output is used for latching the low-byte of
the address into external memory during
normal operation. It is activated every six
oscillator periods except during an
external data memory access.
For the C501-1E this pin is also the
program pulse input (PROG) during OTP
memory programming.
EA/
V
PP
35
31
29
I
External Access Enable
When held at high level, instructions are
fetched from the internal ROM (C501-1R
and C501-1E) when the PC is less than
2000H. When held at low level, the C501
fetches all instructions from external
program memory. For the C501-L this
pin must be tied low.
This pin also receives the programming
supply voltage
V
PP
during OTP memory
programming (C501-1E) only).
*) I
= Input
O = Output
Table 1
Pin Definitions and Functions
(cont'd)
Symbol
Pin Number
I/O*) Function
P-LCC-44 P-DIP-40 P-MQFP-44
C501
Semiconductor Group
12
1997-04-01
P0.0 P0.7 4336
3932
3730
I/O
Port 0
is an 8-bit open-drain bidirectional I/O
port. Port 0 pins that have 1s written to
them float, and in that state can be used
as high-impedance inputs. Port 0 is also
the multiplexed low-order address and
data bus during accesses to external
program or data memory. In this
application it uses strong internal pull-up
resistors when issuing 1s.
Port 0 also outputs the code bytes during
program verification in the C501-1R and
C501-1E. External pull-up resistors are
required during program verification.
V
SS
22
20
16
Circuit ground potential
V
CC
44
40
38
Supply terminal for all operating modes
N.C.
1, 12,
23, 34
6, 17,
28, 39
No connection
*) I
= Input
O = Output
Table 1
Pin Definitions and Functions
(cont'd)
Symbol
Pin Number
I/O*) Function
P-LCC-44 P-DIP-40 P-MQFP-44
Semiconductor Group
13
1997-04-01
C501
Functional Description
The C501 is fully compatible to the standard 8051 microcontroller family.
It is compatible with the 80C32/52/82C52. While maintaining all architectural and operational
characteristics of the 8051microcontroller family, the C501 incorporates some enhancements in the
timer 2 unit.
Figure 6 shows a block diagram of the C501.
Figure 6
Block Diagram of the C501
Port 3
Port 3
Port 2
Port 2
Port 1
Port 1
/O
8-Bit Digit.
Port 0
Port 0
RAM
RESET
ALE/PROG
PSEN
EA/
MCB03219
XTAL2
OSC & Timing
CPU
Timer 0
Timer 1
Timer 2
Interrupt Unit
Serial Channel
(USART)
C501
V
XTAL1
CC
SS
V
V
PP
256 x 8
C501-1R : ROM
C501-1E : OTP
8K x 8
8-Bit Digit.
/O
8-Bit Digit.
/O
8-Bit Digit.
/O
C501
Semiconductor Group
14
1997-04-01
CPU
The C501 is efficient both as a controller and as an arithmetic processor. It has extensive facilities
for binary and BCD arithmetic and excels in its bit-handling capabilities. Efficient use of program
memory results from an instruction set consisting of 44 % one-byte, 41 % two-byte, and 15%
three-byte instructions. With a 12 MHz crystal, 58% of the instructions are executed in 1.0
s
24 MHz: 500 ns, 40 MHz : 300 ns).
Special Function Register PSW (Address D0H)
Reset Value : 00H
Bit
Function
CY
Carry Flag
Used by arithmetic instruction.
AC
Auxiliary Carry Flag
Used by instructions which execute BCD operations.
F0
General Purpose Flag
RS1
RS0
Register Bank select control bits
These bits are used to select one of the four register banks.
OV
Overflow Flag
Used by arithmetic instruction.
F1
General Purpose Flag
P
Parity Flag
Set/cleared by hardware after each instruction to indicate an odd/even
number of "one" bits in the accumulator, i.e. even parity.
CY
AC
F0
RS1
RS0
OV
F1
P
D0H
PSW
D7H
D6H
D5H
D4H
D3H
D2H
D1H
D0H
Bit No.
MSB
LSB
RS1
RS0
Function
0
0
Bank 0 selected, data address 00H-07H
0
1
Bank 1 selected, data address 08H-0FH
1
0
Bank 2 selected, data address 10H-17H
1
1
Bank 3 selected, data address 18H-1FH
Semiconductor Group
15
1997-04-01
C501
Memory Organization
The C501 CPU manipulates data and operands in the following four address spaces:
up to 64 Kbyte of internal/external program memory
up to 64 Kbyte of external data memory
256 bytes of internal data memory
a 128 byte special function register area
Figure 7 illustrates the memory address spaces of the C501.
Figure 7
C501 Memory Map
MCD03224
00 H
H
7F
External
FFFF H
"Code Space"
"Data Space"
"Internal Data Space"
H
0000
RAM
Internal
Internal
RAM
FFH
H
80
Function
Special
Register
Direct
Address
80 H
H
FF
Address
Indirect
(EA = 0)
(EA = 1)
Internal
External
H
FFFF
External
H
0000
2000 H
1FFF H
C501
Semiconductor Group
16
1997-04-01
Special Function Registers
The registers, except the program counter and the four general purpose register banks, reside in
the special function register area.
The 27 special function registers (SFRs) include pointers and registers that provide an interface
between the CPU and the other on-chip peripherals. All SFRs with addresses where address bits
0-2 are 0 (e.g. 80H, 88H, 90H, 98H, ..., F8H, FFH) are bitaddressable.
The SFRs of the C501 are listed in table 2 and table 3. In table 2 they are organized in groups
which refer to the functional blocks of the C501. Table 3 illustrates the contents of the SFRs in
numeric order of their addresses.
Semiconductor Group
17
1997-04-01
C501
Table 2
Special Function Registers - Functional Blocks
Block
Symbol
Name
Address
Contents after
Reset
CPU
ACC
B
DPH
DPL
PSW
SP
Accumulator
B-Register
Data Pointer, High Byte
Data Pointer, Low Byte
Program Status Word Register
Stack Pointer
E0H
1)
F0H
1)
83H
82H
D0H
1)
81H
00H
00H
00H
00H
00H
07H
Interrupt
System
IE
IP
Interrupt Enable Register
Interrupt Priority Register
A8H
1)
B8H
1)
0X000000B
3)
XX000000B
3)
Ports
P0
P1
P2
P3
Port 0
Port 1
Port 2
Port 3
80H
1)
90H
1)
A0H
1)
B0H
1)
FFH
FFH
FFH
FFH
Serial
Channel
PCON
2)
SBUF
SCON
Power Control Register
Serial Channel Buffer Register
Serial Channel Control Register
87H
99H
98H
1)
0XXX0000B
3)
XXH
3)
00H
Timer 0 /
Timer 1
TCON
TH0
TH1
TL0
TL1
TMOD
Timer 0/1 Control Register
Timer 0, High Byte
Timer 1, High Byte
Timer 0, Low Byte
Timer 1, Low Byte
Timer Mode Register
88H
1)
8CH
8DH
8AH
8BH
89H
00H
00H
00H
00H
00H
00H
Timer 2
T2CON
T2MOD
RC2H
RC2L
TH2
TL2
Timer 2 Control Register
Timer 2 Mode Register
Timer 2 Reload/Capture Register, High Byte
Timer 2 Reload/Capture Register, Low Byt
Timer 2 High Byte
Timer 2 Low Byte
C8H
1)
C9H
CBH
CAH
CDH
CCH
00H
XXXXXXX0B
3)
00H
00H
00H
00H
Pow. Sav.
Modes
PCON
2)
Power Control Register
87H
0XXX0000B
3)
1) Bit-addressable special function registers
2) This special function register is listed repeatedly since some bits of it also belong to other functional blocks.
3) "X" means that the value is undefined and the location is reserved
C501
Semiconductor Group
18
1997-04-01
Table 3
Contents of the SFRs, SFRs in numeric order of their addresses
Addr Register Content
after
Reset
1)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
80H
2)
P0
FFH
.7
.6
.5
.4
.3
.2
.1
.0
81H SP
07H
.7
.6
.5
.4
.3
.2
.1
.0
82H DPL
00H
.7
.6
.5
.4
.3
.2
.1
.0
83H DPH
00H
.7
.6
.5
.4
.3
.2
.1
.0
87H PCON
0XXX-
0000B
SMOD
GF1
GF0
PDE
IDLE
88H
2)
TCON
00H
TF1
TR1
TF0
TR0
IE1
IT1
IE0
IT0
89H TMOD
00H
GATE
C/T
M1
M0
GATE
C/T
M1
M0
8AH TL0
00H
.7
.6
.5
.4
.3
.2
.1
.0
8BH TL1
00H
.7
.6
.5
.4
.3
.2
.1
.0
8CH TH0
00H
.7
.6
.5
.4
.3
.2
.1
.0
8DH TH1
00H
.7
.6
.5
.4
.3
.2
.1
.0
90H
2)
P1
FFH
.7
.6
.5
.4
.3
.2
.1
.0
98H
2)
SCON
00H
SM0
SM1
SM2
REN
TB8
RB8
TI
RI
99H SBUF
XXH
.7
.6
.5
.4
.3
.2
.1
.0
A0H
2)
P2
FFH
.7
.6
.5
.4
.3
.2
.1
.0
A8H
2)
IE
0X00-
0000B
EA
ET2
ES
ET1
EX1
ET0
EX0
B0H
2)
P3
FFH
RD
WR
T1
T0
INT1
INT0
TxD
RxD
B8H
2)
IP
XX00.
0000B
PT2
PS
PT1
PX1
PT0
PX0
C8H
2)
T2CON
00H
TF2
EXF2
RCLK
TCLK
EXEN2 TR2
C/T2
CP/RL2
C9H T2MOD
XXXX-
XXX0B
DCEN
CAH RC2L
00H
.7
.6
.5
.4
.3
.2
.1
.0
CBH RC2H
00H
.7
.6
.5
.4
.3
.2
.1
.0
CCH TL2
00H
.7
.6
.5
.4
.3
.2
.1
.0
CDH TH2
00H
.7
.6
.5
.4
.3
.2
.1
.0
D0H
2)
PSW
00H
CY
AC
F0
RS1
RS0
OV
F1
P
E0H
2)
ACC
00H
.7
.6
.5
.4
.3
.2
.1
.0
F0H
2)
B
00H
.7
.6
.5
.4
.3
.2
.1
.0
1) X means that the value is undefined and the location is reserved
2) Bit-addressable special function registers
Semiconductor Group
19
1997-04-01
C501
Timer / Counter 0 and 1
Timer/counter 0 and 1 can be used in four operating modes as listed in table 4.
In the "timer" function (C/T = `0') the register is incremented every machine cycle. Therefore the
count rate is
f
OSC
/12.
In the "counter" function the register is incremented in response to a 1-to-0 transition at its
corresponding external input pin (P3.4/T0, P3.5/T1). Since it takes two machine cycles to detect a
falling edge the max. count rate is
f
OSC
/24. External inputs INTO and INT1 (P3.2, P3.3) can be
programmed to function as a gate to facilitate pulse width measurements. Figure 8 illustrates the
input clock logic.
Figure 8
Timer/Counter 0 and 1 Input Clock Logic
Table 4
Timer/Counter 0 and 1 Operating Modes
Mode
Description
TMOD
Input Clock
Gate
C/T
M1
M0
internal
external (max)
0
8-bit timer/counter with a
divide-by-32 prescaler
X
X
0
0
f
OSC
/
12
32
f
OSC
/
24
32
1
16-bit timer/counter
X
X
1
1
f
OSC
/
12
f
OSC
/
24
2
8-bit timer/counter with
8-bit autoreload
X
X
0
0
f
OSC
/
12
f
OSC
/
24
3
Timer/counter 0 used as one
8-bit timer/counter and one
8-bit timer
Timer 1 stops
X
X
1
1
f
OSC
/
12
f
OSC
/
24
12
f
OSC
/12
MCS01768
OSC
f
C/T
TMOD
0
Control
Timer 0/1
Input Clock
TCON
TR 0/1
Gate
TMOD
&
=1
1
P3.4/T0
P3.5/T1
max
P3.2/INT0
P3.3/INT1
OSC
/24
f
1
_
<
C501
Semiconductor Group
20
1997-04-01
Timer 2
Timer 2 is a 16-bit timer/counter with an up/down count feature. It can operate either as timer or as
an event counter which is selected by bit C/T2 (T2CON.1). It has three operating modes as shown
in table 5.
Note:
=
falling edge
Table 5
Timer/Counter 2 Operating Modes
Mode
T2CON
T2MOD
DCEN
T2CON
EXEN
P1.1/
T2EX
Remarks
Input Clock
R
CLK
or
T
CLK
CP/
RL2
TR2
internal
external
(P1.0/T2)
16-bit
Auto-
reload
0
0
0
0
0
0
0
0
1
1
1
1
0
0
1
1
0
1
X
X
X
0
1
reload upon
overflow
reload trigger
(falling edge)
Down counting
Up counting
f
OSC
/12
max
f
OSC
/24
16-bit
Cap-
ture
0
0
1
1
1
1
X
X
0
1
X
16 bit Timer/
Counter (only
up-counting)
capture TH2,
TL2
RC2H,
RC2L
f
OSC
/12
max
f
OSC
/24
Baud
Rate
Gene-
rator
1
1
X
X
1
1
X
X
0
1
X
no overflow
interrupt
request (TF2)
extra external
interrupt
("Timer 2")
f
OSC
/2
max
f
OSC
/24
off
X
X
0
X
X
X
Timer 2 stops
Semiconductor Group
21
1997-04-01
C501
Serial Interface (USART)
The serial port is full duplex and can operate in four modes (one synchronous mode, three
asynchronous modes) as illustrated in table 6. The possible baudrates can be calculated using the
formulas given in table 7.
Table 6
USART Operating Modes
Mode
SCON
Baudrate
Description
SM0
SM1
0
0
0
f
OSC
/12
Serial data enters and exits through R
D.
T
D outputs the shift clock. 8-bit are
transmitted/received (LSB first)
1
0
1
Timer 1/2 overflow rate
8-bit UART
10 bits are transmitted (through T
D) or
received (R
D)
2
1
0
f
OSC
/32 or
f
OSC
/64
9-bit UART
11 bits are transmitted (T
D) or
received (R
D)
3
1
1
Timer 1/2 overflow rate
9-bit UART
Like mode 2 except the variable baud rate
Table 7
Formulas for Calculating Baudrates
Baud Rate
derived from
Interface Mode
Baudrate
Oscillator
0
2
f
OSC
/12
(2
SMOD
f
OSC
) / 64
Timer 1 (16-bit timer)
(8-bit timer with
8-bit autoreload)
1,3
1,3
(2
SMOD
timer 1 overflow rate) /32
(2
SMOD
f
OSC
) / (32
12
(256-TH1))
Timer 2
1,3
f
OSC
/ (32
(65536-(RC2H, RC2L))
C501
Semiconductor Group
22
1997-04-01
Interrupt System
The C501 provides 6 interrupt sources with two priority levels. Figure 9 gives a general overview of
the interrupt sources and illustrates the request and control flags.
Figure 9
Interrupt Request Sources
Timer 2 Overflow
Timer 1 Overflow
MCS01783
TF0
ET0
P1.1/
T2EX
P3.2/
INT0
EA
High Priority
Timer 0 Overflow
TCON.5
PT0
Low Priority
PT1
TCON.7
ET1
TF1
IE.1
IP.1
IP.3
T2CON.3
TF2
EXEN2
T2CON.7
PT2
1
EXF2
TI
1
PS
SCON.0
ES
RI
IE.5
IP.5
IP.4
IE.4
IE0
EX0
TCON.1
PX0
ET2
IE.3
IT0
IT1
PX1
TCON.3
EX1
IE1
IE.0
IP.0
INT1
P3.3/
IE.7
TCON.0
TCON.2
SCON.1
T2CON.6
TCON.0
IE.2
IP.2
USART
_
<
_
<
Semiconductor Group
23
1997-04-01
C501
A low-priority interrupt can itself be interrupted by a high-priority interrupt, but not by another low-
priority interrupt. A high-priority interrupt cannot be interrupted by any other interrupt source.
If two requests of different priority level are received simultaneously, the request of higher priority is
serviced. If requests of the same priority are received simultaneously, an internal polling sequence
determines which request is serviced. Thus within each priority level there is a second priority
structure determined by the polling sequence as shown in table 9.
Table 8
Interrupt Sources and their Corresponding Interrupt Vectors
Source (Request Flags)
Vector
Vector Address
IE0
TF0
IE1
TF1
RI + TI
TF2 + EXF2
External interrupt 0
Timer 0 interrupt
External interrupt 1
Timer 1 interrupt
Serial port interrupt
Timer 2 interrupt
0003H
000BH
0013H
001BH
0023H
002BH
Table 9
Interrupt Priority-Within-Level
Interrupt Source
Priority
External Interrupt 0,
Timer 0 Interrupt,
External Interrupt 1,
Timer 1 Interrupt,
Serial Channel,
Timer 2 Interrupt,
IE0
TF0
IE1
TF1
RI + TI
TF2 + EXF2
High
Low
C501
Semiconductor Group
24
1997-04-01
Power Saving Modes
Two power down modes are available, the Idle Mode and Power Down Mode.
The bits PDE and IDLE of the register PCON select the Power Down mode or the Idle mode,
respectively. If the Power Down mode and the Idle mode are set at the same time, the Power Down
mode takes precedence. Table 10 gives a general overview of the power saving modes.
In the Power Down mode of operation,
V
CC
can be reduced to minimize power consumption. It must
be ensured, however, that
V
CC
is not reduced before the Power Down mode is invoked, and that
V
CC
is restored to its normal operating level, before the Power Down mode is terminated. The reset
signal that terminates the Power Down mode also restarts the oscillator. The reset should not be
activated before
V
CC
is restored to its normal operating level and must be held active long enough
to allow the oscillator to restart and stabilize (similar to power-on reset).
Table 10
Power Saving Modes Overview
Mode
Entering
Instruction
Example
Leaving by
Remarks
Idle mode
ORL PCON, #01H
enabled interrupt
Hardware Reset
CPU is gated off
CPU status registers maintain
their data.
Peripherals are active
Power-Down
Mode
ORL PCON, #02H
Hardware Reset
Oscillator is stopped, contents
of on-chip RAM and SFR's are
maintained (leaving Power
Down Mode means redefinition
of SFR contents).
Semiconductor Group
25
1997-04-01
C501
OTP Operation
The C501-1E is programmed by usng a modified Quick-Pulse Programming
TM 1)
algorithm. It differs
from older methods in the value used for V
PP
(programming supply voltage) and in the width and
number of the ALE/PROG pulses. The C501-1E contains two signature bytes that can be read and
used by a programming system to identify the device. The signature bytes identify the manufacturer
of the device.
Table 11 shows the logic levels for reading the signature byte, and for programming the program
memory, the encryption table, and the security bits. The circuit configuration and waveforms for
quick-pulse programming are shown in figures 10 to 12.
Notes :
1. "0" = valid low for that pin, "1" = valid high for that pin.
2. V
PP
= 12.75 V
0.25V
3. V
CC
= 5 V
10% during programming and verification.
4. ALE/PROG receives 25 programming pulses while V
PP
is held at 12.75 V. Each programming pulse is low for
100
s (
10
s) and high for a minimum of 10
s.
1)
Quick-Pulse Programming
TM
is a trademark phrase of Intel Corporation
Table 11
OTP Programming Modes
Mode
RESET
PSEN
ALE/
PROG
EA/V
PP
P2.7
P2.6
P3.7
P3.6
Read signature
1
0
1
1
0
0
0
0
Program code data
1
0
0
V
PP
1
0
1
1
Verify code data
1
0
1
1
0
0
1
1
Progam encryption table
1
0
0
V
PP
1
0
1
0
Program security bit 1
1
0
0
V
PP
1
1
1
1
Program security bit 2
1
0
0
V
PP
1
1
0
0
C501
Semiconductor Group
26
1997-04-01
Quick-Pulse Programming
The setup for microcontroller quick-pulse programming is shown in figure 10. Note that the C501-
1E is running with a 4 to 6 MHz oscillator The reason the oscillator needs to be running is that the
device is executing internal address and program data transfers.
The address of the OTP memory location to be programmed is applied to port 1 and 2 as shown in
figure 10. The code byte to be programmed into that location is applied to port 0. RESET, PSEN
and pins of port 2 and 3 specified in table 11 are held at the "Program code data" levels. The ALE/
PROG signal is pulsed low 25 times as shown in figure 11.
For programming of the encryption table, the 25 pulse programming sequence must be repeated for
addresses 0 through 1FH, using the "Program encrytion table" levels. After the encryption table is
programmed, verification cycles will produce only encrypted data.
For programming of the security bits, the 25 pulse programming sequence must be repeat using the
"Program security bit" levels. After one security bit is programmed, further programming of the code
memory and encryption table is disabled. However, the other security bit can still be programmed.
Note that the EA/V
PP
pin must not be allowed to go above the maximum specified V
PP
level. for any
amount of time. Even a narrow glitch above that voltage can cause permanent damage to the
device. The V
PP
source should be well regulated and free of glitches and overshoots.
Program Verification
If security bit 2 has not been programmed, the on-chip OTP program memory can be read out for
program verification. The address of the OTP program memory locations to be read is applied to
ports 1 and 2 as shown in figure 12. The other pins are held at the "Verify code data" levels
indicated in table 11. The contents of the address location will be emitted on port 0. External pullups
are required on port 0 for this operation.
If the encryption table has been programmed, the data presented at port 0 will be the exclusive NOR
of the program byte with one of the encryption bytes. The user will have to know the encryption
table contents in order to correctly decode the verification data. The encryption table itself cannot be
read out.
Reading the SIgnature Bytes
The signature bytes are read by the same procedure as a normal verification of loctions 30H and
31H, except that P3.6 and P3.7 need to be pulled to a logic low. The values are :
30H = E0H indicates manufacturer
31H = 71H indicates C501-1E
Semiconductor Group
27
1997-04-01
C501
Figure 10
C501-1E OTP Memory Programming Configuration
Figure 11
C501-1E ALE/PROG Waveform
MCS03232
Port 1
RESET
P3.6
P3.7
XTAL2
XTAL1
V
SS
CC
V
Port 0
V
PP
EA/
ALE/PROG
PSEN
P2.7
P2.6
P2.0 - P2.4
Programming
Data
+12.75 V
25 x 100 s
0
1
0
A8 - A12
A0 - A7
1
4 - 6 MHz
C501-1E
1
1
+5 V
Low Pulses
MCT03234
ALE/PROG
10 s min.
25 Pulses
1
0
ALE/PROG
C501
Semiconductor Group
28
1997-04-01
Figure 12
C501-1E OTP Memory Verification
MCS03235
Port 1
RESET
P3.6
P3.7
XTAL2
XTAL1
V
SS
CC
V
Port 0
V
PP
EA/
ALE/PROG
PSEN
P2.7
P2.6
P2.0 - P2.4
10 k
Programming
Data
1
1
0
0
0
Enable
A8 - A12
A0 - A7
1
4 - 6 MHz
C501-1E
1
1
+5 V
Semiconductor Group
29
1997-04-01
C501
Absolute Maximum Ratings
Ambient temperature under bias (
T
A
) ......................................................... 40 to 85
C
Storage temperature (
T
stg
) .......................................................................... 65
C to 150
C
Voltage on
V
CC
pins with respect to ground (
V
SS
) ....................................... 0.5 V to 6.5 V
Voltage on any pin with respect to ground (
V
SS
) ......................................... 0.5 V to
V
CC
+0.5 V
Input current on any pin during overload condition..................................... 10 mA to 10 mA
Absolute sum of all input currents during overload condition ..................... I 100 mA I
Power dissipation........................................................................................ TBD
Note: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent
damage of the device. This is a stress rating only and functional operation of the device at
these or any other conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for longer
periods may affect device reliability. During overload conditions (
V
IN
>
V
CC
or
V
IN
<
V
SS
) the
Voltage on
V
CC
pins with respect to ground (
V
SS
) must not exceed the values defined by the
absolute maximum ratings.
C501
Semiconductor Group
30
1997-04-01
DC Characteristics for C501-L / C501-1R
V
CC
= 5 V + 10 %, 15 %;
V
SS
= 0 V;
T
A
= 0 C to 70 C
for the SAB-C501
T
A
= 40 C to 85 C
for the SAF-C501
Notes see page 32.
Parameter
Symbol
Limit Values
Unit Test Condition
min.
max.
Input low voltage (except EA,
RESET)
V
IL
0.5
0.2
V
CC
0.1 V
Input low voltage (EA)
V
IL 1
0.5
0.2
V
CC
0.3 V
Input low voltage (RESET)
V
IL 2
0.5
0.2
V
CC
+ 0.1 V
Input high voltage (except
XTAL1, EA, RESET)
V
IH
0.2
V
CC
+ 0.9
V
CC
+ 0.5
V
Input high voltage to XTAL1
V
IH 1
0.7
V
CC
V
CC
+ 0.5
V
Input high voltage to EA,
RESET
V
IH 2
0.6
V
CC
V
CC
+ 0.5
V
Output low voltage
(ports 1, 2, 3)
V
OL
0.45
V
I
OL
= 1.6 mA
1)
Output low voltage
(port 0, ALE, PSEN)
V
OL 1
0.45
V
I
OL
= 3.2 mA
1)
Output high voltage
(ports 1, 2, 3)
V
OH
2.4
0.9
V
CC

V
I
OH
= 80
A,
I
OH
= 10
A
Output high voltage
(port 0 in external bus mode,
ALE, PSEN)
V
OH 1
2.4
0.9
V
CC

V
I
OH
= 800
A
2)
,
I
OH
= 80
A
2)
Logic 0 input current
(ports 1, 2, 3)
I
IL
10
50
A
V
IN
= 0.45 V
Logical 1-to-0 transition
current (ports 1, 2, 3)
I
TL
65
650
A
V
IN
= 2 V
Input leakage current
(port 0, EA)
I
LI
1
A
0.45 <
V
IN
<
V
CC
Pin capacitance
C
IO
10
pF
f
C
= 1 MHz,
T
A
= 25 C
Power supply current:
Active mode, 12 MHz
7)
Idle mode, 12 MHz
7)
Active mode, 24 MHz
7)
Idle mode, 24 MHz
7)
Active mode, 40 MHz
7)
Idle mode, 40 MHz
7)
Power Down Mode
I
CC
I
CC
I
CC
I
CC
I
CC
I
CC
I
PD






21
4.8
36.2
8.2
56.5
12.7
50
mA
mA
mA
mA
mA
mA
A
V
CC
= 5 V,
4)
V
CC
= 5 V,
5)
V
CC
= 5 V,
4)
V
CC
= 5 V,
5)
V
CC
= 5 V,
4)
V
CC
= 5 V,
5)
V
CC
= 2 ... 5.5 V
3)
Semiconductor Group
31
1997-04-01
C501
DC Characteristics for C501-1E
V
CC
= 5 V + 10 %, 15 %;
V
SS
= 0 V;
T
A
= 0 C to 70 C
for the SAB-C501
T
A
= 40 C to 85 C
for the SAF-C501
Notes see next page.
Parameter
Symbol
Limit Values
Unit Test Condition
min.
max.
Input low voltage (except
EA/V
PP
, RESET)
V
IL
0.5
0.2
V
CC
0.1 V
Input low voltage (EA/V
PP
)
V
IL 1
0.5
0.1
V
CC
0.1 V
Input low voltage (RESET)
V
IL 2
0.5
0.2
V
CC
+ 0.1 V
Input high voltage (except
XTAL1, EA/V
PP
, RESET)
V
IH
0.2
V
CC
+ 0.9
V
CC
+ 0.5
V
Input high voltage to XTAL1
V
IH 1
0.7
V
CC
V
CC
+ 0.5
V
Input high voltage to EA/V
PP
,
RESET
V
IH 2
0.6
V
CC
V
CC
+ 0.5
V
Output low voltage
(ports 1, 2, 3)
V
OL
0.45
V
I
OL
= 1.6 mA
1)
Output low voltage
(port 0, ALE/PROG, PSEN)
V
OL 1
0.45
V
I
OL
= 3.2 mA
1)
Output high voltage
(ports 1, 2, 3)
V
OH
2.4
0.9
V
CC

V
I
OH
= 80
A,
I
OH
= 10
A
Output high voltage
(port 0 in external bus mode,
ALE/PROG, PSEN)
V
OH 1
2.4
0.9
V
CC

V
I
OH
= 800
A
2)
,
I
OH
= 80
A
2)
Logic 0 input current
(ports 1, 2, 3)
I
IL
10
50
A
V
IN
= 0.45 V
Logical 1-to-0 transition
current (ports 1, 2, 3)
I
TL
65
650
A
V
IN
= 2 V
Input leakage current
(port 0, EA/V
PP
)
I
LI
1
A
0.45 <
V
IN
<
V
CC
Pin capacitance
C
IO
10
pF
f
C
= 1 MHz,
T
A
= 25 C
Power supply current:
Active mode, 12 MHz
7)
Idle mode, 12 MHz
7)
Active mode, 24 MHz
7)
Idle mode, 24 MHz
7)
Power Down Mode
I
CC
I
CC
I
CC
I
CC
I
PD




21
18
36.2
20
50
mA
mA
mA
mA
A
V
CC
= 5 V,
4)
V
CC
= 5 V,
5)
V
CC
= 5 V,
4)
V
CC
= 5 V,
5)
V
CC
= 2 ... 5.5 V
3)
C501
Semiconductor Group
32
1997-04-01
Notes:
1)
Capacitive loading on ports 0 and 2 may cause spurious noise pulses to be superimposed on the
V
OL
of ALE
and port 3. The noise is due to external bus capacitance discharging into the port 0 and port 2 pins when these
pins make 1-to-0 transitions during bus operation. In the worst case (capacitive loading > 100 pF), the noise
pulse on ALE line may exceed 0.8 V. In such cases it may be desirable to qualify ALE with a schmitt-trigger,
or use an address latch with a schmitt-trigger strobe input.
2)
Capacitive loading on ports 0 and 2 may cause the
V
OH
on ALE and PSEN to momentarily fall bellow the
0.9
V
CC
specification when the address lines are stabilizing.
3)
I
PD
(Power Down Mode) is measured under following conditions:
EA = Port0 =
V
CC
; RESET =
V
SS
; XTAL2 = N.C.; XTAL1 =
V
SS
; all other pins are disconnected.
4)
I
CC
(active mode) is measured with:
XTAL1 driven with
t
CLCH
,
t
CHCL
= 5 ns,
V
IL
=
V
SS
+ 0.5 V,
V
IH
=
V
CC
0.5 V; XTAL2 = N.C.;
EA = Port0 = RESET=
V
CC
; all other pins are disconnected.
I
CC
would be slightly higher if a crystal oscillator is
used (appr. 1 mA).
5)
I
CC
(Idle mode) is measured with all output pins disconnected and with all peripherals disabled;
XTAL1 driven with
t
CLCH
,
t
CHCL
= 5 ns,
V
IL
=
V
SS
+ 0.5 V,
V
IH
=
V
CC
0.5 V; XTAL2 = N.C.;
RESET = EA =
V
SS
; Port0
= V
CC
; all other pins are disconnected;
7)
I
CC max
at other frequencies is given by:
active mode:
I
CC
= 1.27 x
f
OSC
+ 5.73
idle mode:
I
CC
= 0.28 x
f
OSC
+ 1.45 (C501-L and C501-1R only)
where
f
OSC
is the oscillator frequency in MHz.
I
CC
values are given in mA and measured at
V
CC
= 5 V.
Semiconductor Group
33
1997-04-01
C501
AC Characteristics for C501-L / C501-1R / C501-1E
V
CC
= 5 V + 10 %, 15 %;
V
SS
= 0 V
T
A
= 0 C to 70 C
for the SAB-C501
T
A
= 40 C to 85 C for the SAF-C501
(
C
L
for port 0, ALE and PSEN outputs = 100 pF;
C
L
for all other outputs = 80 pF)
Program Memory Characteristics
*) Interfacing the C501 to devices with float times up to 75 ns is permissible. This limited bus contention will not
cause any damage to port 0 Drivers.
Parameter
Symbol
Limit Values
Unit
12 MHz
Clock
Variable Clock
1/
t
CLCL
= 3.5 MHz to 12 MHz
min.
max.
min.
max.
ALE pulse width
t
LHLL
127
2
t
CLCL
40
ns
Address setup to ALE
t
AVLL
43
t
CLCL
40
ns
Address hold after ALE
t
LLAX
30
t
CLCL
53
ns
ALE low to valid instr in
t
LLIV
233
4
t
CLCL
100
ns
ALE to PSEN
t
LLPL
58
t
CLCL
25
ns
PSEN pulse width
t
PLPH
215
3
t
CLCL
35
ns
PSEN to valid instr in
t
PLIV
150
3
t
CLCL
100
ns
Input instruction hold after PSEN
t
PXIX
0
0
ns
Input instruction float after PSEN
t
PXIZ
*)
63
t
CLCL
20
ns
Address valid after PSEN
t
PXAV
*)
75
t
CLCL
8
ns
Address to valid instr in
t
AVIV
302
5
t
CLCL
115
ns
Address float to PSEN
t
AZPL
0
0
ns
C501
Semiconductor Group
34
1997-04-01
AC Characteristics for C501-L / C501-1R / C501-1E (cont'd)
External Data Memory Characteristics
External Clock Drive Characteristics
Parameter
Symbol
Limit Values
Unit
12 MHz
Clock
Variable Clock
1/
t
CLCL
= 3.5 MHz to 12 MHz
min.
max.
min.
max.
RD pulse width
t
RLRH
400
6
t
CLCL
100
ns
WR pulse width
t
WLWH
400
6
t
CLCL
100
ns
Address hold after ALE
t
LLAX2
30
t
CLCL
53
ns
RD to valid data in
t
RLDV
252
5
t
CLCL
165
ns
Data hold after RD
t
RHDX
0
0
ns
Data float after RD
t
RHDZ
97
2
t
CLCL
70
ns
ALE to valid data in
t
LLDV
517
8
t
CLCL
150
ns
Address to valid data in
t
AVDV
585
9
t
CLCL
165
ns
ALE to WR or RD
t
LLWL
200
300
3
t
CLCL
50
3
t
CLCL
+ 50
ns
Address valid to WR or RD
t
AVWL
203
4
t
CLCL
130
ns
WR or RD high to ALE high
t
WHLH
43
123
t
CLCL
40
t
CLCL
+ 40
ns
Data valid to WR transition
t
QVWX
33
t
CLCL
50
ns
Data setup before WR
t
QVWH
433
7
t
CLCL
150
ns
Data hold after WR
t
WHQX
33
t
CLCL
50
ns
Address float after RD
t
RLAZ
0
0
ns
Parameter
Symbol
Limit Values
Unit
Variable Clock
Freq. = 3.5 MHz to 12 MHz
min.
max.
Oscillator period
t
CLCL
83.3
285.7
ns
High time
t
CHCX
20
t
CLCL
t
CLCX
ns
Low time
t
CLCX
20
t
CLCL
t
CHCX
ns
Rise time
t
CLCH
20
ns
Fall time
t
CHCL
20
ns
Semiconductor Group
35
1997-04-01
C501
AC Characteristics for C501-L24 / C501-1R24 / C501-1E24
V
CC
= 5 V + 10 %, 15 %;
V
SS
= 0 V
T
A
= 0 C to 70 C
for the SAB-C501
T
A
= 40 C to 85 C for the SAF-C501
(
C
L
for port 0, ALE and PSEN outputs = 100 pF;
C
L
for all other outputs = 80 pF)
Program Memory Characteristics
*) Interfacing the C501 to devices with float times up to 37 ns is permissible. This limited bus contention will not
cause any damage to port 0 Drivers.
Parameter
Symbol
Limit Values
Unit
24 MHz
Clock
Variable Clock
1/
t
CLCL
= 3.5 MHz to 24 MHz
min.
max.
min.
max.
ALE pulse width
t
LHLL
43
2
t
CLCL
40
ns
Address setup to ALE
t
AVLL
17
t
CLCL
25
ns
Address hold after ALE
t
LLAX
17
t
CLCL
25
ns
ALE low to valid instr in
t
LLIV
80
4
t
CLCL
87
ns
ALE to PSEN
t
LLPL
22
t
CLCL
20
ns
PSEN pulse width
t
PLPH
95
3
t
CLCL
30
ns
PSEN to valid instr in
t
PLIV
60
3
t
CLCL
65
ns
Input instruction hold after PSEN
t
PXIX
0
0
ns
Input instruction float after PSEN
t
PXIZ
*)
32
t
CLCL
10
ns
Address valid after PSEN
t
PXAV
*)
37
t
CLCL
5
ns
Address to valid instr in
t
AVIV
148
5
t
CLCL
60
ns
Address float to PSEN
t
AZPL
0
0
ns
C501
Semiconductor Group
36
1997-04-01
AC Characteristics for C501-L24 / C501-1R24 / C501-1E24 (cont'd)
External Data Memory Characteristics
External Clock Drive Characteristics
Parameter
Symbol
Limit Values
Unit
24 MHz
Clock
Variable Clock
1/
t
CLCL
= 3.5 MHz to 24 MHz
min.
max.
min.
max.
RD pulse width
t
RLRH
180
6
t
CLCL
70
ns
WR pulse width
t
WLWH
180
6
t
CLCL
70
ns
Address hold after ALE
t
LLAX2
15
t
CLCL
27
ns
RD to valid data in
t
RLDV
118
5
t
CLCL
90
ns
Data hold after RD
t
RHDX
0
0
ns
Data float after RD
t
RHDZ
63
2
t
CLCL
20
ns
ALE to valid data in
t
LLDV
200
8
t
CLCL
133
ns
Address to valid data in
t
AVDV
220
9
t
CLCL
155
ns
ALE to WR or RD
t
LLWL
75
175
3
t
CLCL
50
3
t
CLCL
+ 50
ns
Address valid to WR or RD
t
AVWL
67
4
t
CLCL
97
ns
WR or RD high to ALE high
t
WHLH
17
67
t
CLCL
25
t
CLCL
+ 25
ns
Data valid to WR transition
t
QVWX
5
t
CLCL
37
ns
Data setup before WR
t
QVWH
170
7
t
CLCL
122
ns
Data hold after WR
t
WHQX
15
t
CLCL
27
ns
Address float after RD
t
RLAZ
0
0
ns
Parameter
Symbol
Limit Values
Unit
Variable Clock
Freq. = 3.5 MHz to 24 MHz
min.
max.
Oscillator period
t
CLCL
41.7
285.7
ns
High time
t
CHCX
12
t
CLCL
t
CLCX
ns
Low time
t
CLCX
12
t
CLCL
t
CHCX
ns
Rise time
t
CLCH
12
ns
Fall time
t
CHCL
12
ns
Semiconductor Group
37
1997-04-01
C501
AC Characteristics for C501-L40 / C501-1R40
V
CC
= 5 V + 10 %, 15 %;
V
SS
= 0 V
T
A
= 0 C to 70 C
for the SAB-C501
T
A
= 40 C to 85 C for the SAF-C501
(
C
L
for port 0, ALE and PSEN outputs = 100 pF;
C
L
for all other outputs = 80 pF)
Program Memory Characteristics
*) Interfacing the C501 to devices with float times up to 25ns is permissible. This limited bus contention will not
cause any damage to port 0 Drivers.
Parameter
Symbol
Limit Values
Unit
40 MHz
Clock
Variable Clock
1/
t
CLCL
= 3.5 MHz to 40 MHz
min.
max.
min.
max.
ALE pulse width
t
LHLL
35
2
t
CLCL
15
ns
Address setup to ALE
t
AVLL
10
t
CLCL
15
ns
Address hold after ALE
t
LLAX
10
t
CLCL
15
ns
ALE low to valid instr in
t
LLIV
55
4
t
CLCL
45
ns
ALE to PSEN
t
LLPL
10
t
CLCL
15
ns
PSEN pulse width
t
PLPH
60
3
t
CLCL
15
ns
PSEN to valid instr in
t
PLIV
25
3
t
CLCL
50
ns
Input instruction hold after PSEN
t
PXIX
0
0
ns
Input instruction float after PSEN
t
PXIZ
*)
20
t
CLCL
5
ns
Address valid after PSEN
t
PXAV
*)
20
t
CLCL
5
ns
Address to valid instr in
t
AVIV
65
5
t
CLCL
60
ns
Address float to PSEN
t
AZPL
5
5
ns
C501
Semiconductor Group
38
1997-04-01
AC Characteristics for C501-L40 / C501-1R40 (cont'd)
External Data Memory Characteristics
External Clock Drive Characteristics
Parameter
Symbol
Limit Values
Unit
40 MHz
Clock
Variable Clock
1/
t
CLCL
= 3.5 MHz to 40 MHz
min.
max.
min.
max.
RD pulse width
t
RLRH
120
6
t
CLCL
30
ns
WR pulse width
t
WLWH
120
6
t
CLCL
30
ns
Address hold after ALE
t
LLAX2
10
t
CLCL
15
ns
RD to valid data in
t
RLDV
75
5
t
CLCL
50
ns
Data hold after RD
t
RHDX
0
0
ns
Data float after RD
t
RHDZ
38
2
t
CLCL
12
ns
ALE to valid data in
t
LLDV
150
8
t
CLCL
50
ns
Address to valid data in
t
AVDV
150
9
t
CLCL
75
ns
ALE to WR or RD
t
LLWL
60
90
3
t
CLCL
15
3
t
CLCL
+ 15
ns
Address valid to WR or RD
t
AVWL
70
4
t
CLCL
30
ns
WR or RD high to ALE high
t
WHLH
10
40
t
CLCL
15
t
CLCL
+ 15
ns
Data valid to WR transition
t
QVWX
5
t
CLCL
20
ns
Data setup before WR
t
QVWH
125
7
t
CLCL
50
ns
Data hold after WR
t
WHQX
5
t
CLCL
20
ns
Address float after RD
t
RLAZ
0
0
ns
Parameter
Symbol
Limit Values
Unit
Variable Clock
Freq. = 3.5 MHz to 40 MHz
min.
max.
Oscillator period
t
CLCL
25
285.7
ns
High time
t
CHCX
10
t
CLCL
t
CLCX
ns
Low time
t
CLCX
10
t
CLCL
t
CHCX
ns
Rise time
t
CLCH
10
ns
Fall time
t
CHCL
10
ns
Semiconductor Group
39
1997-04-01
C501
Figure 13
Program Memory Read Cycle
MCT00096
ALE
PSEN
Port 2
LHLL
t
A8 - A15
A8 - A15
A0 - A7
Instr.IN
A0 - A7
Port 0
t
AVLL
PLPH
t
t
LLPL
t
LLIV
t
PLIV
t
AZPL
t
LLAX
t
PXIZ
t
PXIX
t
AVIV
t
PXAV
C501
Semiconductor Group
40
1997-04-01
Figure 14
Data Memory Read Cycle
MCT00097
ALE
PSEN
Port 2
WHLH
t
Port 0
RD
t
LLDV
t
RLRH
t
LLWL
t
RLDV
t
AVLL
t
LLAX2
t
RLAZ
t
AVWL
t
AVDV
t
RHDX
t
RHDZ
A0 - A7 from
Ri or DPL
from PCL
A0 - A7
Instr.
IN
Data IN
A8 - A15 from PCH
P2.0 - P2.7 or A8 - A15 from DPH
Semiconductor Group
41
1997-04-01
C501
Figure 15
Data Memory Write Cycle
Figure 16
External Clock Drive at XTAL2
MCT00098
ALE
PSEN
Port 2
WHLH
t
Port 0
WR
t
WLWH
t
LLWL
t
QVWX
t
AVLL
t
LLAX2
t
QVWH
t
AVWL
t
WHQX
A0 - A7 from
Ri or DPL
from PCL
A0 - A7
Instr.IN
Data OUT
A8 - A15 from PCH
P2.0 - P2.7 or A8 - A15 from DPH
MCT00033
t
CHCX
t
CLCX
CHCL
t
CLCH
t
V
CC
t
CLCL
- 0.5V
0.45V
CC
0.7
V
V - 0.1
CC
0.2
C501
Semiconductor Group
42
1997-04-01
ROM Verification Characteristics for C501-1R
ROM Verification Mode 1
Figure 17
ROM Verification Mode 1
Parameter
Symbol
Limit Values
Unit
min.
max.
Address to valid data
t
AVQV
48
t
CLCL
ns
ENABLE to valid data
t
ELQV
48
t
CLCL
ns
Data float after ENABLE
t
EHQZ
0
48
t
CLCL
ns
Oscillator frequency
1/
t
CLCL
4
6
MHz
MCT00049
t
AVQV
t
EHQZ
t
ELQV
Address
Data OUT
P1.0 - P1.7
P2.0 - P2.4
Port 0
P2.7
ENABLE
Inputs: P2.5 - P2.6, PSEN =
ALE, EA =
RESET =
P0.0 - P0.7 = D0 - D7
Data:
P2.0 - P2.4 = A8 - A12
Address: P1.0 - P1.7 = A0 - A7
V
IH
SS
V
V
SS
Semiconductor Group
43
1997-04-01
C501
OTP Programming and Verification Characteristics
V
CC
= 5 V
10%,
V
SS
= 0 V
, T
A
= 21 C to + 27 C
Parameter
Symbol
Limit Values
Unit
min.
max.
Programming supply voltage
V
PP
12.5
13.0
V
Programming supply current
I
PP
50
mA
Oscillator frequency
1 /
t
CLCL
4
6
MHz
Address setup to ALE/PROG low
t
AVGL
48
t
CLCL
ns
Address hold after ALE/PROG
t
GHAX
48
t
CLCL
ns
Data setup to ALE/PROG low
t
DVGL
48
t
CLCL
ns
Data hold after ALE/PROG
t
GHDX
48
t
CLCL
ns
P2.7 (ENABLE) high to V
PP
t
EHSH
48
t
CLCL
ns
V
PP
setup to ALE/PROG low
t
SHGL
10
s
V
PP
hold after ALE/PROG low
t
GHSL
10
s
ALE/PROG width
t
GLGH
90
110
s
Address to data valid
t
AVQV
48
t
CLCL
ns
ENABLE low to data valid
t
ELQV
48
t
CLCL
ns
Data float after ENABLE
t
EHQZ
0
48
t
CLCL
ns
ALE/PROG high to ALE/PROG low
t
GHGL
10
s
C501
Semiconductor Group
44
1997-04-01
Figure 18
C501-1E OTP Memory Program/Read Cycle
MCT03237
Programming
Address
Data
Data
Address
t
DVGL
t
AVGL
t
GLGH
t
SHGL
t
EHSH
t
ELQV
t
EHQZ
t
GHSL
t
GHGL
t
GHAX
t
GHDX
t
AVQV
Verification
Logic 1
Logic 0
P1.0 - P1.7
P2.0 - P2.4
Port 0
ALE/PROG
EA/
P2.7
ENABLE
PP
V
Semiconductor Group
45
1997-04-01
C501
Figure 19
AC Testing: Input, Output Waveforms
Figure 20
AC Testing: Float Waveforms
Figure 21
Recommended Oscillator Circuits
0.45 V
V
CC
0.2
-0.1
+0.9
0.2
CC
V
Test Points
MCT00039
V
CC
-0.5 V
AC Inputs during testing are driven at
V
CC
0.5 V for a logic `1' and 0.45 V for a logic `0'. Timing
measurements are made at
V
IHmin
for a logic `1' and
V
ILmax
for a logic `0'.
MCT00038
V
Load
V
Load
-0.1 V
+0.1 V
Load
V
Timing Reference
Points
V
OH
-0.1 V
+0.1 V
OL
V
For timing purposes a port pin is no longer floating when a 100 mV change from load voltage
occurs and begins to float when a 100 mV change from the loaded
V
OH
/
V
OL
level occurs.
I
OL
/
I
OH
20 mA.
MCS02452
XTAL1
XTAL2
XTAL2
XTAL1
Crystal Oscillator Mode
Driving from External Source
External Oscillator
Signal
N.C.
20 pF
3.5 - 40 MHz
C =
pF
10
(incl. stray capacitance)
P-LCC-44/Pin 20
P-DIP-40/Pin 18
M-QFP-44/Pin 14
M-QFP-44/Pin 15
P-DIP-40/Pin 19
P-LCC-44/Pin 21
M-QFP-44/Pin 14
P-DIP-40/Pin 18
P-LCC-44/Pin 20
P-LCC-44/Pin 21
P-DIP-40/Pin 19
M-QFP-44/Pin 15
C
C
Note: During programming and verification of the C501-1E OTP memory
a clock signal of 4-6 MHz must be applied to the device.
C501
Semiconductor Group
46
1997-04-01
Package Outlines
Figure 22
P-DIP-40 Package Outlines
Plastic Package, P-DIP-40 for C501G-L / C501G-1R
(Plastic Dual in-Line Package)
GPD05883
Sorts of Packing
Package outlines for tubes, trays etc. are contained in our
Data Book "Package Information"
Dimensions in mm
Semiconductor Group
47
1997-04-01
C501
Figure 23
P-LCC-44 Package Outlines
GPL05882
Plastic Package, P-LCC-44 SMD for C501G-L / C501G-1R / C501G-1E
(Plastic Leaded Chip-Carrier)
Sorts of Packing
Package outlines for tubes, trays etc. are contained in our
Data Book "Package Information"
Dimensions in mm
SMD = Surface Mounted Device
C501
Semiconductor Group
48
1997-04-01
Figure 24
P-MQFP-44 Package Outlines
GPM05957
Plastic Package, P-MQFP-44 SMD for C501G-L / C501G-1R
(Plastic Metric Quad Flat Package)
Sorts of Packing
Package outlines for tubes, trays etc. are contained in our
Data Book "Package Information"
Dimensions in mm
SMD = Surface Mounted Device