Functional Description

The CMOS device SDA 9290-6 is a picture processor and belongs to a family of devices
forming an extended third-generation digital TV signal-processing system for enhanced
picture quality with special functions (Featurebox). Besides the Picture Processor (PP)
that is described here, the system consists of a field memory (at least three triple-port,
1-Mbit generation TV Sequential-Access Memory devices (SDA 9251 X), a Memory
Sync Controller (MSC SDA 9220-5) and a Display Prozessor (SDA 9280). A block
diagram of the Featurebox is shown in figure 4.

The Picture Processor SDA 9290-6 is a follow-on development of the Picture Processor
SDA 9290-5. Modifications of the movement detector and the recursive filters permits
further picture improvement by reducing the video noise and cross-color interference.
The SDA 9290-6 can be set independently at the picture-signal input and output via the
two pins FSBQ/FSI to the 4:1:1 and 4:2:2 formats. A 4:1:1 Featurebox (3 TV-SAMs) can
therefore be operated with 4:2:2 input signals as well.

Type

Ordering Code

Package

SDA 9290-6

Q67101-H5193

P-LCC-68-1 (SMD)

Picture Processor

Preliminary Data

CMOS IC

SDA 9290-6

P-LCC-68-1

Features

· Noise and cross color reduction by field - or frame

recursive filtering

· Adjustment of degree of noise reduction
· Automatic adaption to signal quality during vertical

blanking

· Pixel adaptive movement detection
· Split screen modes for demonstration purposes
· Multi-picture facilities
· Picture decimation using vertical filtering
· 8 programmable grey levels for framing
· 4:1:1 and 4:2:2 (Y:U:V) compatibility
· 8-bit word size for all components
· IIC-Bus programming of the video line for S/N

measurement in automatic adaption mode

· Optimized characteristics of the recursive filters

Semiconductor Group

1997-07-22

SDA 9290-6

Semiconductor Group

1997-07-22

The necessary decimation and interpolation operations are activated automatically
when the format is set. Together with a corresponding Memory Sync Controller
(SDA 9220) it enables functions like multi-picture, tuner scanning, picture-in-still and
still-in-picture. The different modes can be activated by a microcontroller on the

C-Bus

interface (slave receiver). The

C-Bus address for accessing the device is

Circuit Description

The core of the picture processor (see block diagram) is formed of the Image-lmproving
Processor (IIP) and the Multi-Picture Processor (MPP). The IIP is responsible for noise
and cross-color reduction, while the MPP together with the new Memory Sync Controller
implements the functions multi-picture, tuner scanning, picture-in-still and still-in-picture.

Image-lmproving Processor

The signal inputs Yl0-YI7 and UVI0-UVI7 and the back-channel signal inputs YB0-YB7
and UVB0-UVB7 picture data with 12 bits in quasi-parallel format (4:1:1) and with 16 bits
in parallel format (4:2:2). The clock rate for both signals is 13.5 MHz. For signal
processing in the IIP and MPP the chrominance bit levels have to be separated in the
case of the quasi parallel format by demultiplexers DEMUXS and DEMUXR, these being
largely identical in design.

A reduction in video noise is achieved by correlating the picture contents of two
successive fields, the non-correlated components (noise) being attenuated by the digital
filter. To achieve this, the instantaneous digital picture signal on the outputs of the
demultiplexer DEMUXS and the picture signal delayed by a field interval on the outputs
of the back-channel demultiplexer DEMUXR are fed to the IIP and combined.

The signal-to-noise ratio (

S/N

) unit detects the noise components of the input signals and

the movement detector uses this information to select an appropriate set of parameters
with filter coefficients and thresholds for the comparators. For this purpose the
luminance signal is assigned to one of three classes according to its

S/N

ratio, with each

class defining a different degree of maximum noise reduction. The limits between the
middle class and the upper and lower classes can be programmed by the

C-Bus

registers R1 and R2 with the values for the thresholds SU and SL. When the picture
signals come from a video cassette recorder, the adaptation on the

S/N

ratio of the input

signal should be disabled by

L-Bus register R0, VCR bit D2.

Measurement of the signal-to-noise ratio in the automatic mode has been advanced
from line 6 to line 4 in order to avoid conflicts with future text and data services.

The degree of noise reduction for the luminance and chrominance signals can be varied
between 0 dB and 12 dB by selecting the appropriate filter coefficients.

SDA 9290-6

Semiconductor Group

1997-07-22

A picture signal with reduced noise and cross-color appears on the output of the IIP for
further processing. The signal will be forwarded via blocks MUXI and MUXO to the
picture memories through the outputs (YQ0-YQ7 and UVQO-UVQ7 respectively).

The coefficients of the selected class are controlled by the movement detector as a
function of pixels to prevent artifacts (loss of focus) in moving parts of the picture. The
video line for S/N measurement can be programmed by the

C-Bus register R2 (D7-D5).

Multi-Picture Processor

Signals are processed in the 4:1:1 format. The vertical-decimation line memory again
operates with 208 pixels per line to adapt the 1/9th picture format to the new picture
memory with TV-SAMs. Gray frame generation is similarly affected by this change in
pixel value.

The signal processing in the decimation filter of the MPP reduces the picture to
approximately 1/9th of its original size. This produces a basis for new features, the full
implementation of which calls for a matching MSC (SDA 9220).

Figure 8 shows how the screen is divided up. The following modes can be implemented
with the MPP:

1. Multi-Picture (automatic)

Fields are extracted from a sequence of movements at fixed intervals, reduced and
reproduced on the screen as a sequence of stills. At one position it is possible to show
a moving picture.

2. Multi-Picture (manual)

This differs from the above in that the viewer can determine at the push of a button
what phases of movement are to be stored.

3. Multi-Picture (tuner scanning)

The pictures of the sequence of stills are derived from the different TV channels and
give an overview of the programs on offer. In this mode the picture memory is
operated with a crystal-controlled clock to ensure that the picture remains stable when
switching from one channel to another.

4. Still-in-Picture

A field is extracted from the on-going program, reduced and inserted as a still in the
master channel.

5. Picture-in-Still

The on-going program is inserted as a reduced-size moving picture in a still.

The framing block that follows the decimation filter in the MPP permits frames to be
inserted in order to border the reduced-size pictures on the screen. The brightness of the
framing can be varied in eight steps by the

C Bus.

The format conversion produced in the demultiplexers for signal processing in the IIP
and MPP is reversed again in the multiplexer MUXO. The picture signal appears again
in quasi-parallel format or parallel format on the output of the MUXO block. The inputs
of the TV-SAMs are directly driven by the sixteen outputs YQ0-YQ7 and UVQ0-UVQ7.

SDA 9290-6

Semiconductor Group

1997-07-22

C Bus Interface

C Bus interface configured as a "slave receiver" is used for programming the different functions

and modes of the picture processor. Via this interface up to four registers can be written according
to the following transfer protocol for controlling the operation mode:

S: Start condition
A: Acknowledge
P: Stop condition
Slave address: 0 0 1 0 1 0 1

(Note: There is a general description of the

C Bus in the Siemens publication "

C Bus Technical

Description".)

After every data byte that is transmitted the internal register address (subaddress) is automatically
incremented to the next register so that, if necessary, several registers can be loaded with one

Bus telegram.

In the multi-picture mode the operating mode transmitted on the

C Bus is switched within the

vertical blanking interval, i.e. during the high phase of signal VS1, if the Memory Sync Controller
(MSC) activates the DREQ line during this period.

It should be noted that the new operating mode has always to be transmitted to the picture
processor first and immediately afterwards to the MSC on the

C Bus at an interval not longer than

30 ms.

This is the only way to ensure interference-free synchronization of the picture processor and the
MSC. The four

C Bus registers are described below in more detail. The values marked "*D" in the

right-hand margin are set by an internally generated reset signal (default values) when the
operating voltage is applied.

Register Sub-

address

Data Byte

VCR

SUV8

YF5

YF4

YF3

SL4

SL3

SL2

SL1

SL0

LINE2

LINE1

LINE0

SU4

SU3

SU2

SU1

SU0

SNTEN SNT1

SNT0

KTEN

KT3

KT2

KT1

KT0

0 A

A P

Slave Address

Sub Address

Data Byte

SDA 9290-6

Semiconductor Group

1997-07-22

This control register sets the threshold SU for S/N adaptation, and the
values for the line counter.

Bits D7-D5:

Bits D4-D0: Threshold SU

(S/N adaptation)

SU4

SU3

SU2

SU1

SU0

:
:

Noise Measurement: Decoded Values of the Line Counter

LINE2

LINE1

LINE0

Decoded
Value

SDA 9290-6

Semiconductor Group

1997-07-22

Note: X is ignored.

*D = Default values after reset.

This register is for testing. certain S/N classes and filter coefficients for the
motion detector can be firmly set.

Bits D7-D5: S/N Class

SNTEN

SNT1

SNT0

Automatic adaptation

Class 0

Class 1

Class 2

Bits D4-D0: Filter Coefficient

KTEN

KT3

KT2

KT1

KT0

Motion detector ON

K = 1

K = 3/4

K = 5/8

K = 9/16

K = 3/4

K = 1/2

K = 3/8

K = 5/16

K = 5/8

K = 3/8

K = 1/4

K = 3/16

K = 9/16

K = 5/16

K = 3/16

K = 1/8

SDA

9290-6

Semiconductor Group

1997-07-22

Figure 2

Block Diagram

"1"

"0"

YI,
UIVI

MUXI

MUXO

UIIVII

YII,

IIP

Recursive

Filters

Movement

Detector

K0,K1

S1,S2

ROM

"S / N"

Measure

ment

KUV

DEMUXS

4:1:1

Decimation

Decimation-

Filters

Line Memory

Interpolator

4:2:2

Framing

MPP

YIM,
UIMVIM

DEMUXR

YS,
USVS

URVR

Generation

Clock

Signals

Control-

Receiver

C Bus

UVI

DREQ
LL3X

BLN
VS1
LLIN
LLSEL
FSI
FSBQ
SDA
SCL

UVB

UVO

UEB09850

GND

SDA 9290-6

Semiconductor Group

1997-07-22

Figure 3
Pin Configuration (top view)

SDA 9290-6

N.C.

SPEN

CLKEN

FSI

FSBQ

VS1

SDA

SCL

LL3X

LLSEL

LLIN

BLN

UVB0

UVB1

UVB2

UVB3

UVB4

UVB5

UVB6

UVB7

YB0

YB1

YB2

YB3

YB4

YB5

YB6

YB7

YI1

YI5

DREQ

YI7

YI6

YI4

YI3

YI2

YI0

UVI7

UVI6

UVI5

UVI4

UVI3

UVI2

UVI1

UVI0

YQ0

YQ4

YQ7

YQ6

YQ5

YQ3

YQ2

YQ1

UVQ7

UVQ6

UVQ5

UVQ4

UVQ3

UVQ2

UVQ1

UVQ0

27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43

68 67

65 64

UEP09851

GND

SDA 9290-6

Semiconductor Group

1997-07-22

Pin Definitions and Functions

Pin No. Symbol

Function

Description

Positive supply
voltage (+ 5 V)

Positive supply voltage (+ 5 V)

2-9

UVQ7 ...
UVQ0

Data outputs

Push-pull outputs for directly driving the TV-SAM
chrominance inputs:
8 bits for 4:2:2 format;
4 bits for 4:1:1 format;
[UVQ0 ... UVQ3 only valid for 4:2:2 format]

GND

Ground

Ground (0 V)

11-18

UVB0 ...
UVB7

Back-channel
data outputs

Back-channel inputs for chrominance data from TV-SAM

19-26

YB0 ...
YB7

Back- channel
data inputs

Back-channel inputs for luminance data from TV-SAM

27-34

UVI0 ...
UVI7

Data inputs

Data inputs for chrominance data accept the dig. YUV
signal

35-42

YI0 ...
YI7

Data inputs

Data inputs for luminance data accept the dig. YUV
signal

DREQ

Data request
signal for multi-
picture mode

Data-request input; initiates data transfer in multi-picture
mode and switches mode together with signal VS1

GND

Ground

Ground (0 V)

BLN

Blanking signal
(15.625 kHz)

Input for line-synchronous blanking signal that
determines line blanking interval (active low) and
synchronizes clock and sequence control

LLIN

First system clock
(13.5 MHz)

Input for line-locked system clock, 13.5 MHz, from which
internal timing is derived. Positive edge indicates validity
of input data

LLSEL

none

Must be connected to

(high-level)

LL3X

Second system
clock (13.5 MHz)

Input for line-locked 13.5-MHz clock that ensured picture
stability in multi-picture mode and is used as output clock
in every mode

SCL

C Bus shift clock

input

C-Bus shift-clock input

SDA

C Bus data

input/output

C-Bus data input/output

VS1

Vertical sync input
(50 Hz)

Vertical sync input; determines vertical position of TV
picture for 50-Hz or 60-Hz field frequency

Positive supply
voltage (+ 5 V)

Positive supply voltage (+ 5 V)

SDA 9290-6

Semiconductor Group

1997-07-22

FSBQ

Selection of output
format

Switching of data output format:
Low level for 4:1:1 format; high level for 4:2:2 format

FSI

Selection of input
format

Switching of data input format: Low level for 4:1:1 format;
high level for 4:2:2 format

CLKEN

Connect test pin 2

Has to be grounded (0 V) in normal mode

SPEN

Connect test pin 2

Has to be grounded (0 V) in normal mode

57-59

N.C.

Reserved

No connections possible or meaningful

GND

Ground

Ground (0 V)

61-68

YQ7 ...
YQ0

Data outputs

Push-pull outputs for directly driving TV-SAM inputs for
4:1:1 and 4:2:2 modes; (8-bit luminance)

Pin Definitions and Functions (cont'd)

Pin No. Symbol

Function

Description

SDA 9290-6

Semiconductor Group

1997-07-22

Electrical Characteristics

Note: Stresses above those listed here may cause permanent damage to the device.

Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
Maximum ratings are absolute ratings; exceeding only one of these values may
cause irreversible damage to the integrated circuit.

Note: In the operating range the functions given in the circuit description are fulfilled.

Absolute Maximum Ratings
(all voltages are referred to GND)

Parameter

Symbol

Limit Values

Unit

Remarks

min.

max.

Ambient temperature

Storage temperature

stg

125

Total power dissipation

tot

Supply voltage

0.3

Input/output voltage

I/Q

0.3

Thermal resistance system-air

th SA

K/W

with heat
sink

Operating Range

Supply voltage

4.5

5.5

Supply current

180

Ambient temperature

SDA 9290-6

Semiconductor Group

1997-07-22

Characteristics
(all voltages are referred to GND)

Parameter

Symbol

Limit Values

Unit

Test Condition

min.

typ.

max.

H-input voltage

2.0

5.5

L-input voltage

0.8

Input current

Input capacitance

(except BLN, LLIN)

Input capacitance

(only BLN, LLIN)

H-input voltage

3.0

5.5

L-input voltage

0.8

Input capacitance

Input current

H-output voltage

2.4

= 2.0 mA

L-output voltage

0.4

= 3.0 mA

L-output voltage

0.4

= 3.0 mA

Permissible output voltage

5.5

Input signals UVI0 ... UVI7, YI0 ... YI7, UVB0 ... UVB7, YB0 ... YB7, BLN, LLSEL, FSI, FSBQ, LLIN, LL3X,
DREQ, VS1

Input signals SDA, SCL (refer to figure 6)

Output signals YQ0-YQ7, UVQ0-UVQ7

Output signal SDA (open drain)

SDA 9290-6

Semiconductor Group

1997-07-22

Input Clock LL3X = 13.5 MHz (refer to figure 6)

Cycle

LLL3X

Fall time

THL

Rise time

THL

H-pulse width

L-pulse width

Change in rel to LLIN

Input Clock LLIN (refer to figure 6)

Cycle

LLIN

LLSEL = high

H-pulse width

LLSEL = high

L-pulse width

LLSEL = high

Fall time

THL

Rise time

THL

Input Clock BLN (refer to figure 5)

Setup time

LLSEL = high

Hold time

LLSEL = high

H-pulse width

720

LL3X

Cycle, 625 lines

BLN

864

LL3X

Cycle, 525 lines

BLN

858

LL3X

Characteristics (cont'd)
(all voltages are referred to GND)

Parameter

Symbol

Limit Values

Unit

Test Condition

min.

typ.

max.

SDA 9290-6

Semiconductor Group

1997-07-22

Input Signal VS1

Setup time

Reference
LL3X

Hold time

Reference
LL3X

Cycle, 625 lines

VS1

312.5

BLN

Cycle, 525 lines

VS1

262.5

BLN

H-pulse width, 625 lines

26.5

BLN

H-pulse width, 525 lines

16.5

BLN

Input Signal DREQ

Setup time

Reference
LL3X

Hold time

Reference
LL3X

H-pulse width

LL3X

Input Signal (Data) YI0 ... YI7, UVI0 ... UVI7, YB0 ... YB7, UVB0 ... UVB7
(refer to figure 5)

Setup time

Reference
LL3X

Hold time

Reference
LL3X

Setup time

Reference LLIN

Hold time

Reference LLIN

Characteristics (cont'd)
(all voltages are referred to GND)

Parameter

Symbol

Limit Values

Unit

Test Condition

min.

typ.

max.

SDA 9290-6

Semiconductor Group

1997-07-22

Note: The listed characteristics are ensured over the operating range of the integrated

circuit. Typical characteristics specify mean values expected over the production
spread. If not otherwise specified, typical characteristics apply at

= 25

C and

the given supply voltage.

Output Signal (Data) YQ0 ... YQ7, UVQ0 ... UVQ7 (refer to figure 5)

Hold time

Reference
LL3X

Delay time

Reference
LL3X

= 30 pF

Characteristics (cont'd)
(all voltages are referred to GND)

Parameter

Symbol

Limit Values

Unit

Test Condition

min.

typ.

max.

SDA

9290-6

Semiconductor Group

1997-07-22

Figure 4

Application Circuit

(simplified)

13.5 MHz

SCB WT

RB SAC SAR SCAD RE RA SCA

27 MHz

DREQ

VS1

LLSEL

BLN LLIN

LL3X

UVB

UVQ

FSBQ

UVI

FSI

SCL

SDA

PP II

SDA 9290-6

3 x TV-SAM

SDA 9251-2X

SDA 9280

OEB

SDC

SQB

OEA

SQA

SAR

LL3X

SAC

SCA

SCAD

DREQ

VS1

BLN

LLIN

LLSEL

CFH

WEI

MUX

DDA

SCL

SDA

RESO

RESI

RST

OSCO

OSCI

B-Y

YI
UVI

SCA

CLL

BLN

SDA

SCL

LL1.5X

FRM

VS2

HS2

CSY

BLN

LL3

CFH

UES09852

ADR

CSY

HS2

VS2

FRM

BLN2

LL1.5X

SDA 9220-5

MSC III

-( )

R-Y

13.5 MHz

GND

SDA 9290-6

Semiconductor Group

1997-07-22

Figure 7
Timing for

C Bus

Table 1

All values are referred to specified input levels

and

Parameter

Symbol

Limit Values

Unit

min.

max.

Clock frequency

SCL

100

kHz

Inactive time before start of new transmission

BUF

4.7

Hold time for start condition
(after this time first clock pulse is generated)

HD; STA

4.0

Low clock phase

LOW

4.7

High clock phase

HIGH

4.0

Setup time for data

SU; DAT

250

Rise time for SDA and SCL signals

TLH

Fall time for SDA and SCL signals

THL

300

Setup time for SCL clock in stop condition

SU; STO

4.7

UET00130

BUF

HD, STA

LOW

TLH

Stop

Start

Stop

THL

HIGH

HD, DAT

SU, DAT

SU, STO

SDA

SCL

SDA 9290-6

Semiconductor Group

1997-07-22

Y: Luminance Signal
U: Chrominance Signal
V: Chrominance Signal

Table 2
Assignment of Signal and Pin Names

Format 4:1:1

Y:7-Bit Signal

Y:8-Bit Signal

Picture Processor

Input

Back

Channel

Input

Output

YI7

YB7

YQ7

YI6

YB6

YQ6

YI5

YB5

YQ5

YI4

YB4

YQ4

YI3

YB3

YQ3

YI2

YB2

YQ2

YI1

YB1

YQ1

YI0

YB0

YQ0

U6 U4 U2 U0

U7 U5 U3 U1

UVI7

UVB7

UVQ7

U5 U3 U1

U6 U4 U2 U0

UVI6

UVB6

UVQ6

V6 V4 V2 V0

V7 V5 V3 V1

UVI5

UVB5

UVQ5

V5 V3 V1

V6 V4 V2 V0

UVI4

UVB4

UVQ4

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