EDGE HIGH-PERFORMANCE PRODUCTS
1
www.semtech.com
Edge710
500 MHz Pin Electronics Driver,
Window Comparator, and Load
Description
Features
Functional Block Diagram
Applications
Revision 2 / December 1, 2000
The Edge710 is a totally monolithic ATE pin electronics
solution manufactured in a high-performance
complementary bipolar process. In Automatic Test
Equipment (ATE) applications, the Edge710 incorporates
a driver, a load, and a window comparator suitable for
very fast bidirectional channels in VLSI, Mixed-Signal, and
Memory test systems.
The three-statable driver is capable of generating 9V swings
over a 12V range. In addition, 13V super voltage may be
obtained under certain operating conditions. Separate
rise and fall edge adjustments support both high speed
and low speed applications, and allow for superior rise
and fall time matching. An input power down mode allows
extremely low leakage current in HiZ.
The load supports programmable source and sink currents
of
35 mA over a 12V range, or it can be completely
disabled. The source current, sink current, and
commutating voltage are all independently set. In addition,
the load is configurable and may be used as a
programmable voltage clamp.
The window comparator spans a 12V common mode
range, tracks input signals with edge rates greater than 6
V/ns, and passes sub-ns pulses. An input power down
mode allows for extremely low leakage measurements.
The inclusion of all pin electronics building blocks into a
52 lead MQFP (10 mm body w/ internal heat spreader)
offers a highly integrated solution that is traditionally
implemented with multiple integrated circuits or discretes.
Fully Integrated Three-Statable Driver, Window
Comparator, and Dynamic Active Load
12V Driver, Load, Compare Range
13V Super Voltage Capable
35 mA Programmable Load
Comparator Input Tracking >6V/ns
Leakage (L+D+C) < 1
A (normal mode)
Leakage (L+D+C) < 25 nA (IPD mode)
Small footprint (52 pin MQFP)
VLSI Test Equipment
Mixed-Signal Test Equipment
Memory Testers (Bidirectional Channels)
ASIC Verifiers
BIAS
DVH
DHI
DHI*
DVR_EN
DVR_EN*
DVL
IPD_D
QA*
QA
PECL
IPD_C
QB
QB*
ISC_IN
VCM_IN
VCM_OUT_A
VCM_OUT_B
ISK_IN
LD_EN
LD_EN*
RADJ
DOUT
FADJ
CVA
VINP
CVB
BRIDGE_SC
LOAD
BRIDGE_SK
1K
1K
VCC
VEE
2
2000 Semtech Corp.
www.semtech.com
EDGE HIGH-PERFORMANCE PRODUCTS
Edge710
PIN Description
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3
2000 Semtech Corp.
www.semtech.com
EDGE HIGH-PERFORMANCE PRODUCTS
Edge710
PIN Description (continued)
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52 MQFP
10 mm X 10 mm
Top Side
BRIDGE_SK
LOAD
GND
GND
IPD_C
IPD_D
VINP
VCC
VCC
DOUT
VEE
VEE
CATHODE
VEE
LD_EN
LD_EN*
VCC
QA*
QA
PECL
PECL
GND
QB
QB*
DHI
DHI*
VEE
CVB
CV
A
VCC
ISC_IN
GND
GND
ISK_IN
VCM_IN
VCM_CAP
VCM_OUT_A
VCM_OUT_B
BRIDGE_SC
D
VR_EN
D
VR_EN*
F
ADJ
RADJ
BIAS
DV
L
DV
H
GND
GND
N/C
D
VH_CAP
D
VL_CAP
ANODE
4
2000 Semtech Corp.
www.semtech.com
EDGE HIGH-PERFORMANCE PRODUCTS
Edge710
Circuit Description
Driver
Introduction
The driver will force DOUT to one of three states:
1. DVH (Drive High)
2. DVL (Drive Low)
3. HiZ (High Impedance).
Both driver digital control inputs (DHI / DHI*, DRV_EN /
DRV_EN*) are "Flex Inputs" - wide voltage differential inputs
capable of receiving ECL, TTL, CMOS, or custom level
signals. Single-ended operation is supported by
connecting the inverting input to the appropriate DC
threshold level.
Drive Enable
The drive enable (DRV_EN / DRV_EN*) inputs control
whether the driver is forcing a voltage, or is placed in a
high-impedance state. If DRV_EN is more positive than
DRV_EN*, the output will force either DVH or DVL,
depending on the driver data input. If DRV_EN is more
negative that DRV_EN*, the output goes into a high
impedance state.
Do NOT leave DRV_EN / DRV_EN* floating.
Driver Data
The driver data inputs (DHI / DHI*) determine whether the
driver output is forcing a high or a low. If DHI is more
positive than DHI*, the driver will force DVH when the
driver is active. If DHI is more negative than DHI*, the
driver will force DVL when active.
Do NOT leave DHI / DHI* floating.
Table 1. Driver Control Truth Table
Driver Levels
DVH and DVL are high input impedance voltage controlled
inputs which establish the driver levels of a logical "1" and
"0" respectively.
Driver Level Buffer Compensation
DVH_CAP and DVL_CAP are op amp compensation pins
for the high and low level on-chip buffers. Each pin requires
a 0.01
F chip capacitor (with good high frequency
characteristics) connected to ground. A tight layout with
minimal distance between the pin and the capacitor is
recommended.
Driver Bias
The BIAS pin is an analog current input which establishes
an on-chip bias current, from which other currents are
generated. This current, to some degree, also establishes
the overall power consumption and performance of the
chip. Ideally, an external current source would be used to
minimize any part-to-part performance variation within a
test system. However, a precision external resistor tied to
a large positive voltage is acceptable. (See figure below.)
The optimal BIAS current is a function of the RADJ and
FADJ settings, and cannot be set independently.
The established bias current follows the equation:
BIAS = (VCC - 0.7) / (Rext + 1.5).
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1.5K
REXT
BIAS
VCC
VEE
5
2000 Semtech Corp.
www.semtech.com
EDGE HIGH-PERFORMANCE PRODUCTS
Edge710
Circuit Description (continued)
Driver Slew Rate Adjustment
The driver rising and falling transition times are
independently adjustable. The RADJ and FADJ pins are
analog current inputs which establish the driver rise and
fall times.
Ideally, an external current source would be used for RADJ
and FADJ. However, for most applications (where the rise
and fall times are fixed), precision external resistors to a
positive voltage are acceptable. The currents into RADJ
and FADJ follow the equation:
RADJ, FADJ = (VCC - 0.7) / (Rext + 1.5).
Input Power Down
IPD_D is a TTL compatible input which affects both the
driver speed as well as high impedance leakage. With
IPD_D = 0, the driver functions normally. With IPD_D =
1, the driver is in IPD mode, where it still functions,
although with slower rise and fall times, but with an
extremely low HiZ leakage current.
Do not leave IPD_D floating !! If IPD_D is not used,
connect it to ground.
LOAD > VCM_IN
1.5K
Rise/Fall
Adjust Current
RADJ (FADJ)
Load
The load is capable of sourcing and sinking at least 35
mA dynamically, or being placed into a high impedance
state. The load may also be configured with separate
commutating voltage to act as a programmable voltage
clamp. In addition, the load may act as a 50
transmission line termination.
Load Enable
The load enable input determines whether the load is active
or in high impedance. If LD_EN is more positive than
LD_EN*, the load is active and is capable of sourcing and
sinking currents. If LD_EN is more negative than LD_EN*,
the load is placed into a high impedance state.
LD_EN / LD_EN* are "Flex In" - wide voltage differential
inputs capable of receiving ECL, TTL, CMOS, or custom
levels. Single-ended operation is supported by connecting
the inverting input to the appropriate DC threshold level.
Do NOT leave LD_EN / LD_EN* floating.
Commutating Voltage
VCM_IN is a high input impedance analog voltage input
which sets the commutating voltage of the load. If LOAD
is more positive than VCM_IN, the bridge will sink current
from the DUT into the load. If LOAD is more negative than
VCM_IN, the load will source current from the load into
the DUT.
LOAD < VCM_IN
VCM_IN
DUT
VCM_IN
DUT
6
2000 Semtech Corp.
www.semtech.com
EDGE HIGH-PERFORMANCE PRODUCTS
Edge710
Circuit Description (continued)
Source and Sink Current Levels
The amount of current that the diode bridge can source
and sink is adjustable from 0 mA to 35 mA. The source
and sink levels are separate and independent.
ISC_IN and ISK_IN are current controlled inputs whose
voltage level is held very close to ground (<100 mV
variation) over the entire legal current input range.
There is a nominal gain of 20 between the ISC_IN current
and the bridge source current.
ISOURCE = 20 * ISC_IN
There is a nominal gain of 20 between the ISK_IN current
and the bridge sink current.
ISINK = 20 * ISK_IN
Because the inversion creates a 180 phase shift between
ISK_IN and ISINK, there is a tendency toward instability.
A minimum of 500 W of external series resistance should
be used between an external voltage or current source
and the ISC_IN and ISK_IN pins to ensure stability. Stray
capacitance at the ISK_IN pin should be kept to a
minimum. PCB layout should minimize coupling between
ISK_IN and LOAD.
Caution: The ISKIN and ISCIN inputs are designed for
positive current between 0 mA and 1.75 mA flowing into
the part. Care should be taken to insure that current is
never required to flow out of the part on these two nodes.
Commutating Voltage Compensation
The VCM_CAP pin is an op amp compensation node that
requires a fixed .01
F chip capacitor (with good high
frequency characteristics) to ground. This capacitor is
used to compensate an internal node on the on-chip buffer
for the commutating voltage input.
Split Load
The VCM_OUT_A is the actual commutating voltage
generated by the on-chip buffer. VCM_OUT_A is also
connected to the upper half of the diode bridge, and is
responsible for sinking the programmed source current
when the load is sinking current from the DUT.
VCM_OUT_B is connected to the lower half of the diode
bridge, and is responsible for providing the sink current
when the load is sourcing current to the DUT.
VCM_OUT_B does NOT have an on-chip buffer. To
configure the load as a standard active diode bridge,
connect VCM_OUT_A and VCM_OUT_B together off-chip.
Or, to configure the load as a split load, an external buffer
must be used for VCM_OUT_B.
External Bridge Connections
Access to the top and bottom of the diode bridge is granted
through a 1 KW resistor. Pins BRIDGE_SC and BRIDGE_SK
allow external current sources to be used instead of the
internal I_SOURCE and I_SINK sources. These external
pins are useful when extremely accurate source and sink
currents are required for low current operation.
1K
1K
BRIDGE_SC
I_SOURCE
I_SINK
LOAD
BRIDGE_SK
VCM_OUT_B
VCM_OUT_A
VCM_IN
7
2000 Semtech Corp.
www.semtech.com
EDGE HIGH-PERFORMANCE PRODUCTS
Edge710
Circuit Description (continued)
Window Comparator
Two comparators are connected on-chip to form a window
comparator to determine whether the DUT is high, low, or
in an indeterminant state. VINP is tied to the positive
inputs of both comparators.
The selection of either comparator A or B for the DUT high
versus the DUT low is arbitrary. However, because the
positive input is used on both comparators, the comparator
used to detect DUT low will have an inversion at it digital
outputs.
The figure below shows the correct polarity for the
comparator connections.
Thresholds
CVA and CVB are the two comparator threshold levels.
These inputs are high impedance voltage controlled inputs
that determine at which VINP voltage the comparators
will change output states.
PECL Level Capability
PECL is the power supply level for the output stage of the
comparators. When connected to ground, the comparator
outputs will be standard ECL outputs. However, by making
PECL more positive, QA / QA* and QB / QB* will track
PECL and also become more positive.
By raising these voltage levels, the comparators may
connect directly with CMOS ICs.
QA*
QA
QB
QB*
IPD_C
PECL
CVA
VINP
CVB
The power supply driving the PECL pin must be capable of
sourcing all the current flowing out of the QA/QA* and QB/
QB* open emitter outputs.
Comparator Input Protection
VINP connect to over-voltage diodes connected to the
positive and negative power supplies. These diodes are
sized to handle up to 100 mA current.
Thermal Monitor
An on-chip thermal diode string of five diodes in series
exists (see figure below). This string allows accurate die
temperature measurements.
An external bias current of 100
A is injected through the
string, and the measured voltage corresponds to a specific
junction temperature with the following equation:
Tj[
C] = {(ANODE - CATHODE)/5 .7752} / (.0018).
ANODE
CATHODE
Temperature Coefficient = 9 mV / C
Bias Current
8
2000 Semtech Corp.
www.semtech.com
EDGE HIGH-PERFORMANCE PRODUCTS
Edge710
Application Information
Super Voltage Operation
The Edge710 may be used to generate a super voltage
level up to 13V at the driver output. To generate this high
voltage, an analog input mux may be used to switch
between the normal high and low drive levels, and a super
voltage level.
Certain Power Supply conditions must be met to support
this functionality.
Extremely Low Leakage Usage
The Edge710 is capable of supporting total load + drive
+ comparator leakage
~15 nA. This low leakage mode
may be very useful during PMU operation if the pin
electronics are not isolated by a relay, thus eliminating
the need for 1 relay per pin.
To realize this low leakage, the following conditions must
be met:
1. IPD_D = 1 (place the driver in "power down" mode)
2. IPD_C = 1 (place the comparator in "power down"
mode)
3. CVA, CVB
VINP (program the comparator
thresholds
any expected voltage at the comparator
inputs.)
DVH
DVL
S/V
S/V SELECT
710
D_OUT
A
B
Y
B
A
Y
9
2000 Semtech Corp.
www.semtech.com
EDGE HIGH-PERFORMANCE PRODUCTS
Edge710
Package Information
PIN Descriptions
4X
4
4
D
D
A
B
D2
3
3
3
0.25
C
A B
D
e
E
E2
SEE DETAIL "A"
TOP VIEW
D1
E1
5
7
5
7
5
2
7
Z
D
Z
E
4X
0.20
C
A B
D
C
O O
BOTTOM VIEW
10
2000 Semtech Corp.
www.semtech.com
EDGE HIGH-PERFORMANCE PRODUCTS
Edge710
Package Information (continued)
A, B, D
3
DETAIL "A"
e
A2
A1
0.13
R. MIN.
0.40 MIN.
0 MIN.
0 7
C
C
0.13 / 0.30 R.
L
1.60 REF.
GAGE PLANE
0.10 S
0.25
DETAIL "B"
12 16
1.41 REF.
SEE DETAIL "B"
12 16
A
H
C
2
0.076
8
0.13 / 0.23
0.13 / 0.17
12
BASE METAL
WITH LEAD FINISH
b
b
1
ccc
M
S
S
A B
D
C
SECTION C-C
Notes:
1.
All dimensions and tolerances conform to ANSI Y14.5-1982.
2.
Datum plane -H- located at mold parting line and coincident
with lead, where lead exits plastic body at bottom of parting
line.
3.
Datums A-B and -D- to be determined where centerline
between leads exits plastic body at datum plane -H-.
4.
To be determined at seating plane -C-.
5.
Dimensions D1 and E1 do not include mold protrusion.
Allowable mold protrusion is 0.254 mm per side.
Dimensions D1 and E1 do include mold mismatch and
are determined at datum plan -H-.
6.
"N" is the total # of terminals.
7.
Package top dimensions are smaller than bottom
dimensions by 0.20 mm, and top of package will not
overhang bottom of package.
8.
Dimension b does not include dambar protrusion.
Allowable dambar protrusion shall be 0.08 mm total in
excess of the b dimension at maximum material
condition. Dambar cannot be located on the lower
radius or the foot.
9.
All dimensions are in millimeters.
10.
Maximum allowable die thickness to be assembled
in this package family is 0.635 millimeters.
11.
This drawing conforms to JEDEC registered outline MS-108.
12.
These dimensions apply to the flat section of the lead
between 0.10 mm and 0.25 mm from the lead tip.
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0
JEDEC Variation
(all dimensions in millimeters)
11
2000 Semtech Corp.
www.semtech.com
EDGE HIGH-PERFORMANCE PRODUCTS
Edge710
Recommended Operating Conditions
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12
2000 Semtech Corp.
www.semtech.com
EDGE HIGH-PERFORMANCE PRODUCTS
Edge710
Absolute Maximum Ratings
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Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device.
This is a stress rating only, and functional operation of the device at these, or any other conditions beyond
those listed, is not implied. Exposure to absolute maximum conditions for extended periods may affect device
reliability.
13
2000 Semtech Corp.
www.semtech.com
EDGE HIGH-PERFORMANCE PRODUCTS
Edge710
DC Characteristics
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1
DC test conditions (unless otherwise specified): "Recommended Operating Conditions".
RADJ = FADJ = 1.1 mA. BIAS = .6 mA.
14
2000 Semtech Corp.
www.semtech.com
EDGE HIGH-PERFORMANCE PRODUCTS
Edge710
DC Characteristics (continued)
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m
DC test conditions (unless otherwise specified): "Recommended Operating Conditions".
RADJ = FADJ = 1.1 mA. BIAS = .6 mA.
Note 1: This parameter is guaranteed by characterization. It is tested in production against
100 mV
limits.
Note 2: Tested at PECL = 0V, PECL = +4V.
Note 3: No Load Conditions.
15
2000 Semtech Corp.
www.semtech.com
EDGE HIGH-PERFORMANCE PRODUCTS
Edge710
DC Characteristics (continued)
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Note 1:
This parameter is guaranteed by characterization. It is tested in production against
200 nA
limits.
Note 2:
Gain is computed from 2 points: DVH = 1V, +4V.
Note 3:
Gain is computed from 2 points: DVL = 1V, +4V.
16
2000 Semtech Corp.
www.semtech.com
EDGE HIGH-PERFORMANCE PRODUCTS
Edge710
AC Characteristics
r
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DC test conditions (unless otherwise specified): "Recommended Operating Conditions".
RADJ = FADJ = 1.1 mA. BIAS = .6 mA.
17
2000 Semtech Corp.
www.semtech.com
EDGE HIGH-PERFORMANCE PRODUCTS
Edge710
Ordering Information
Contact Information
Semtech Corporation
Edge High-Performance Division
10021 Willow Creek Rd., San Diego, CA 92131
Phone: (858)695-1808 FAX (858)695-2633
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