SB1000
PRODUCT BRIEF
Revision: 1.1
Silicon Bridge Inc.,
1
August 26, 2002
41688 Christy Street, Fremont, CA 94538 (510)-360-8888
SILICON BRIDGE
FEATURES
Compliant with IEEE 802.3ae 10Gbps Ethernet
XAUI specification
Integrated CMU, CDR, MUX/DMUX enabling oper-
ating range from 1 - 3.2Gbps
Integrated per-channel receive equalizer
Integrated per-channel transmit pre-emphasis
Flexible parallel interface configurable to be 10/20, or
XGMI bus
Single reference at 1/10 and 1/20 clock frequency
Support word alignment and comma detect
Integrated 8B/10B encoder/decoder with bypass
mode
FIFOs for XAUI channel alignment, and receive rate
matching
TX phase matching FIFO
Retimed repeater function support
Programmable through the MDIO interface
Programmable on chip termination resistors
Per-channel Built-In Self Test with PRBS generator/
checker and incremental patterns
Serial and parallel loopback
Per-channel power down mode
Single 1.8V supply
Power dissipation: 100mW per channel
Available in TSMC 0.18um CMOS technology
BENIFITS/ADVANTAGES
Low power
Integrated programmable pre-emphasis circuit which
opens up the transmitter eye at the end of a long PCB
traces or cable
Integrated equalization circuit which allows the re-
ceiver to recover clock and data over long PCB trace
or cable
Very low jitter generation < 5ps rms
Support both backplane and line card applications
Rich sets of control and monitor features
Rich sets of BIST features for device manufacturabil-
ity and reliability
Wide frequency range of operation
APPLICATIONS
10Gbps Ethernet XAUI to XGMII
Fiber Channel and Infiniband
10Gbps CWDM fiber optic module
10Gbps Backplane & interconnect
Test equipment
XAUI retimer
OC-48
Figure 1.0: Typical Application Diagram
3.125G
XCVR
SB1000
3.125G
XCVR
3.125G
XCVR
3.125G
XCVR
CWDM
Optical
Module
3.125G
XCVR
SB1000
3.125G
XCVR
3.125G
XCVR
3.125G
XCVR
RTL
CODE
CHASIS
4x3.125Gbps Backplane
XGMII
XGMII
4x3.125Gbps
LINE CARD
ASIC
3.125G
XCVR
SB1000
3.125G
XCVR
3.125G
XCVR
3.125G
XCVR
RTL
XGMII
CODE
ASIC
SB1000 Macro Cell
for backplane ASIC
SB1000 Macro Cell
for line card ASIC
SB1000 - Quad 1 - 3.125Gbps Low Power CMOS Trans-
ceiver Macro Cell in 0.18um TSMC Process
SB1000
PRODUCT BRIEF
Revision: 1.1
Silicon Bridge Inc.,
2
August 26, 2002
41688 Christy Street, Fremont, CA 94538 (510)-360-8888
SILICON BRIDGE
1.0 General Description
SB1000 is a feature-rich, programmable, high-performance transceiver macro cell which inte-
grates four channels of 3.125Gbps to reach an aggregate rates of up to 12.5Gbps. Each transceiv-
er port is capable of transmitting and receiving data rate from 1 to 3.125 Gbps. It is ideal for
10Gbps Ethernet, fibre channel, infiband, backplane, chip to chip interconnect, OC-48 and test
equipment applications.
The macro is highly integrated and consists of an on chip serializer, deserialzer, clock and data re-
covery (CDR), a transmit Phase Lock Loop (TXPLL), receive equalizer, clock synthesizer, 8B/10B
encoder/decoder, deskew FIFO, rate compensation FIFO, transmit FIFO, serial MDIO port, pro-
grammable pre-emphasis, termination resistors, equalizer, and BIST functions.
In the tranmsitter path, the SB1000 takes in an XGMII, or 10/20 bit interface and latches them into
the TX FIFO.The built-in FIFO compensates for phase matching between clocks. Before forward-
ing the data to the serializer to output as serial data streams, the parallel data could be optionally
decoded by the 10B/8B decoder depending on applications. Each deserializer which operates up
to 3.125Gbps, includes a programmable pre-emphasis circuit and programmable 50/60/75 termi-
nation resistors. The pre-emphasis circuit enables the device to open up the transmit eye as the
signal travels across a lossy PCB traces.
In the receiver path, the device receives serial NRZ data, performs signal equalization, clock and
data recovery, deserialzation, symbol alignment, channel alignment, rate compensation, and out-
puts it to the XGMII interface. The receive equalization circuit allows the receiver to recover the
data across long lossy PCB traces or cable. The deskew and rate compensation FIFOs provide
XAUI channel alignment and receive/transmit clock rate compensation, respectively. Furthermore,
the receiver provides a feature which retimes the recovered data and directly loop it to the trans-
mitter for the repeater or XAUI retimer application.
A rich sets of programmable features are accessed through MDIO interface. PRBS, incremental
patterns, serial forward/reverse, and parallel loopbacks are part of the built-in self test (BIST) of
the device.
CDR
8B/10B
TX
10B/8B
Serializer
PRBS
XGM
I
I
Interf
ace
XA
UI
I
n
terface
Channel 0
Channel 1
Channel 2
Channel 3
SB1010 Block Diagram
JTAG
SCAN
Power Down
MDIO I/F
MDIO Registers
TXPLL + Clock Synthesizer
XAUI State Machine
REFCLK+/-
RX
Equalizer
Decoder
FIFO
Checker
PRBS
Generator
Pre-emp.
Circuit
retimed mode
parallel loopback mode
serial loopback mode
TXDATA
TXCLK
RXDATA
RXCLK
RXI+/-
TXO+/-
Deserialzer
Encoder
Deskew/
Rate Comp
FIFOs
Bit
Alignment
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