TIME SLOT ASSIGNMENT CIRCUIT
S5T8555
1
INTRODUCTION
The S5T8555 is a per channel Time Slot Assignment Circuit (TSAC)
that produces 8-bit receive and transmit time slots for four 1 CHIP
CODEC.
Each frame synchronization pulse may be independently assigned
to a time slot in a frame of up to 64 time slots
FEATURES
Single, 5V operation
Low power consumption: 5mW
Controls four 1 CHIP CODEC
Independent transmit and receive frame syncs
channel unidirectional mode
Up to 64 time slots per frame
Compatible with S5T8554B/7B CODECs
TTL and CMOS compatible
ORDERING INFORMATION
Device
Package
Operating Temperature
S5T8555X01-L0B0
20
-
CERDIP
-
20
C to 125
C
20-CERDIP
S5T8555
TIME SLOT ASSIGNMENT CIRCUIT
2
PIN CONFIGURATION
GND
FS
X
3
CH0
CH1
RSY
C
/CH2
XSY
C
BCLK
FS
X
1
FS
R
1
FS
X
0
FS
R
0
TS
X
D
C
CLK
C
CS
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
KT8555
V
CC
FS
R
2
FS
X
2
FS
R
3
20
19
18
17
MODE
S5T8555
TIME SLOT ASSIGNMENT CIRCUIT
S5T8555
3
PIN DISCRIPTION
Pin No
Symbol
Description
3
1
18
16
FS
X
0
FS
X
1
FS
X
2
FS
X
3
A Transmit frame sync output which is normally low, and goes active-high for 8 cycles
of BCLK when a valid transmit time slot assignment is made.
4
2
19
17
FS
R
0
FS
R
1
FS
R
2
FS
R
3
A Receive frame sync output which is normally low, and goes active-high for 8 cycles
of BCLK when a valid receive time slot assignment is made.
5
TS
X
This pin pulls low during any active transmit time slot. (N-channel open drain)
6
D
C
The input for an 8 bit serial control word. X is the first bit clocked in.
7
CLK
C
The clock input for the control interface.
8
CS
The active-low chip select for the control interface.
9
MODE
Mode 1 = Open or V
CC
Mode 2 = Gnd
10
GND
Ground
11
BCLK
The bit clock input (2.048 MHz)
12
XSY
C
The transmit Time Slot Output sync pulse input. Must be synchronous with BCLK.
13
RSY
C
/CH2
The receive time slot sync pulse input. Must be synchronous with BCLK. In mode 1
this input is the receive time slot 0 sync pulse, RSY
C
, which must be synchronous
with BCLK. In mode 2 this is the CH2 input for the MSB of the channel select word.
14
CH1
The input for the NSB (next significant bit) of the channel select word.
15
CH0
The input for the LSB (last significant bit) of the channel select word, which defines
the frame sync output affected by the following control word.
20
V
CC
Power supply pin. 5V
5%
S5T8555
TIME SLOT ASSIGNMENT CIRCUIT
4
ABSOLUTE MAXIMUM RATING (Ta = 25
C)
Characteristic
Symbol
Value
Unit
Positive Supply Voltage
V
CC
70.
V
Input Voltage
V
I
V
CC
+ 0.3 ~
-
0.3
V
Output Voltage
V
O
V
CC
+ 0.3 ~
-
0.3
V
Operating Temperature Range
T
OPR
-
25 ~ 125
C
Storage Temperature Range
T
STG
-
65 ~ 150
C
Lead Temperature (Soldering, 10 secs)
T
LEAD
300
C
TIME SLOT ASSIGNMENT CIRCUIT
S5T8555
5
ELECTRICAL CHARACTERISTICS
(Unless otherwise noted; V
CC
= 5.0V
5%, Ta = 0
C to 70
C)
Characteristic
Symbol
Test Conditions
Min.
Typ.
Max.
Unit
Operating Current
I
CC
BCLK = 2.048MHz, all output
open
-
1
1.5
mA
Input Voltage High
V
IH
-
2.0
-
-
V
Input Voltage Low
V
IL
-
-
-
0.7
V
Input Current 1
I
I1
All Inputs Except Mode,
V
IL
V
IN
V
IH
-
1
-
1
A
Input Current 2
I
I2
Mode, V
IN
= 0V
-
100
-
-
A
Output Voltage High
V
OH
FS
X
and FS
R
Outputs,
I
OH
= 3mA
2.4
-
-
V
Output Voltage Low
FS
X
and FS
R
Outputs,
I
OH
= 3mA
-
-
0.4
V
TS
X
output, I
OL
=3mA
-
-
0.4
V
Rise and Fall Time of Clock
t
R (CK)
t
F (CK)
BCLK, CLK
C
-
-
50
nS
Delay to TS
X
Low
t
D (TSXL)
C
L
=50pF
-
-
140
nS
Delay to TS
X
High
t
D (TSXH)
R
L
=1k
30
-
100
nS
Hold Time BCLK to Frame Sync
t
H (BFS)
-
50
-
-
nS
Set-Up Time from Frame Sync
BCLK
t
H (FSB)
-
30
-
-
nS
Delay Time from BLCK Low to
FS
X/R
0-3 High or Low
t
D
C
L
= 50pF
-
-
50
nS
Hold Time from Channel Select
to CLK
t
H (CSC)
-
50
-
-
nS
Set-Up Time from Channel
Select to CLK
t
SU (CSC)
-
30
-
-
nS
Period of Clock
t
CK
BCLK, CLK
C
240
-
-
nS
Width of Clock High
t
W (CKH)
BCLK, CLK
50
-
-
nS
Width of Clock Low
t
W (CKL)
BCLK, CLK
50
-
-
nS
Set-Up Time from D
C
to CLK
t
SU (DCC)
-
30
-
-
nS
Hold Time from CLK to D
C
t
H (CDC)
-
50
-
-
nS
Set-Up Time from CS to CLK
t
SU (CC)
-
30
-
-
nS
Hold Time from CLK to CS
t
H (CC)
-
100
-
-
nS
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