DATA SHEET
S5L9250B
1
INTRODUCTION
The CD-ROM 48X 1 chip receives the input signal read from the CD-DA/VIDEO-CD/CD-ROM disc after handling
by the RF amplifier. The signal is input into the digital servo block which has a built-in DSP core, and goes
through focus and tracking adjustments. The RF signal input into a data path goes through the data slicer, PLL,
EFM demodulator, C1/C2 ECC and the audio handling block. In the case of a CD-DA, the signal is output through
the 1-bit DAC. In the case of a CD-ROM, the signal is input into an external CD-ROM controller for handling, then
transmitted to the host through the ATAPI I/F. Also, if you operate the CD-DA in audio buffering mode while
already in CAV mode, the signal is stored in the CD-ROM controller DRAM at high speed, then output at 1x from
the CD-ROM controller, after passing through the 1-bit DAC built-in to the S5L9250B.
FEATURES
Main Features
Digital servo, CD-DSP, 1-bit DAC.
33.8688MHz crystal.
Supports CLV 4X and 8X.
Supports CAV MAX 16X, 20X, 24X, 32X, 40X, and 48X.
Interrupt (SINTB)
MICOM interface
Digital Servo Block
Automatic adjusting feature (focus/tracking loop offset, balance, loop gain)
Built-in AGC feature that adapts to work optimally with various disc types
Built-in search algorithm for speed control
Servo monitor signal generation (FOK, MIRROR, TZC, ANTI-SHOCK)
Various loop filter coefficient selection by MICOM
Built-in algorithm for handling defects/shocks
Disc discriminating data out (FEpk, SBADpk)
RF IC and serial interface
Built-in 10-bit DAC (Focus/Tracking/SLD)
OAK DSP core
CD Digital Signal Processing Block
Wide capture range analog PLL
Data Slicer using duty feedback method
EFM demodulation
Sync detection, protection, insertion
CLV, CAV disc spindle motor control
C1/C2 ECC
Built-in 16 K SRAM for ECC
Subcode P - W handling feature
CD-DA Audio handling feature
SUB-Q De-interleaving & CRC check
High speed data transmission support by CD-ROM decoder block for audio buffering (sync mode
selection
between subcode sync and CD-DA data)
Digital audio out block
Subcode sync. Insertion, Protection
S5L9250B
DATA SHEET
2
1-Bit DAC
16-bit
digital-to-analog converter
On-chip analog postfilter
Filtered line-level outputs, linear phase filtering
90dB SNR
Sampling rate: 44.1kHz
Input rate 1Fs or 2Fs by normal mode/ double mode selection
Digital volume control by MICOM interface
On-chip voltage reference
Digital de-emphasis on/off, digital attenuation
Low clock jitter sensitivity
Technology & Gate Density
0.35um mixed mode CMOS technology
3.3V power supply (internal core & analog)
5.0V power supply (digital I/O)
Current used: 300mA
Package: 128QFP.
Core used: OAK DSP; ADC for servo use; DAC, 1-bit DAC; 16K SRAM.
Clock used:
1) 33.8688MHz & PLL clock (4.3218MHz * speed coeff.)
DP part.
2) 33.8688MHz or 40MHz synthesized frequency
servo part.
3) 16.9344MHz
1-bit DAC part.
ORDERING INFORMATION
Device
Package
Operating Temperature
S5L9250B01-Q0R0
128-QFP-1420C
-20
C -
+75
C
DATA SHEET
S5L9250B
3
CD-ROM 48X 1 CHIP (DSP+SERVO+1-BIT DAC) BLOCK DIAGRAM
Data
Slicer
PLL
(bit clock regenerator)
EQ Control
Voltage
Generator
EFM
Demodulator
Sync Detector
Glue
Logic
Data RAM
512 * 16*2
Analog
Block
PWM
Block
10-bit
ADC
ROM 8K
Word
OAK Core
10-bit
DAC*4
Memory
Control
SRAM for ECC
C1/C2 ECC
Audio Processing
Block
DSP I/F
CD-DSP Part
D/Filter &
1-bit DAC
Subcode I/F
Subcode
Processing
Block
Spindle
Control
D/Audio Out
Sub-Q Handling
Block
To Servo
From Servo
PSC
CMD
Micom
I/F
Timing
Generator
XI
XO
33.8688MHz
EQ CTL
To Motor
Digital
Audio
Subcode
I/F
Micom
I/F
nX-to-1X
CD-DA
Signal
Analog
Audio
TRD
Sled 1
FOD
Sled 0
TPWM 1
Various
Error
Signals
From RF
I/O
Signal
Servo Part
RF
Signal
FG
S5L9250B
DATA SHEET
4
PIN CONFIGURATION
EQCTL
VCCA1(VCCA)
RFI
LPF0
LPF1
VCCA7(VCCA)
EFMCOMP
VSSA7(VSSA)
RISS
VALGC
VCCA6(VSSA)
RVCO
RDAC
VSSA6(VSSA)
VCTRL
VCCA5(VCCA)
VBG
PWMI
PWMO
VSSA5(VSSA)
VHALF
VREF
VCCA4(VCCA)
AOUTR
AOUTL
VSSA4(VSSA)
KS9250
EVT3
PIN DIAGRAM
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
LRCKI
SDATAI
VDDD1-VDD3I
BCKI
VSSD1-VSSI
SCORO
DVSS12-VSSOP
CK50M
DVDD11-VDD3I
WFCKO
SBSO
DBDD11-VDD5OP
EXCK
DAOUT
DVSS11-VSSOP
BCKO
C2PO
DVSS10-VSSI
LRCKO
SDATAO
GFS
EFML/SL
DVSS9-VSSOP
CLVLOCK
PLCK/EMPH
PLOCK
DVDD8-VDD3I
SCANEN
DVSS8-VSSI
AD0
AD1
AD2
AD3
AD4
AD5
AD6
DVDD7-VDD5OP
AD7
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
VSSA1-VSSA
VREFI
VSSA2-VSSA
RFRP
RFCT
SBAD
CEI
TZCA
TE
TELPF
FE
FELPF
VCCA2-VCCA
AOUT
PPUMP
VSSA3-VSSA
TRD
FOD
SLED0
SLED1
SPINDLE
VREFO
VCCA3-VCCA
SMON
DVSS1-VSSOP
GPIO0
SSTOP/GPIO1
PS1/GPIO2
FG
DIRROT
DVDD2-VDD3I
RFEN
RFDATA
RFCLK
DVSS2-VSSI
DFCTI
TEST1
DVDD1-VDD5OP
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
TPWM1/GPIO3
CKO
TEST2
TEST3
DVDD2A(VDD3I)
TEST4
TZCO/GPIO4
MIRR/GPIO5
PHOLD/GPIO6
DVSS4(VSSI)
COUT/GPIO7
FOKB/GPIO8
SENSE
DVDD3(VDD5OP)
XI
XO
DVSS5(VSSOP)
SINTB
ZRST
WRB/RWB
DVDD4(VDD3I)
RDB/DSB
ALE/RSB
DVSS7(VSSOP)
CSB
DVSS6(VSSI)
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
RF Interface
Motor IF
RF IF
Micom IF
X'tal
Micom
IF
Monitor Part
CD-ROM Decoder IF
i-Bit
DAC
Part
PLL Part
Data Slicer
Part
From RF
NOTES:
1. P1 - P23: Analog
2. P24 - P102: Digital
3. P103 - P128: Digital
S5L9050B
EVT3
PIN DIAGRAM
DATA SHEET
S5L9250B
5
PIN DESCRIPTION
Table 1. Pin Description
No
Name
Description
Related
Block
I/O
Pad Type
To/From
1
VSSA1
Analog ground (EQ controller)
-
P
VSSA
-
2
VREFI
VREF input
SERVO
I
PICA
RF
3
VSSA2
Analog ground (for servo ADC use)
-
P
VSSA
-
4
RFRP
RF envelope signal
SERVO
I
PICA
RF
5
RFCT
RF envelope's center detection signal
SERVO
I
PICA
RF
6
SBAD
FOK, DFCT generating SUB-BEAM ADD
signal (E+F)
SERVO
I
PICA
RF
7
CEI
ERROR signal for center servo use
SERVO
I
PICA
RF
8
TZCA
TZC signal generating signal (=TE)
SERVO
I
PICA
RF
9
TE
Tracking error signal
SERVO
I
PICA
RF
10
TELPF
TE defect holding pin
SERVO
I
PICA
-
11
FE
Focusing error signal
SERVO
I
PICA
RF
12
FELPF
FE defect holding pin
SERVO
I
PICA
-
13
VCCA2
Analog 3.3V power (for servo ADC use)
-
P
VCCA
-
14
AOUT
Analog out
SERVO
O
POBA
MONI
15
PPUMP
Pump out for PLL use (filter)
SERVO
O
POBA
-
16
VSSA3
Analog ground (for servo DAC use)
-
P
VSSA
-
17
TRD
Tracking drive signal (10-bit DAC)
SERVO
O
POBA
DRV
18
FOD
Focusing drive signal (10-bit DAC)
SERVO
O
POBA
DRV
19
SLED0
Stepping control signal 0/DC motor
control signal
SERVO
O
POBA
DRV
20
SLED1
Stepping control signal 1
SERVO
O
POBA
DRV
21
SPINDLE
Spindle controlling PWM output
CLV
O
POBA
-
22
VREFO
VREF out for driver IC
SERVO
O
POBA
SLED
23
VCCA3
Analog 3.3V power (for DAC use)
-
P
VCCA
-
24
SMON
Spindle motor on/off
CLV
O
PHOB4
MOTOR
25
DVSS1
Digital GND
(for output PAD + PRE driver)
-
P
VSSOP
-
26
GPIO0
General purpose I/O 0
B
PHBCT4
27
STOP/GPIO
LIMIT switch/sled position sensor
PS0/general purpose I/O
SERVO
B
PHBCT4
-
28
PS1/GPIO
Sled position sensor signal 1/general
purpose I/O
SERVO
B
PHBCT4
-
29
FG
Frequency generator signal (for CAV)
CLV
I
PHIC
MOTOR
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