Электронный компонент: S5D2501F01

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JAN. 2000

DATA SHEET

S5D2501F

OSD PROCESSOR FOR MONITORS S5D2501F

1

OVERVIEW

The S5D2501F is used to display some characters or symbols
on a screen of monitor. Basically, the operation is to control the
internal memory on chip and generate the R,G,B signals for
some characters or symbols. The R,G,B signals are synchro-
nized with the horizontal sync. Then the R,G,B signals are
mixed with the main video signal in the Video Amp IC.
The font data for characters or symbols are stored in the inter-
nal ROM. This stored data are accessed and controlled by the
control data from a micro controller. The control data are trans-
mitted through the I

2

C bus. All timing control signals including

the system clock are synchronized with the horizontal sync.
Therefore there is a PLL circuitry on chip.

FEATURES

�

Build in 1K-byte SRAM

�

464 ROM fonts (448 standard fonts + 16 Multi-color

fonts)

�

Full Screen Memory Architecture

�

Wide range PLL available (15 kHz -- 120 kHz)

�

Programmable vertical height of character

�

Programmable vertical and horizontal positioning

�

Character color selection up to 16 different colors

�

Programmable background color (Up to 16 colors)

�

Character blinking, bordering and shadowing

�

Color blinking

�

Character scrolling

�

Fade-in and fade-out

�

Row to row spacing control

�

Window outline and shadowing

�

Box drawing

�

Character sizing up to four times

�

8 PWM DAC channels with 8-bit resolution

�

96 MHz pixel frequency from on-chip PLL

�

I2C Protocol Data Transmission (Slave Address : BAH)

�

OSD Vertical Bouncing Auto Detect / Correction

�

Back Raster Blanking (Row Control)

24-DIP-300

ORDERING INFORMATION

Device

Package

Operating Temperature

S5D2501F 24-DIP-300

0

�

C

-- 70

�

C

S5D2501F

OSD PROCESSOR FOR MONITORS

2

BLOCK DIAGRAM

Figure 1. Functional Block Diagram

.

PWM
Data

Control
Data

16

16

RAM
Data

16

ROM

Addr

9

Frame

Control

Row

Control

Display
Control

Font
Data

12

Font
Data

12

CLK

H-Pulse

V-Pulse

Frame

Control

Row

Control

H/V/CLK
Control

H/V/CLK
Control

PWM0

PWM1

PWM2

PWM3

PWM4

PWM5

PWM6

PWM7

HFLB

VFLB

VC

O_I

N

VR

EF
1

VR

EF

V

SS

A

V

DD

A

V

SS

V

DD

SDA

SCL

INT

R_OUT

G_OUT

B_OUT

FBLK

Font
Control

Data

Receiver

P

W
M
G

en
e

r
at

o

r

PW

M
R

e

g

i
s

t
e

r

Co
n

t
r
o

l

R

e

g

i
s

t
e

r

Single Color

ROM

(448 x 18x12)

RAM

(480 x 16)

Multi-Color

ROM

(16x4 x 18x12)

Display

Controller

Output

Stage

OSD_PLL

Timing

Controller

7

8

9

10

11

12

13

14

15

16

6

17

2

3

4

1

5

18

24

2 3

2 2

2 1

2 0

1 9

OSD PROCESSOR FOR MONITORS S5D2501F

3

PIN CONFIGURATIONS

Figure 2. Pin Configurations

1

2

3

4

5

6

7

8

9

1 0

1 1

1 2

2 4

2 3

2 2

2 1

2 0

1 9

1 8

1 7

1 6

1 5

1 4

1 3

S5D2501F

V S S - A

VCO-IN

V R E F 1

V R E F

V D D - A

H F L B

S D A

S C L

P W M 0

P W M 1

P W M 2

P W M 3

V D D _ D

INT

R _ O U T

G _ O U T

B _ O U T

F B L K

V S S _ D

V F L B

P W M 7

P W M 6

P W M 5

P W M 4

S5D2501F

OSD PROCESSOR FOR MONITORS

4

PIN DESCRIPTIONS

Table 1. Pin Descriptions

Pin No.

Signal

Active

I/O

Description

1

VSS_A

-

-

Ground (Analog Part)

2

VCO_IN

-

Input

This voltage is generated at the external loop filter and
goes into the input stage of the VCO.

3

VREF1

-

Input

1.26 V DC Voltage from the Bandgap Reference.
Connected to ground through a resistor to make internal
reference current (Typical 36 k

for 27

�

A)

4

VREF

-

Input

Bandgap Reference Voltage (Typical 1.26 V)

5

VDD_A

-

-

+5 V Supply Voltage for Analog Part

6

HFLB

Low

Input

Horizontal Flyback Signal

7

SDA

-

In/Out

Serial Data (I

2

C)

8

SCL

-

In/Out

Serial Clock (I

2

C)

9

PWM 0

-

Output

PWM DAC 0 Output

10

PWM 1

-

Output

PWM DAC 1 Output

11

PWM 2

-

Output

PWM DAC 2 Output

12

PWM 3

-

Output

PWM DAC 3 Output

13

PWM 4

-

Output

PWM DAC 4 Output

14

PWM 5

-

Output

PWM DAC 5 Output

15

PWM 6

-

Output

PWM DAC 6 Output

16

PWM 7

-

Output

PWM DAC 7 Output

17

VFLB

Low

Input

Vertical Flyback Signal

18

VSS_D

-

-

Ground for Digital Part

19

FBLK

-

Output

Fast Blank Signal

20

B_OUT

-

Output

Video Signal Output (B)

21

G_OUT

-

Output

Video Signal Output (G)

22

R_OUT

-

Output

Video Signal Output (R)

23

INT

-

Output

Intensity Signal Output

24

VDD_D

-

-

+5 V Supply Voltage for Dogital Part

Document Outline

• OVERVIEW
• Features
• Ordering Information
• Device
• Package
• Operating Temperature
• S5D2501F
• 24-DIP-300
• 0�C � 70�C
  • BLOCK DIAGRAM
    • Figure 1. Functional Block Diagram
  • PIN CONFIGURATIONS
    • Figure 2. Pin Configurations
  • PIN DESCRIPTIONS
    • Table 1. Pin Descriptions
• Pin No.
• Signal
• Active
• I/O
• Description
• 1
• VSS_A
• -
• -
• Ground (Analog Part)
• 2
• VCO_IN
• -
• Input
• This voltage is generated at the external loop filter and
• goes into the input stage of the VCO.
• 3
• VREF1
• -
• Input
• 1.26 V DC Voltage from the Bandgap Reference.
• Connected to ground through a resistor to make internal
• reference current (Typical 36 kW for 27mA)
• 4
• VREF
• -
• Input
• Bandgap Reference Voltage (Typical 1.26 V)
• 5
• VDD_A
• -
• -
• +5 V Supply Voltage for Analog Part
• 6
• HFLB
• Low
• Input
• Horizontal Flyback Signal
• 7
• SDA
• -
• In/Out
• Serial Data (I2C)
• 8
• SCL
• -
• In/Out
• Serial Clock (I2C)
• 9
• PWM 0
• -
• Output
• PWM DAC 0 Output
• 10
• PWM 1
• -
• Output
• PWM DAC 1 Output
• 11
• PWM 2
• -
• Output
• PWM DAC 2 Output
• 12
• PWM 3
• -
• Output
• PWM DAC 3 Output
• 13
• PWM 4
• -
• Output
• PWM DAC 4 Output
• 14
• PWM 5
• -
• Output
• PWM DAC 5 Output
• 15
• PWM 6
• -
• Output
• PWM DAC 6 Output
• 16
• PWM 7
• -
• Output
• PWM DAC 7 Output
• 17
• VFLB
• Low
• Input
• Vertical Flyback Signal
• 18
• VSS_D
• -
• -
• Ground for Digital Part
• 19
• FBLK
• -
• Output
• Fast Blank Signal
• 20
• B_OUT
• -
• Output
• Video Signal Output (B)
• 21
• G_OUT
• -
• Output
• Video Signal Output (G)
• 22
• R_OUT
• -
• Output
• Video Signal Output (R)
• 23
• INT
• -
• Output
• Intensity Signal Output
• 24
• VDD_D
• -
• -
• +5 V Supply Voltage for Dogital Part
  • ABSOLUTE MAXIMUM RATINGS
• Parameters
• Symbol
• Value
• Unit
• Min.
• Typ.
• Max.
• Maximum Supply Voltage
• VDD
• -
• -
• 6.5
• V
• Input Voltage
• VI
• -
• -
• 5.25
• V
• Operating Temperature Range
• TOPR
• -20
• -
• 70
• �C
• Storage Temperature Range
• TSTG
• -40
• 125
• �C
• Power Dissipation
• PD
• -
• -
• 1200
• mW
  • ELECTRICAL CHARACTERISTICS
    • Table 2. DC Electrical Characteristics
• Parameters (Conditions)
• Symbol
• Min.
• Typ.
• Max.
• Unit
• Supply Voltage
• VDD
• 4.75
• 5.00
• 5.25
• V
• Supply Current
• (No load on any output)
• IDD
• -
• -
• 25
• mA
• Input Voltage
• VIH
• 0.8VDD
• -
• -
• V
• VIL
• -
• -
• VSS + 0.4
• V
• Output Voltage
• (lout = �1mA)
• VOH
• 0.8VDD
• -
• -
• V
• VOL
• -
• -
• VSS + 0.4
• V
• Input Leakage Current
• IIL
• -10
• -
• 10
• mA
• VCO Input Voltage
• VVCO
• 2.5
• V
  • Operation Timings
    • Table 3. Operation Timings
• Parameters (Conditions)
• Symbol
• Min.
• Typ.
• Max.
• Unit
• Output Signal R/G/B_OUT, INT, FBLK (Ta = 25�C VDDA = VDD = 5 V , CLOAD = 30pF)
• Rise Time
• tR
• -
• -
• 6
• nsec
• Fall Time
• tF
• -
• -
• 6
• nsec
• Input Signal HFLB, VFLB
• Horizontal Flyback Signal Frequency
• fHFLB
• -
• -
• 120
• kHz
• Vertical Flyback Signal Frequency
• fVFLB
• -
• -
• 200
• Hz
• I2C Interface SDA, SCL (Refer to Figure 3)
• SCL Clock Frequency
• fSCL
• -
• -
• 300
• kHz
• Hold Time for start condition
• ths
• 500
• -
• -
• ns
• Set Up Time for stop condition
• tsus
• 500
• -
• -
• ns
• Low Duration of clock
• tlow
• 400
• -
• -
• ns
• High Duration of clock
• thigh
• 400
• -
• -
• ns
• Hold Time for data
• thd
• 0
• -
• -
• ns
• Set Up Time for data
• tsud
• 500
• -
• -
• ns
• Time between 2 access
• tss
• 500
• -
• -
• ns
• Fall Time of SDA
• tfSDA
• -
• -
• 20
• ns
• Rise Time of both SCL and SDA
• trSDA
• -
• -
• -
• ns
  • Figure 3. I2C Bus Timing Diagram
  • FUNCTIONAL DESCRIPTIONS
• A15
• A14
• A13
• A12
• A11
• A10
• A9
• A8
• X
• X
• X
• X
• R3
• R2
• R1
• R0
• A7
• A6
• A5
• A4
• A3
• A2
• A1
• A0
• X
• X
• X
• C4
• C3
• C2
• C1
• C0
  • Figure 4. (a) SDA line and SCL line (Write Operation)
  • Figure 5. Memory Map of Display Registers
  • Figure 6. Array of ROM Fonts
  • PWM OutPuT
• Horizontal Mode
• 320 dots/line
• (fPWM)
• 480 dots/line
• (fPWM)
• 640 dots/line
• (fPWM)
• 800 dots/line
• (fPWM)
• 15kHz < Hf < 20kHz
• (320/256) * Hf
• (480/256) * Hf
• (640/256) * Hf
• (800/256) * Hf
• 20kHz < Hf < 35kHz
• (800/256) * (Hf/2)
• 35kHz < Hf < 50kHz
• (640/256) * (Hf/2)
• 50kHz < Hf < 65kHz
• (480/256) * (Hf/2)
• 65kHz < Hf < 80kHz
• (800/256) * (Hf/4)
• 80kHz < Hf < 95kHz
• (640/256) * (Hf/4)
• 95kHz < Hf < 110kHz
• (320/256) * (Hf/2)
• 110kHz < Hf < 120kHz
  • Frame Control & Timing
    • Figure 7. Frame Composition with the OSD Characters
    • Table 4. Register Description (Continued)
• Registers
• Bits
• Description
• Character & Attribute
• Register (Row 00�14,
• Column 00�29)
• C8�C0
• (Bit 8�0)
• Character Code Address of 464 ROM Fonts.
• Blink
• (Bit 9)
• Character Blinking.
• Set this bit to activate the blinking effect. The blinking period is set
• by the 'Bli T' bit and the duty is selected by the 'Bli 0' and 'Bli 1' bits.
• If �INTE� bit is high, this bit controls the font intensity combined with
• �INTE�, �RINT� and �CINT� as following table.
• INTE
• Blink
• RINT
• CINT
• Function
• 0
• 0
• -
• -
• Normal
• 0
• 1
• -
• -
• Blink
• 1
• 0
• -
• -
• Normal
• 1
• 1
• 0
• 1
• Character Intensity
• 1
• 1
• 1
• 0
• Raster Intensity
• 1
• 1
• 1
• 1
• Character & Raster Intensity
• B,G,R
• (Bit C�A)
• Character Color is determined by these bits.
• 8 colors can be selected and the color intensity of a character is
• given by 'CINT' bit of Row Attribute Regisers.
• So you can select up to 16 colors. If a multi-color font is selected,
• this bits must be set to all 0's.
• BOX 1, BOX0
• (Bit E, D)
• Character Box Drawing.
• The combinations of this two bits generate four different box drawing
• modes as following. The following example is the case that box
• dawing is activated with the font 'A'.
• * Bit F � D (RB/RG/RR) is also used for raster color by setting the
• 'BOXE' bit low. Raster color of a font is determined by this bits if
• the 'BOXE' bit is low. Priority of raster color selected here is higher
• than that of row attribute.
• Character & Attribute
• Register
• BINV
• (Bit F)
• Box Inversion.
• The box drawing activated by the bit E and D is changed to white
• box from black and conversely.
• Row Attribute Register
• (Row 00 � 14, Column 30)
• VZ1,VZ0
• (Bit 1, 0)
• Vertical Character Size Control.
• Vertical character size is determined by the combinations of this two
• bits as following table.
• VZ1
• VZ0
• Vertical Character Size
• 0
• 0
• 1X
• 0
• 1
• 2X
• 1
• 0
• 3X
• 1
• 1
• 4X
• HZ1,HZ0
• (Bit 3, 2)
• Horizontal Character Size Control.
• The horizontal character size is determined by the combinations of
• this two bits as following table.
• HZ1
• HZ0
• Horizontal Character Size
• 0
• 0
• 1X
• 0
• 1
• 2X
• 1
• 0
• 3X
• 1
• 1
• 4X
• CINT
• (Bit 4)
• Character Color Intensity.
• If INTE, Blink and this bit is set, the color intensity of characters
• in the same row is high.
• RINT
• (Bit 5)
• Raster Color Intensity.
• If INTE, Blink and this bit is set, the color intensity of rasters
• in the same row is high
• RB,RG,RR
• (Bit 8�6)
• Raster Color is determined by these bits.
• 8 colors can be selected and the color intensity of a character is
• given by 'RINT' bit of Row Attribute Registers.
• So you can select up to 16 colors.
• SHA
• (BIT 9)
• Character Shadowing.
• Set this bit to activate characters shadowing.
• BORD
• (Bit A)
• Character Bordering.
• Set this bit to activate characters bordering.
• Row Attribute Register
• BOXE
• (Bit B)
• BOX Enable.
• If this bit is set, Bit F-D in the Character & Attribute Registers are
• used for the box-drawing function.
• Otherwise,those are used for raster color of a font.
• Even though the raster color attribute is given by Bit 8-6 in the row
• attribute registers, the priority of Bit F-D in the character & attribute
• registers is higher.
• CBli
• (Bit C)
• Color Blink Enable.
• If this bit is high, color blinking effect is activated. The color effect is
• to repeat color inversion between character and raster.
• Color blinking time and the duty is controlled by Bil T, Bil 1 and Bli 0.
• INTE
• (Bit D)
• Intensity Enable.
• If this bit and Blink bit(CHARACTER ATTRIBUTE) is high, character
• and raster intensity can be controlled.
• BREN
• (Bit E)
• Back Raster Enable.
• If this bit is high and back raster color is black, back raster color is
• blank.
• Bit F
• Reserved
• Frame Control Register 0
• (Row 15, Column 00)
• Bli T
• (Bit 0)
• Blink Time Control.
• If this bit is high, the blink time is 0.5 sec. Otherwise, 1 sec.
• Bli 1,Bli 0
• (Bit 2,1)
• Blinking Duty Control.
• The blinking duty is controlled by the combination of this two bits as
• following.
• Bli 1
• Bli 0
• Blinking Duty
• 0
• 0
• Blink Off
• 0
• 1
• Duty 25%
• 1
• 0
• Duty 50%
• 1
• 1
• Duty 75%
• ScrT
• (Bit 3)
• Scroll Time Control.
• If this bit is high, the scroll time is 1 sec. Otherwise, 0.5 sec.
• Scrl
• (Bit 4)
• Scroll Enable.
• The scroll display is activated by setting this bit high.
• EN
• (Bit 5)
• OSD Enable.
• The character display is controlled by this bit. If this bit is high,
• OSD is enable. Otherwise, disable.
• Erase
• (Bit 6)
• RAM Erasing.
• RAM data are erased by setting this bit.
• WSHA
• (Bit 8)
• Window Shadowing.
• Set this bit to activate window shadowing.
• WBOR
• (Bit 9)
• Window Bordering.
• Set this bit to activate window bordering.
• WC
• (Bit A)
• White/black selection of window border and shadow.
• If this bit is high, the color of window border and shadow is white.
• Otherwise, black.
• HPOL
• (Bit B)
• Polarity of Horizontal Fly Back Signal. Positive 1, Negative 0
• VPOL
• (Bit C)
• Polarity of Vertical Fly Back Signal. Positive 1, Negative 0
• FdeT
• (Bit D)
• Fade-in and fade-out Time Control.
• If this bit is high, the time is 1 sec. Otherwise, 0.5 sec.
• Fde
• (Bit E)
• Fade-in and fade-out Enable.
• The fade-in and fade-out effect is activated by setting this bit high.
• Bit F
• Reserved.
• Frame Control Register 1
• (Row 15, Column 01)
• CH5�CH0
• (Bit 5�0)
• Character Height Control.
• The vertical character size is determined by the bit 'VZ1' and VZ0'.
• This six bits are available to get a proper character height by setting
• a binary value. According to the value made by this six bits,
• the character height is determined.
• If the value is 32, the number of vertical pixel of character font is 32.
• Eventually, the character height is expanded from 18 to 63.
• The binary vlaue must be greater than 18.
• FBLK
• (Bit 6)
• It determines the configuration of FBLK output pin.
• When it is clear, FBLK pin outputs high during displaying characters
• or rasters. Otherwise,FBLK pin outputs high only during displaying
• characters.
• dot 1,dot 0
• (Bit 9,8)
• This two bits determine the number of dots per horizontal line.
• Refer to following table.
• dot 1
• dot 0
• No. of Dots
• 0
• 0
• 320 dots/line
• 0
• 1
• 480 dots/line
• 1
• 0
• 640 dots/line
• 1
• 1
• 800 dots/line
• HF2�HF0
• (Bit C�A)
• These three bits decide horizontal frequency range (region).
• Please refer to Application Note for more information.
• FPLL
• (Bit D)
• If this bit is high, the VCO block of OSD_PLL operates on full range
• (4 MHz - 96 MHz).
• Frame Control Register 1
• (Row 15, Column 01)
• CP 1,CP 0
• (Bit F,E)
• This bit controls charge pump output current.
• CP 1
• CP 0
• Charge Pump Current
• 0
• 0
• 0.75mA
• 0
• 1
• 1 mA
• 1
• 0
• 1.25mA
• 1
• 1
• 1.5 mA
• Frame Control Register 2
• (Row 15, Column 02)
• VP7�VP0
• (Bit 7�0)
• Vertical Start Position Control.
• It means the top margin height from the V-sync reference edge.
• ( = VP[7:0] � 4 )
• HP7�HP0
• (Bit F�8)
• Horizontal Start Position Control.
• It means the horizontal display delay from the H-sync reference
• edge to the 1'st pixel position of characters. ( = HP[7:0] � 6 )
• Frame Control Register 3
• (Row 15, Column 02)
• STC 4
• �STC 0
• Window Start Column Position.
• It means the column address that window starts from.
• STR 3
• �STR 0
• Window Start Row Position.
• It means the row address that window starts from.
• RSI
• Row Space Color Intensity.
• RSR,RSG, RSB
• Row Space Color Attribute.
• RS2�RS0
• (Bit F�D)
• Row Space.
• It means the line number between a character row and the next row.
• The defaut value is 0. (line number for spacing = RS[2:0] � 2)
• Frame Control Register 4
• (Row 15, Column 04)
• SPC 4� SPC 0
• Window Stop Column Position.
• It means the column address that window stops on.
• SPR 3� SPR 0
• Window Stop Row Position.
• It means the row address that window stops on.
• VW 1, 0
• Vertical width of window shadowing.
• HW 1, 0
• Horizontal width of window shadowing.
• BW 1, 0
• Width of window bordering.
• PWM Registers
• (Row 15, Column 05 - 08)
• Bit 7� 0
• This 8-bit value decides the output duty cycle and waveforms of
• PWM for channel 1,3,5 and 7.
• Bit F�8
• This 8-bit value decides the output duty cycle and waveforms of
• PWM for channel 2,4,6 and 8.