S3C9234/P9234

PRODUCT OVERVIEW

1-1

PRODUCT OVERVIEW

SAM88RCRI PRODUCT FAMILY

Samsung's SAM88RCRI family of 8-bit single-chip CMOS microcontrollers offer fast and efficient CPU, a wide range
of integrated peripherals, and supports OTP device.

A dual address/data bus architecture and bit- or nibble-configurable I/O ports provide a flexible programming
environment for applications with varied memory and I/O requirements. Timer/counters with selectable operating
modes are included to support real-time operations.

S3C9234/P9234 MICROCONTROLLER

The S3C9234 can be used for dedicated control functions in a variety of applications, and is especially designed for
application with FRS or etc.

The S3C9234/P9234 single-chip 8-bit microcontroller is fabricated using an advanced CMOS process. It is built
around the powerful SAM88RCRI CPU core.

Stop and Idle power-down modes were implemented to reduce power consumption. To increase on-chip register
space, the size of the internal register file was logically expanded. The S3C9234/P9234 has 4K-byte of program
ROM, and 208-byte of RAM (including 16-byte of working register and 16-byte LCD display RAM).

Using the SAM88RCRI design approach, the following peripherals were integrated with the SAM88RCRI core:

-- 7 configurable I/O ports including ports shared with segment/common drive outputs

-- 7-bit programmable pins for external interrupts

-- One 8-bit basic timer for oscillation stabilization and watch-dog functions

-- Two 8-bit timer/counters with selectable operating modes

-- Watch timer for real time

-- 8-bit serial I/O interface

OTP

The S3C9234 microcontroller is also available in OTP (One Time Programmable) version. S3P9234 microcontroller
has an on-chip 4K-byte one-time-programmable EPROM instead of masked ROM.
The S3P9234 is comparable to S3C9234, both in function and in pin configuration.

PRODUCT OVERVIEW

S3C9234/P9234

1-2

FEATURES

CPU

SAM88RCRI CPU core

Memory

8 bits program memory (ROM)

208

8 bits data memory (RAM)

(Including LCD data memory)

Instruction Set

41 instructions

Idle and Stop instructions added for power-down
modes

52 I/O Pins

I/O: 16 pins

I/O: 36 pins (sharing with LCD signal outputs)

Interrupts

11 interrupt source and 1 vector

One interrupt level

8-Bit Basic Timer

Watchdog timer function

3 kinds of clock source

Two 8-Bit Timer/Counters

The programmable 8-bit timer/counters

External event counter function

Configurable as one 16-bit timer/counters

Watch Timer

Interval time: 3.91mS, 0.25S, 0.5S, and 1S
at 32.768 kHz

0.5/1/2/4 kHz Selectable buzzer output

LCD Controller/Driver

32 segments and 4 common terminals

Static, 1/2 duty, 1/3 duty, and 1/4 duty selectable

Internal resistor circuit for LCD bias

8-bit Serial I/O Interface

8-bit transmit/receive mode

8-bit receive mode

LSB-first or MSB-first transmission selectable

Internal or external clock source

Two Power-Down Modes

Idle mode: only CPU clock stops

Stop mode: system clock and CPU clock stop

Oscillation Sources

Crystal, ceramic, or RC for main clock

Main clock frequency: 0.4 MHz - 8MHz

32.768 kHz crystal oscillation circuit for
sub clock

Instruction Execution Times

500nS at 8MHz fx(minimum)

Operating Voltage Range

2.0 V to 5.5 V at 0.4 - 4.2MHz

2.7 V to 5.5 V at 0.4 - 8.0MHz

Operating Temperature Range

-25

C to +85

Package Type

64-pin QFP

S3C9234/P9234

PRODUCT OVERVIEW

1-3

BLOCK DIAGRAM

8-Bit Timer/

CounterA

Port I/O and Interrupt

Control

SAM88RCRI CPU

RESET

I/O Port 0

4-Kbyte

ROM

208-Byte

File

OUT

16-Bit

Timer/

Counter1

8-Bit Timer/

CounterB

P0.0-P0.3/

COM0-COM3

I/O Port 1

P2.0/SCK

P2.1/SO

P2.2/SI

P2.3

P2.4/INT
P2.5/INT
P2.6/INT
P2.7/INT

I/O Port 2

I/O Port 3

I/O Port 4

P4.0-P4.7/

SEG23-SEG16

Watchdog

Timer

Basic Timer

Watch Timer

LCD

Driver/

Controller

SIO

I/O Port 6

P2.0/SCK
P2.1/SO
P2.2/SI

BUZ/P1.7

I/O Port 5

TAOUT/P1.4

T1CLK/P1.3

TBOUT/P1.5

P3.0-P3.7/

SEG31-SEG24

P1.0/INT
P1.1/INT
P1.2/INT

P1.3/T1CLK

P1.4/TAOUT
P1.5/TBOUT

P1.6/CLKOUT

P1.7/BUZ

SEG24-SEG31/P3.7-P3.0

SEG16-SEG23/P4.7-P4.0

SEG8-SEG15/P5.7-P5.0

COM0-COM3/P0.0-P0.3

SEG0-SEG7/P6.7-P6.0

P6.0-P6.7/
SEG7-SEG0

P5.0-P5.7/
SEG15-SEG8

Figure 1-1. Block Diagram

PRODUCT OVERVIEW

S3C9234/P9234

1-4

PIN ASSIGNMENTS

S3C9234(S3P9234)

(64-QFP-1420F)

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19

51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33

SEG13/P5.2
SEG14/P5.1
SEG15/P5.0
SEG16/P4.7
SEG17/P4.6
SEG18/P4.5
SEG19/P4.4
SEG20/P4.3
SEG21/P4.2
SEG22/P4.1
SEG23/P4.0
SEG24/P3.7
SEG25/P3.6
SEG26/P3.5
SEG27/P3.4
SEG28/P3.3
SEG29/P3.2
SEG30/P3.1
SEG31/P3.0

COM0/P0.0
COM1/P0.1
COM2/P0.2
COM3/P0.3

BIAS

VLC0
VLC1
VLC2

OUT

TEST

OUT

RESET

P1.0/INT
P1.1/INT
P1.2/INT

SEG0/P6.7

SEG1/P6.6

SEG2/P6.5

SEG3/P6.4

SEG4/P6.3

SEG5/P6.2

SEG6/P6.1

SEG7/P6.0

SEG8/P5.7

SEG9/P5.6

SEG10/P5.5

SEG11/P5.4

SEG12/P5.3

P1.3/T1CLK

P1.4/TAOUT

P1.5/TBOUT

P1.6/CLKOUT

P1.7/BUZ

P2.0/SCK

P2.1/SO

P2.2/SI

P2.3

P2.4/INT

P2.5/INT

P2.6/INT

P2.7/INT

Figure 1-2. S3C9234 64-QFP Pin Assignments

S3C9234/P9234

PRODUCT OVERVIEW

1-5

PIN DESCRIPTIONS

Table 1-1. Pin Descriptions

Pin Names

Pin

Type

Pin Description

Circuit

Type

Pin No.

Shared

Functions

P0.0 - P0.3

I/O

I/O port with bit-programmable pins;
Input or push-pull output and software
assignable pull-ups.

H-9

1 - 4

COM0-COM3

P1.0 - P1.2
P1.3
P1.4
P1.5
P1.6
P1.7

I/O

I/O port with bit-programmable pins;
Schmitt trigger input or push-pull, open-drain
output and software assignable pull-ups;
P1.0 P1.2 are alternately used for external
interrupt input(noise filters, interrupt enable and
pending control).

E-4

17 19

20
21
22
23
24

INT

T1CLK

TAOUT
TBOUT

CLKOUT

BUZ

P2.0
P2.1
P2.2
P2.3
P2.4 P2.7

I/O

I/O port with bit-programmable pins;
Schmitt trigger input or push-pull, open-drain
output and software assignable pull-ups.

E-4

25
26
27
28

29 - 32

SCK

INT

P3.0 - P3.7

I/O

I/O port with bit-programmable pins;
Input or push-pull, open-drain output and
software assignable pull-ups.

H-8

33 - 40

SEG31-SEG24

P4.0 - P4.7

I/O

I/O port with bit-programmable pins;
Input or push-pull output and software assignable
pull-ups.

H-9

41 - 48

SEG23-SEG16

P5.0 P5.7

I/O

I/O port with bit-programmable pins;
Input or push-pull output and software assignable
pull-ups.

H-9

49 - 56

SEG15-SEG8

P6.0 P6.7

I/O

I/O port with 2bits-programmable pins;
Input or push-pull output and software assignable
pull-ups.

H-9

57 - 64

SEG7-SEG0

RESET

System reset pin

,XT

OUT

Crystal oscillator pins for sub clock.

14, 15

OUT

Main oscillator pins.

12, 11

TEST

Test input: it must be connected to V

Power input pins

9, 10

BAIS

LCD power control pin

VLC0VLC2

LCD power supply pin

6 8

INT

I/O

External interrupts input pins.

E-4

17 19
29 32

P1.0 P1.2
P2.4 P2.7

PRODUCT OVERVIEW

S3C9234/P9234

1-6

Table 1-1. Pin Descriptions (Continued)

Pin Names

Pin

Type

Pin Description

Circuit

Type

Pin No.

Shared

Functions

T1CLK

I/O

Timer 1/A external clock input.

E-4

P1.3

TAOUT

I/O

Timer 1/A clock output.

E-4

P1.4

TBOUT

I/O

Timer B clock output.

E-4

P1.5

CLKOUT

I/O

System clock output.

E-4

P1.6

BUZ

I/O

Output pin for buzzer signal.

E-4

P1.7

SCK, SO, SI

I/O

Serial clock, serial data output, and serial
data input.

E-4

25 27

P2.0 P2.2

COM0-COM3

I/O

LCD common signal outputs.

H-9

1 4

P0.0 P0.3

SEG0 SEG7
SEG8 SEG15
SEG16 SEG23

I/O

LCD segment signal outputs.

H-9

64 57
56 49
48 41

P6.7 P6.0
P5.7 P5.0
P4.7 P4.0

SEG24 SEG31

I/O

LCD segment signal outputs.

H-8

40 33

P3.7 P3.0

S3C9234/P9234

ADDRESS SPACES

2-1

ADDRESS SPACES

OVERVIEW

The S3C9234/P9234 microcontroller has three kinds of address space:

-- Program memory (ROM)

-- Internal register file

-- LCD display register file

A 16-bit address bus supports program memory operations. Special instructions and related internal logic determine
when the 16-bit bus carries addresses for program memory. A separate 8-bit register bus carries addresses and data
between the CPU and the internal register file.

The S3C9234 has 4K bytes of mask - programmable program memory on-chip. The S3C9234/P9234 microcontroller
has 192 bytes general-purpose registers in its internal register file and the 16 bytes for LCD display memory is
implemented in the internal register file too. 48 bytes in the register file are mapped for system and peripheral control
functions.

ADDRESS SPACES

S3C9234/P9234

2-2

PROGRAM MEMORY (ROM)

Program memory (ROM) stores program code or table data. The S3P9234 has 4K bytes of mask - programmable
program memory. The program memory address range is therefore 0H-0FFFH. The first 2 bytes of the ROM (0000H
0001H) are an interrupt vector address. The program reset address in the ROM is 0100H.

4,096

256

0FFFH

0100H

4K bytes

Internal

Program

Memory

Area

Interrupt

Vector

0002H

0001H

Program Start

0000H

(Decimal)

(Hex)

Figure 2-1. S3C9234/P9234 Program Memory Address Space

S3C9234/P9234

ADDRESS SPACES

2-3

REGISTER ARCHITECTURE

The upper 64 bytes of the S3C9234/P9234's internal register file are addressed as working registers, system control
registers and peripheral control registers. The lower 192 bytes of internal register file (00HBFH) is called the general
purpose register space.

For many SAM88RCRI microcontrollers, the addressable area of the internal register file is further expanded by the
additional of one or more register pages at general purpose register space (00HBFH).

FFH

B0H

AFH

00H

192 Bytes

64 Bytes of

Common Area

D0H
CFH

E0H

DFH

Working Registers

System Control

Registers

Peripheral Control

Registers

General Purpose

and Stack Area

LCD Display Registers and

General Purpose Registers

C0H
BFH

Byte

Figure 2-2. Internal Register File Organization

ADDRESS SPACES

S3C9234/P9234

2-4

COMMON WORKING REGISTER AREA (C0HCFH)

The SAM88RCRI register architecture provides an efficient method of working register addressing that takes full
advantage of shorter instruction formats to reduce execution time.

This16-byte address range is called common area. That is, locations in this area can be used as working registers
by operations that address any location on any page in the register file. Typically, these working registers serve as
temporary buffers for data operations between different pages.

The Register (R) addressing mode can be used to access this area

Registers are addressed either as a single 8-bit register or as a paired 16-bit register. In 16-bit register pairs, the
address of the first 8-bit register is always an even number and the address of the next register is an odd number.
The most significant byte of the 16-bit data is always stored in the even-numbered register; the least significant byte
is always stored in the next (+ 1) odd-numbered register.

MSB

LSB

Rn + 1

n = Even address

Figure 2-3. 16-Bit Register Pairs

PROGRAMMING TIP -- Addressing the Common Working Register Area

As the following examples show, you should access working registers in the common area, locations C0HCFH,
using working register addressing mode only.

Examples:

1. LD

0C2H,40H

; Invalid addressing mode!

Use working register addressing instead:

R2,40H

; R2 (C2H)

the value in location 40H

2. ADD

0C3H,#45H

; Invalid addressing mode!

Use working register addressing instead:

ADD R3,#45H

; R3 (C3H)

R3 + 45H

S3C9234/P9234

ADDRESS SPACES

2-5

SYSTEM STACK

S3C9-series microcontrollers use the system stack for subroutine calls and returns and to store data. The PUSH
and POP instructions are used to control system stack operations. The S3C9234/P9234 architecture supports stack
operations in the internal register file.

STACK OPERATIONS

Return addresses for procedure calls and interrupts and data are stored on the stack. The contents of the PC are
saved to stack by a CALL instruction and restored by the RET instruction. When an interrupt occurs, the contents of
the PC and the FLAGS register are pushed to the stack. The IRET instruction then pops these values back to their
original locations. The stack address is always decremented before a push operation and incremented after a pop
operation. The stack pointer (SP) always points to the stack frame stored on the top of the stack, as shown in Figure
2-4.

Stack contents

after a call
instruction

Stack contents

after an

interrupt

Top of

stack

Flags

PCH

PCL

PCH

Top of

stack

Low Address

High Address

Figure 2-4. Stack Operations

STACK POINTER (SP)

Register location D9H contains the 8-bit stack pointer (SP) that is used for system stack operations. After a reset,
the SP value is undetermined.

Because only internal memory space is implemented in the S3C9234/P9234, the SP must be initialized to an 8-bit
value in the range 00HAFH.

NOTE

In case a Stack Pointer is initialized to 00H, it is decreased to FFH when stack operation starts. This means
that a Stack Pointer access invalid stack area.

ADDRESS SPACES

S3C9234/P9234

2-6

PROGRAMMING TIP -- Standard Stack Operations Using PUSH and POP

The following example shows you how to perform stack operations in the internal register file using PUSH and POP
instructions:

SP,#0B8H

; SP

B8H (Normally, the SP is set to 0B8H by the

; initialization routine)

·
·
·

PUSH

SYM

; Stack address 0B7H

SYM

PUSH

WTCON

; Stack address 0B6H

WTCON

PUSH

20H

; Stack address 0B5H

20H

PUSH

; Stack address 0B4H

·
·
·

POP

; R3

Stack address 0B4H

POP

20H

; 20H

Stack address 0B5H

POP

WTCON

; WTCON

Stack address 0B6H

POP

SYM

; SYM

Stack address 0B7H

S3C9234/P9234

ADDRESSING MODES

3-1

ADDRESSING MODES

OVERVIEW

Instructions that are stored in program memory are fetched for execution using the program counter. Instructions
indicate the operation to be performed and the data to be operated on. Addressing mode is the method used to
determine the location of the data operand. The operands specified in SAM88RCRI instructions may be condition
codes, immediate data, or a location in the register file, program memory, or data memory.

The SAM88RCRI instruction set supports six explicit addressing modes. Not all of these addressing modes are
available for each instruction. The addressing modes and their symbols are as follows:

-- Register (R)

-- Indirect Register (IR)

-- Indexed (X)

-- Direct Address (DA)

-- Relative Address (RA)

-- Immediate (IM)

ADDRESSING MODES

S3C9234/P9234

3-2

REGISTER ADDRESSING MODE (R)

In Register addressing mode, the operand is the content of a specified register (see Figure 3-1). Working register
addressing differs from Register addressing because it uses a 16-byte working register space in the register file and
a 4-bit register within that space (see Figure 3-2).

dst

Value used in

Instruction Execution

OPCODE

OPERAND

8-bit Register

File Address

Point to One

Rigister in Register

File

One-Operand

Instruction

(Example)

Sample Instruction:

DEC

CNTR

; Where CNTR is the label of an 8-bit register address

Program Memory

Figure 3-1. Register Addressing

dst

OPCODE

4-Bit

Working Register

Point to the

Woking Register

(1 of 16)

Two-Operand

Instruction

(Example)

Sample Instruction:

ADD

R1, R2

; Where R1 = C1H and R2 = C2H

Program Memory

src

4 LSBs

OPERAND

CFH

C0H

.
.
.
.

Figure 3-2. Working Register Addressing

S3C9234/P9234

ADDRESSING MODES

3-3

INDIRECT REGISTER ADDRESSING MODE (IR)

In Indirect Register (IR) addressing mode, the content of the specified register or register pair is the address of the
operand. Depending on the instruction used, the actual address may point to a register in the register file, to
program memory (ROM), or to an external memory space (see Figures 3-3 through 3-6).

You can use any 8-bit register to indirectly address another register. Any 16-bit register pair can be used to
indirectly address another memory location.

8-Bit Register

File Address

One-Operand

Instruction

(Example)

dst

Address of Operand

used by Instruction

OPCODE

ADDRESS

Point to One

Rigister in Register

File

Sample Instruction:

@SHIFT

; Where SHIFT is the label of an 8-Bit register address

Program Memory

Value used in

Instruction Execution

OPERAND

Figure 3-3. Indirect Register Addressing to Register File

ADDRESSING MODES

S3C9234/P9234

3-6

INDIRECT REGISTER ADDRESSING MODE (Concluded)

dst

OPCODE

4-Bit Working

Sample Instructions:

LCD

R5,@RR6

; Program memory access

LDE

R3,@RR14

; External data memory access

LDE

@RR4, R8

; External data memory access

Program Memory

src

Value used in

Instruction

OPERAND

Example Instruction

References either

Program Memory or

Data Memory

Program Memory

Data Memory

Next 3 Bits Point

to Working

(1 of 8)

LSB Selects

Pair

16-Bit
address
points to
program
memory
or data
memory

CFH

.
.
.
.

C0H

Figure 3-6. Indirect Working Register Addressing to Program or Data Memory

S3C9234/P9234

ADDRESSING MODES

3-7

INDEXED ADDRESSING MODE (X)

Indexed (X) addressing mode adds an offset value to a base address during instruction execution in order to
calculate the effective operand address (see Figure 3-7). You can use Indexed addressing mode to access locations
in the internal register file or in external memory.

In short offset Indexed addressing mode, the 8-bit displacement is treated as a signed integer in the range of
128 to +127. This applies to external memory accesses only (see Figure 3-8).

For register file addressing, an 8-bit base address provided by the instruction is added to an 8-bit offset contained in
a working register. For external memory accesses, the base address is stored in the working register pair
designated in the instruction. The 8-bit or 16-bit offset given in the instruction is then added to the base address (see
Figure 3-9).

The only instruction that supports Indexed addressing mode for the internal register file is the Load instruction (LD).
The LDC and LDE instructions support Indexed addressing mode for internal program memory, external program
memory, and for external data memory, when implemented.

dst

OPCODE

Two-Operand

Instruction

Example

Point to One of the

Woking Register

(1 of 16)

Sample Instruction:

LD R0, #BASE[R1]

; Where BASE is an 8-bit immediate value

Program Memory

4 LSBs

Value used in

Instruction

OPERAND

INDEX

Base Address

src

Figure 3-7. Indexed Addressing to Register File

ADDRESSING MODES

S3C9234/P9234

3-8

INDEXED ADDRESSING MODE (Continued)

Point to Working

(1 of 8)

LSB Selects

16-Bit
address
added to
offset

dst

OPCODE

Program Memory

XS (OFFSET)

4-Bit Working

Sample Instructions:

LDC

R4, #04H[RR2]

; The values in the program address (RR2 + #04H)
are loaded into register R4.

LDE

R4,#04H[RR2]

; Identical operation to LDC example, except that
external program memory is accessed.

NEXT 3 Bits

Pair

src

8-Bits

16-Bits

Program Memory

Data Memory

OPERAND

Value used in
Instruction

16-Bits

Figure 3-8. Indexed Addressing to Program or Data Memory with Short Offset

S3C9234/P9234

ADDRESSING MODES

3-9

INDEXED ADDRESSING MODE (Concluded)

Point to Working

(1 of 8)

LSB Selects

16-Bit
address
added to
offset

Program Memory

4-Bit Working

Sample Instructions:

LDC

R4, #1000H[RR2]

; The values in the program address (RR2 +

#1000H)

are loaded into register R4.

LDE

R4, #1000H[RR2]

; Identical operation to LDC example, except that
external program memory is accessed.

NEXT 3 Bits

Pair

8-Bits

16-Bits

Program Memory

Data Memory

OPERAND

Value used in
Instruction

16-Bits

OPCODE

(OFFSET)

dst

src

Figure 3-9. Indexed Addressing to Program or Data Memory with Long Offset

ADDRESSING MODES

S3C9234/P9234

3-10

DIRECT ADDRESS MODE (DA)

In Direct Address (DA) mode, the instruction provides the operand's 16-bit memory address. Jump (JP) and Call
(CALL) instructions use this addressing mode to specify the 16-bit destination address that is loaded into the PC
whenever a JP or CALL instruction is executed.

The LDC and LDE instructions can use Direct Address mode to specify the source or destination address for Load
operations to program memory (LDC) or to external data memory (LDE), if implemented.

Sample Instructions:

LDC

R5,1234H

; The values in the program address (1234H)
are loaded into register R5.

LDE

R5,1234H

; Identical operation to LDC example, except that
external program memory is accessed.

dst/src

OPCODE

Program Memory

"0" or "1"

Lower Address Byte

LSB Selects Program
Memory or Data Memory:
"0" = Program Memory
"1" = Data Memory

Memory
Address
Used

Upper Address Byte

Program or

Data Memory

Figure 3-10. Direct Addressing for Load Instructions

ADDRESSING MODES

S3C9234/P9234

3-12

RELATIVE ADDRESS MODE (RA)

In Relative Address (RA) mode, a two's-complement signed displacement between 128 and + 127 is specified in
the instruction. The displacement value is then added to the current PC value. The result is the address of the next
instruction to be executed. Before this addition occurs, the PC contains the address of the instruction immediately
following the current instruction.

The instructions that support RA addressing is JR.

OPCODE

Program Memory

Displacement

Program Memory
Address Used

Sample Instructions:

ULT,$ + OFFSET ; Where OFFSET is a value in the range + 127 to - 128

Next OPCODE

Signed
Displacement Value

Current Instruction

Current

PC Value

Figure 3-12. Relative Addressing

IMMEDIATE MODE (IM)

In Immediate (IM) addressing mode, the operand value used in the instruction is the value supplied in the operand
field itself. Immediate addressing mode is useful for loading constant values into registers.

(The Operand value is in the instruction)

OPCODE

Sample Instruction:

LD R0,#0AAH

Program Memory

OPERAND

Figure 3-13. Immediate Addressing

S3C9234/P9234

CONTROL REGISTERS

4-1

CONTROL REGISTERS

OVERVIEW

In this section, detailed descriptions of the S3C9234/P9234 control registers are presented in an easy-to-read
format. These descriptions will help familiarize you with the mapped locations in the register file. You can also use
them as a quick-reference source when writing application programs.

System and peripheral registers are summarized in Table 4-1. Figure 4-1 illustrates the important features of the
standard register description format.

Control register descriptions are arranged in alphabetical order according to register mnemonic. More information
about control registers is presented in the context of the various peripheral hardware descriptions in Part II of this
manual.

CONTROL REGISTERS

S3C9234/P9234

4-2

Table 4-1. System and Peripheral Control Registers

Register Name

Mnemonic

Address(Page 0)

R/W

RESET

Value(bit)

Decimal

Hex

SIO Control Register

SIOCON

208

D0H

R/W

SIO Data Register

SIODATA

209

D1H

R/W

SIO Prescaler Register

SIOPS

210

D2H

R/W

Oscillator Control Register

OSCCON

211

D3H

R/W

System Clock Control Register

CLKCON

212

D4H

R/W

System Flags Register

FLAGS

213

D5H

R/W

Stop Control Register

STPCON

214

D6H

R/W

LCD Control Register

LCON

215

D7H

R/W

Interrupt Pending Register

INTPND

216

D8H

R/W

Stack Pointer

217

D9H

R/W

Watch Timer Control Register

WTCON

218

DAH

R/W

Location DBH is not mapped.

Basic Timer Control Register

BTCON

220

DCH

R/W

Basic Timer Counter

BTCNT

221

DDH

Location DEH is not mapped.

System Mode Register

SYM

223

DFH

R/W

Port 0 Data Register

224

E0H

R/W

Port 1 Data Register

225

E1H

R/W

Port 2 Data Register

226

E2H

R/W

Port 3 Data Register

227

E3H

R/W

Port 4 Data Register

228

E4H

R/W

Port 5 Data Register

229

E5H

R/W

Port 6 Data Register

230

E6H

R/W

Timer A Counter

TACNT

231

E7H

Timer B Counter

TBCNT

232

E8H

Timer A Data Register

TADATA

233

E9H

R/W

Timer B Data Register

TBDATA

234

EAH

R/W

Timer 1/A Control Register

TACON

235

EBH

R/W

Timer B Control Register

TBCON

236

ECH

R/W

S3C9234/P9234

CONTROL REGISTERS

4-3

Table 4-1. System and Peripheral Control Registers (Continued)

Register Name

Mnemonic

Address(Page 0)

R/W

RESET

Value(bit)

Decimal

Hex

Port 0 Control Register

P0CON

237

EDH

R/W

Port 1 Control Register(High Byte)

P1CONH

238

EEH

R/W

Port 1 Control Register(Low Byte)

P1CONL

239

EFH

R/W

Port 1 Pull-up Resistor Enable
Register

P1PUR

240

F0H

R/W

Port 1 Interrupt Control Register

P1INT

241

F1H

R/W

Port 2 Control Register (High Byte)

P2CONH

242

F2H

R/W

Port 2 Control Register (Low Byte)

P2CONL

243

F3H

R/W

Port 2 Pull-up Resistor Enable
Register

P2PUR

244

F4H

R/W

Port 2 Interrupt Control Register

P2INT

245

F5H

R/W

Port 3 Control Register (High Byte)

P3CONH

246

F6H

R/W

Port 3 Control Register (Low Byte)

P3CONL

247

F7H

R/W

Port 3 Pull-up Resistor Enable
Register

P3PUR

248

F8H

R/W

Port 4 Control Register (High Byte)

P4CONH

249

F9H

R/W

Port 4 Control Register (Low Byte)

P4CONL

250

FAH

R/W

Port 5 Control Register (High Byte)

P5CONH

251

FBH

R/W

Port 5 Control Register (Low Byte)

P5CONL

252

FCH

R/W

Port 6 Control Register

P6CON

253

FDH

R/W

Clock Output Control Register

CLOCON

254

FEH

R/W

Location FFH is not mapped.

NOTES:
1. An "x" means that the bit value is undefined following reset.
2. A dash("-") means that the bit is neither used nor mapped, but the bit is read as "0".

CONTROL REGISTERS

S3C9234/P9234

4-4

FLAGS

- System Flags Register

Bit Identifier

RESET

Value

Read/Write

R = Read-only
W = Write-only
R/W = Read/write
' - ' = Not used

Bit number:
MSB = Bit 7
LSB = Bit 0

Addressing mode or
modes you can use to
modify register values
(1-bit, 4-bit, or 8-bit)

Description of the
effect of specific
bit settings

RESET

value notation:

'-' = Not used
'x' = Undetermind value
'0' = Logic zero
'1' = Logic one

Bit number(s) that is/are appended to the
register name for bit addressing

D5H

(hexadecimal)

Full Register name

mnemonic

Name of individual

bit or bit function

R/W

Carry Flag (C)

Operation dose not generate a carry or borrow condition

Operation generates carry-out or borrow into high-order bit7

Zero Flag

Operation result is a non-zero value

Operation result is zero

Sign Flag

Operation generates positive number (MSB = "0")

Operation generates negative number (MSB = "1")

Figure 4-1. Register Description Format

S3C9234/P9234

CONTROL REGISTERS

4-5

BTCON

-- Basic Timer Control Register

DCH

Bit Identifier

RESET

Value

Read/Write

R/W

.7-.4

Watchdog Timer Function Disable Code (for System Reset)

Disable watchdog timer function

Any other value

Enable watchdog timer function

.3-.2

Basic Timer Clock Selection Bits

fxx/4096

fxx/1024

fxx/128

fxx/16

Basic Timer Counter Clear Bit

No effect

Clear the basic timer counter value
(Automatically cleared to "0" after being cleared basic timer counter)

Clock Frequency Divider Clear Bit for Basic Timer and Timer Counters

No effect

Clear clock frequency dividers
(Automatically cleared to "0" after being cleared clock frequency dividers)

NOTE: The fxx is the selected clock for system (main clock or sub clock).

CONTROL REGISTERS

S3C9234/P9234

4-6

CLKCON

-- System Clock Control Register

D4H

Bit Identifier

RESET

Value

Read/Write

R/W

Oscillator IRQ Wake-up Function Enable Bit

Enable IRQ for main oscillator wake-up function

Disable IRQ for main oscillator wake-up function

.6-.5

Bits 6-5

Always logic zero

.4-.3

CPU Clock (System Clock) Frequency Selection Bits

Select fxx/16

Select fxx/8

Select fxx/2

Non-divided clock (fxx)

.2-.0

Bits 2-0

Always logic zero

CONTROL REGISTERS

S3C9234/P9234

4-8

FLAGS

-- System Flags Register

D5H

Bit Identifier

RESET

Value

Read/Write

R/W

Carry Flag (C)

Operation does not generate a carry or borrow condition

Operation generates a carry-out or borrow into high-order bit 7

Zero Flag (Z)

Operation result is a non-zero value

Operation result is zero

Sign Flag (S)

Operation generates a positive number (MSB = "0")

Operation generates a negative number (MSB = "1")

Overflow Flag (V)

Operation result is

+127 or

128

Operation result is

+127 or

128

.3-.0

Not used for S3C9234/P9234.

S3C9234/P9234

CONTROL REGISTERS

4-9

INTPND

-- Interrupt Pending Register

D8H

Bit Identifier

RESET

Value

Read/Write

R/W

P2.7's Interrupt Pending Bit

No interrupt pending (when read), Clear pending bit (when write)

Interrupt is pending (when read)

P2.6's Interrupt Pending Bit

No interrupt pending (when read), Clear pending bit (when write)

Interrupt is pending (when read)

P2.5's Interrupt Pending Bit

No interrupt pending (when read), Clear pending bit (when write)

Interrupt is pending (when read)

P2.4's Interrupt Pending Bit

No interrupt pending (when read), Clear pending bit (when write)

Interrupt is pending (when read)

Not used for S3C9234/P9234.

P1.2's Interrupt Pending Bit

No interrupt pending (when read), Clear pending bit (when write)

Interrupt is pending (when read)

P1.1's Interrupt Pending Bit

No interrupt pending (when read), Clear pending bit (when write)

Interrupt is pending (when read)

P1.0's Interrupt Pending Bit

No interrupt pending (when read), Clear pending bit (when write)

Interrupt is pending (when read)

CONTROL REGISTERS

S3C9234/P9234

4-10

LCON

-- LCD Control Register

D7H

Bit Identifier

RESET

Value

Read/Write

R/W

Internal LCD Dividing Resistors Enable Bit

Enable internal LCD dividing resistors

Disable internal LCD dividing resistors

.6-.5

LCD Clock Selection Bits

fw/2

(64 Hz)

fw/2

(128 Hz)

fw/2

(256 Hz)

fw/2

(512 Hz)

.4-.2

LCD Duty and Bias Selection Bits

1/4duty, 1/3bias

1/3duty, 1/3bias

1/3duty, 1/2bias

1/2duty, 1/2bias

Static

Not used for S3C9234/P9234.

LCD Display Control Bits

All LCD signals are low (Turn off the P-Tr)

Turn display on (Turn on the P-Tr)

NOTE: "x" means don't care.

S3C9234/P9234

CONTROL REGISTERS

4-11

OSCCON

-- Oscillator Control Register

D3H

Bit Identifier

RESET

Value

Read/Write

R/W

.7-.4

Not used for S3C9234/P9234.

Main Oscillator Control Bit

Main oscillator RUN

Main oscillator STOP

Sub Oscillator Control Bit

Sub oscillator RUN

Sub oscillator STOP

Not used for S3C9234/P9234.

System Clock Selection Bit

Select main oscillator for system clock

Select sub oscillator for system clock

CONTROL REGISTERS

S3C9234/P9234

4-12

P0CON

 Port 0 Control Register

EDH

Bit Identifier

RESET

Value

Read/Write

R/W

.7-.6

P0.3/COM3 Configuration Bits

Input mode

Input with pull-up resistor

Push-pull output mode

Alternative function (COM3)

.5-.4

P0.2/COM2 Configuration Bits

Input mode

Input with pull-up resistor

Push-pull output mode

Alternative function (COM2)

.3-.2

P0.1/COM1 Configuration Bits

Input mode

Input with pull-up resistor

Push-pull output mode

Alternative function (COM1)

.1-.0

P0.0/COM0 Configuration Bits

Input mode

Input with pull-up resistor

Push-pull output mode

Alternative function (COM0)

S3C9234/P9234

CONTROL REGISTERS

4-13

P1CONH

-- Port 1 Control Register High Byte

EEH

Bit Identifier

RESET

Value

Read/Write

R/W

.7-.6

P1.7/BUZ Configuration Bits

Schmitt trigger input mode

N-channel open-drain output mode

Push-pull output mode

Alternative function (BUZ)

.5-.4

P1.6/CLKOUT Configuration Bits

Schmitt trigger input mode

N-channel open-drain output mode

Push-pull output mode

Alternative function (CLKOUT)

.3-.2

P1.5/TBOUT Configuration Bits

Schmitt trigger input mode

N-channel open-drain output mode

Push-pull output mode

Alternative function (TBOUT)

.1-.0

P1.4/TAOUT Configuration Bits

Schmitt trigger input mode

N-channel open-drain output mode

Push-pull output mode

Alternative function (TAOUT)

CONTROL REGISTERS

S3C9234/P9234

4-14

P1CONL

 Port 1 Control Register Low Byte

EFH

Bit Identifier

RESET

Value

Read/Write

R/W

.7-.6

P1.3/T1CLK Configuration Bits

Schmitt trigger input mode (T1CLK)

N-channel open-drain output mode

Push-pull output mode

Not available

.5-.4

P1.2/INT Configuration Bits

Schmitt trigger input mode

N-channel open-drain output mode

Push-pull output mode

Not available

.3-.2

P1.1/INT Configuration Bits

Schmitt trigger input mode

N-channel open-drain output mode

Push-pull output mode

Not available

.1-.0

P1.0/INT Configuration Bits

Schmitt trigger input mode

N-channel open-drain output mode

Push-pull output mode

Not available

S3C9234/P9234

CONTROL REGISTERS

4-15

P1INT

Port 1 Interrupt Enable Register

F1H

Bit Identifier

RESET

Value

Read/Write

R/W

.7-.6

Not used for S3C9234/P9234.

.5-.4

P1.2/INT External Interrupt Configuration Bits

Disable interrupt

Enable interrupt by falling edge

Enable interrupt by rising edge

Enable interrupt by both falling and rising edge

.3-.2

P1.1/INT External Interrupt Configuration Bits

Disable interrupt

Enable interrupt by falling edge

Enable interrupt by rising edge

Enable interrupt by both falling and rising edge

.1-.0

P1.0/INT External Interrupt Configuration Bits

Disable interrupt

Enable interrupt by falling edge

Enable interrupt by rising edge

Enable interrupt by both falling and rising edge

CONTROL REGISTERS

S3C9234/P9234

4-16

P1PUR

Port 1 Pull-up Resistors Enable Register

F0H

Bit Identifier

RESET

Value

Read/Write

R/W

P1.7's Pull-up Resistor Enable Bit

Disable pull-up resistor

Enable pull-up resistor

P1.6's Pull-up Resistor Enable Bit

Disable pull-up resistor

Enable pull-up resistor

P1.5's Pull-up Resistor Enable Bit

Disable pull-up resistor

Enable pull-up resistor

P1.4's Pull-up Resistor Enable Bit

Disable pull-up resistor

Enable pull-up resistor

P1.3's Pull-up Resistor Enable Bit

Disable pull-up resistor

Enable pull-up resistor

P1.2's Pull-up Resistor Enable Bit

Disable pull-up resistor

Enable pull-up resistor

P1.1's Pull-up Resistor Enable Bit

Disable pull-up resistor

Enable pull-up resistor

P1.0's Pull-up Resistor Enable Bit

Disable pull-up resistor

Enable pull-up resistor

NOTE: A pull-up resistor of port1 is automatically disabled when the corresponding pin is selected as push-pull

output or alternative function.

S3C9234/P9234

CONTROL REGISTERS

4-17

P2CONH

Port 2 Control Register High Byte

F2H

Bit Identifier

RESET

Value

Read/Write

R/W

.7-.6

P2.7/INT Configuration Bits

Schmitt trigger input mode

N-channel open-drain output mode

Push-pull output mode

Not available

.5-.4

P2.6/INT Configuration Bits

Schmitt trigger input mode

N-channel open-drain output mode

Push-pull output mode

Not available

.3-.2

P2.5/INT Configuration Bits

Schmitt trigger input mode

N-channel open-drain output mode

Push-pull output mode

Not available

.1-.0

P2.4/INT Configuration Bits

Schmitt trigger input mode

N-channel open-drain output mode

Push-pull output mode

Not available

CONTROL REGISTERS

S3C9234/P9234

4-18

P2CONL

 Port 2 Control Register Low Byte

F3H

Bit Identifier

RESET

Value

Read/Write

R/W

.7-.6

P2.3 Configuration Bits

Schmitt trigger input mode

N-channel open-drain output mode

Push-pull output mode

Not available

.5-.4

P2.2/SI Configuration Bits

Schmitt trigger input mode (SI)

N-channel open-drain output mode

Push-pull output mode

Not available

.3-.2

P2.1/SO Configuration Bits

Schmitt trigger input mode

N-channel open-drain output mode

Push-pull output mode

Alternative function (SO)

.1-.0

P2.0/SCK Configuration Bits

Schmitt trigger input mode (SCK)

N-channel open-drain output mode

Push-pull output mode

Alternative function (SCK)

S3C9234/P9234

CONTROL REGISTERS

4-19

P2INT

-- Port 2 Interrupt Enable Register

F5H

Bit Identifier

RESET

Value

Read/Write

R/W

P2.7/INT External Interrupt Edge Selection Bit

Select falling edge

Select rising edge

P2.7/INT External Interrupt Enable Bit

Disable interrupt

Enable interrupt

P2.6/INT External Interrupt Edge Selection Bit

Select falling edge

Select rising edge

P2.6/INT External Interrupt Enable Bit

Disable interrupt

Enable interrupt

P2.5/INT External Interrupt Edge Selection Bit

Select falling edge

Select rising edge

P2.5/INT External Interrupt Enable Bit

Disable interrupt

Enable interrupt

P2.4/INT External Interrupt Edge Selection Bit

Select falling edge

Select rising edge

P2.4/INT External Interrupt Enable Bit

Disable interrupt

Enable interrupt

CONTROL REGISTERS

S3C9234/P9234

4-20

P2PUR

Port 2 Pull-up Resistors Enable Register

F4H

Bit Identifier

RESET

Value

Read/Write

R/W

P2.7's Pull-up Resistor Enable Bit

Disable pull-up resistor

Enable pull-up resistor

P2.6's Pull-up Resistor Enable Bit

Disable pull-up resistor

Enable pull-up resistor

P2.5's Pull-up Resistor Enable Bit

Disable pull-up resistor

Enable pull-up resistor

P2.4's Pull-up Resistor Enable Bit

Disable pull-up resistor

Enable pull-up resistor

P2.3's Pull-up Resistor Enable Bit

Disable pull-up resistor

Enable pull-up resistor

P2.2's Pull-up Resistor Enable Bit

Disable pull-up resistor

Enable pull-up resistor

P2.1's Pull-up Resistor Enable Bit

Disable pull-up resistor

Enable pull-up resistor

P2.0's Pull-up Resistor Enable Bit

Disable pull-up resistor

Enable pull-up resistor

NOTE: A pull-up resistor of port 2 is automatically disabled when the corresponding pin is selected as push-pull output or

alternative function.

S3C9234/P9234

CONTROL REGISTERS

4-21

P3CONH

 Port 3 Control Register High Byte

F6H

Bit Identifier

RESET

Value

Read/Write

R/W

.7-.6

P3.7/SEG24 Configuration Bits

Input mode

N-channel open-drain output mode

Push-pull output mode

Alternative function (SEG24)

.5-.4

P3.6/SEG25 Configuration Bits

Input mode

N-channel open-drain output mode

Push-pull output mode

Alternative function (SEG25)

.3-.2

P3.5/SEG26 Configuration Bits

Input mode

N-channel open-drain output mode

Push-pull output mode

Alternative function (SEG26)

.1-.0

P3.4/SEG27 Configuration Bits

Input mode

N-channel open-drain output mode

Push-pull output mode

Alternative function (SEG27)

CONTROL REGISTERS

S3C9234/P9234

4-22

P3CONL

Port 3 Control Register Low Byte

F7H

Bit Identifier

RESET

Value

Read/Write

R/W

.7-.6

P3.3/SEG28 Configuration Bits

Input mode

N-channel open-drain output mode

Push-pull output mode

Alternative function (SEG28)

.5-.4

P3.2/SEG29 Configuration Bits

Input mode

N-channel open-drain output mode

Push-pull output mode

Alternative function (SEG29)

.3-.2

P3.1/SEG30 Configuration Bits

Input mode

N-channel open-drain output mode

Push-pull output mode

Alternative function (SEG30)

.1-.0

P3.0/SEG31 Configuration Bits

Input mode

N-channel open-drain output mode

Push-pull output mode

Alternative function (SEG31)

S3C9234/P9234

CONTROL REGISTERS

4-23

P3PUR

Port 3 Pull-up Resistors Enable Register

F8H

Bit Identifier

RESET

Value

Read/Write

R/W

P3.7's Pull-up Resistor Enable Bit

Disable pull-up resistor

Enable pull-up resistor

P3.6's Pull-up Resistor Enable Bit

Disable pull-up resistor

Enable pull-up resistor

P3.5's Pull-up Resistor Enable Bit

Disable pull-up resistor

Enable pull-up resistor

P3.4's Pull-up Resistor Enable Bit

Disable pull-up resistor

Enable pull-up resistor

P3.3's Pull-up Resistor Enable Bit

Disable pull-up resistor

Enable pull-up resistor

P3.2's Pull-up Resistor Enable Bit

Disable pull-up resistor

Enable pull-up resistor

P3.1's Pull-up Resistor Enable Bit

Disable pull-up resistor

Enable pull-up resistor

P3.0's Pull-up Resistor Enable Bit

Disable pull-up resistor

Enable pull-up resistor

NOTE: A pull-up resistor of port3 is automatically disabled when the corresponding pin is selected as push-pull

output or alternative function.

CONTROL REGISTERS

S3C9234/P9234

4-24

P4CONH

 Port 4 Control Register High Byte

F9H

Bit Identifier

RESET

Value

Read/Write

R/W

.7-.6

P4.7/SEG16 Configuration Bits

Input mode

Input with pull-up resistor

Push-pull output mode

Alternative function (SEG16)

.5-.4

P4.6/SEG17 Configuration Bits

Input mode

Input with pull-up resistor

Push-pull output mode

Alternative function (SEG17)

.3-.2

P4.5/SEG18 Configuration Bits

Input mode

Input with pull-up resistor

Push-pull output mode

Alternative function (SEG18)

.1-.0

P4.4/SEG19 Configuration Bits

Input mode

Input with pull-up resistor

Push-pull output mode

Alternative function (SEG19)

S3C9234/P9234

CONTROL REGISTERS

4-25

P4CONL

Port 4 Control Register Low Byte

FAH

Bit Identifier

RESET

Value

Read/Write

R/W

.7-.6

P4.3/SEG20 Configuration Bits

Input mode

Input with pull-up resistor

Push-pull output mode

Alternative function (SEG20)

.5-.4

P4.2/SEG21 Configuration Bits

Input mode

Input with pull-up resistor

Push-pull output mode

Alternative function (SEG21)

.3-.2

P4.1/SEG22 Configuration Bits

Input mode

Input with pull-up resistor

Push-pull output mode

Alternative function (SEG22)

.1-.0

P4.0/SEG23 Configuration Bits

Input mode

Input with pull-up resistor

Push-pull output mode

Alternative function (SEG23)

CONTROL REGISTERS

S3C9234/P9234

4-26

P5CONH

 Port 5 Control Register High Byte

FBH

Bit Identifier

RESET

Value

Read/Write

R/W

.7-.6

P5.7/SEG8 Configuration Bits

Input mode

Input with pull-up resistor

Push-pull output mode

Alternative function (SEG8)

.5-.4

P5.6/SEG9 Configuration Bits

Input mode

Input with pull-up resistor

Push-pull output mode

Alternative function (SEG9)

.3-.2

P5.5/SEG10 Configuration Bits

Input mode

Input with pull-up resistor

Push-pull output mode

Alternative function (SEG10)

.1-.0

P5.4/SEG11 Configuration Bits

Input mode

Input with pull-up resistor

Push-pull output mode

Alternative function (SEG11)

S3C9234/P9234

CONTROL REGISTERS

4-27

P5CONL

 Port 5 Control Register Low Byte

FCH

Bit Identifier

RESET

Value

Read/Write

R/W

.7-.6

P5.3/SEG12 Configuration Bits

Input mode

Input with pull-up resistor

Push-pull output mode

Alternative function (SEG12)

.5-.4

P5.2/SEG13 Configuration Bits

Input mode

Input with pull-up resistor

Push-pull output mode

Alternative function (SEG13)

.3-.2

P5.1/SEG14 Configuration Bits

Input mode

Input with pull-up resistor

Push-pull output mode

Alternative function (SEG14)

.1-.0

P5.0/SEG15 Configuration Bits

Input mode

Input with pull-up resistor

Push-pull output mode

Alternative function (SEG15)

CONTROL REGISTERS

S3C9234/P9234

4-28

P6CON

 Port 6 Control Register

FDH

Bit Identifier

RESET

Value

Read/Write

R/W

.7-.6

P6.7-P6.6/SEG0-SEG1 Configuration Bits

Input mode

Input with pull-up resistor

Push-pull output mode

Alternative function (SEG0-SEG1)

.5-.4

P6.5-P6.4/SEG2-SEG3 Configuration Bits

Input mode

Input with pull-up resistor

Push-pull output mode

Alternative function (SEG2-SEG3)

.3-.2

P6.3-P6.2/SEG4-SEG5 Configuration Bits

Input mode

Input with pull-up resistor

Push-pull output mode

Alternative function (SEG4-SEG5)

.1-.0

P6.1-P6.0/SEG6-SEG7 Configuration Bits

Input mode

Input with pull-up resistor

Push-pull output mode

Alternative function (SEG6-SEG7)

S3C9234/P9234

CONTROL REGISTERS

4-29

SIOCON

-- SIO Control Register

D0H

Bit Identifier

RESET

Value

Read/Write

R/W

SIO Shift Clock Selection Bit

Internal clock (P.S clock)

External clock (SCK)

Data Direction Control Bit

MSB-first mode

LSB-first mode

SIO Mode Selection Bit

Receive-only mode

Transmit/Receive mode

Shift Clock Edge Selection Bit

Tx at falling edges, Rx at rising edges

Tx at rising edges, Rx at falling edges

SIO Counter Clear and Shift Start Bit

No action

Clear 3-bit counter and start shifting

SIO Shift Operation Enable Bit

Disable shifter and clock counter

Enable shifter and clock counter

SIO Interrupt Enable Bit

Disable SIO interrupt

Enable SIO interrupt

SIO Interrupt Pending Bit

No interrupt pending (when read), Clear pending bit (when write)

Interrupt is pending (when read)

CONTROL REGISTERS

S3C9234/P9234

4-32

TACON

-- Timer 1/A Control Register

EBH

Bit Identifier

RESET

Value

Read/Write

R/W

Timer 1 Mode Selection Bit

Two 8-bit timers mode (Timer A/B)

One 16-bit timer mode (Timer 1)

.6-.4

Timer 1/A Clock Selection Bits

fxx/512

fxx/256

fxx/64

fxx/8

fxx (system clock)

fxt (sub clock)

T1CLK (external clock)

Not available

Timer 1/A Counter Clear Bit

No effect

Clear the timer 1/A counter (when write)

Timer 1/A Counter Enable Bit

Disable counting operation

Enable counting operation

Timer 1/A Interrupt Enable Bit

Disable interrupt

Enable interrupt

Timer 1/A Interrupt Pending Bit

No interrupt pending bit (when read), Clear pending bit (when write)

Interrupt is pending (when read)

S3C9234/P9234

CONTROL REGISTERS

4-33

TBCON

-- Timer B Control Register

ECH

Bit Identifier

RESET

Value

Read/Write

R/W

Not used for S3C9234/P9234.

.6-.4

Timer B Clock Selection Bits

fxx/512

fxx/256

fxx/64

fxx/8

fxt (sub clock)

Timer B Counter Clear Bit

No effect

Clear the timer B counter (when write)

Timer B Counter Enable Bit

Disable counting operation

Enable counting operation

Timer B Interrupt Enable Bit

Disable interrupt

Enable interrupt

Timer B Interrupt Pending Bit

No interrupt pending (when read), Clear pending bit (when write)

Interrupt is pending (when read)

CONTROL REGISTERS

S3C9234/P9234

4-34

WTCON

-- Watch Timer Control Register

DAH

Bit Identifier

RESET

Value

Read/Write

R/W

Watch Timer Clock Selection Bit

Select main clock divided by 2

(fx/128)

Select sub clock (fxt)

Watch Timer Interrupt Enable Bit

Disable watch timer interrupt

Enable watch timer interrupt

.5-.4

Buzzer Signal Selection Bits

0.5 kHz

1 kHz

2 kHz

4 kHz

.3-.2

Watch Timer Speed Selection Bits

Set watch timer interrupt to 1s

Set watch timer interrupt to 0.5s

Set watch timer interrupt to 0.25s

Set watch timer interrupt to 3.91ms

Watch Timer Enable Bit

Disable watch timer; Clear frequency dividing circuits

Enable watch timer

Watch Timer Interrupt Pending Bit

No interrupt pending (when read), Clear pending bit (when write)

Interrupt is pending (when read)

S3C9234/P9234

INTERRUPT STRUCTURE

5-1

INTERRUPT STRUCTURE

OVERVIEW

The SAM88RCRI interrupt structure has two basic components: a vector, and sources. The number of interrupt
sources can be serviced through a interrupt vector which is assigned in ROM address 0000H0001H.

SOURCES

VECTOR

0000H
0001H

NOTES:
1. The SAM88RCRI interrupt has only one vector address (0000H-0001H).
2. The number of Sn value is expandable.

Figure 5-1. S3C9-Series Interrupt Type

INTERRUPT PROCESSING CONTROL POINTS

Interrupt processing can be controlled in two ways: globally, or by specific interrupt level and source. The system-
level control points in the interrupt structure are therefore:

-- Global interrupt enable and disable (by EI and DI instructions)

-- Interrupt source enable and disable settings in the corresponding peripheral control register(s)

ENABLE/DISABLE INTERRUPT INSTRUCTIONS (EI, DI)

The system mode register, SYM (DFH), is used to enable and disable interrupt processing.

SYM.3 is the enable and disable bit for global interrupt processing, which you can set by modifying SYM.3. An
Enable Interrupt (EI) instruction must be included in the initialization routine that follows a reset operation in order to
enable interrupt processing. Although you can manipulate SYM.3 directly to enable and disable interrupts during
normal operation, we recommend that you use the EI and DI instructions for this purpose.

INTERRUPT STRUCTURE

S3C9234/P9234

5-2

INTERRUPT PENDING FUNCTION TYPES

When the interrupt service routine has executed, the application program's service routine must clear the appropriate
pending bit before the return from interrupt subroutine (IRET) occurs.

INTERRUPT PRIORITY

Because there is not a interrupt priority register in SAM87RCRI, the order of service is determined by a sequence of
source which is executed in interrupt service routine.

Interrupt Pending

Global Interrupt

Control (EI, Di instruction)

Vector
Interrupt
Cycle

Interrpt priority

is determind by

software polling

method

"EI" Instruction

Execution

RESET

Source

Interrupts

Source

Interrupt

Enable

Figure 5-2. Interrupt Function Diagram

S3C9234/P9234

INTERRUPT STRUCTURE

5-3

INTERRUPT SOURCE SERVICE SEQUENCE

The interrupt request polling and servicing sequence is as follows:

1. A source generates an interrupt request by setting the interrupt request pending bit to "1".

2. The CPU generates an interrupt acknowledge signal.

3. The service routine starts and the source's pending flag is cleared to "0" by software.

4. Interrupt priority must be determined by software polling method.

INTERRUPT SERVICE ROUTINES

Before an interrupt request can be serviced, the following conditions must be met:

-- Interrupt processing must be enabled (EI, SYM.3 = "1")

-- Interrupt must be enabled at the interrupt's source (peripheral control register)

If all of the above conditions are met, the interrupt request is acknowledged at the end of the instruction cycle. The
CPU then initiates an interrupt machine cycle that completes the following processing sequence:

1. Reset (clear to "0") the global interrupt enable bit in the SYM register (DI, SYM.3 = "0")

to disable all subsequent interrupts.

2. Save the program counter and status flags to stack.

3. Branch to the interrupt vector to fetch the service routine's address.

4. Pass control to the interrupt service routine.

When the interrupt service routine is completed, an Interrupt Return instruction (IRET) occurs. The IRET restores the
PC and status flags and sets SYM.3 to "1"(EI), allowing the CPU to process the next interrupt request.

GENERATING INTERRUPT VECTOR ADDRESSES

The interrupt vector area in the ROM contains the address of the interrupt service routine. Vectored interrupt
processing follows this sequence:

1. Push the program counter's low-byte value to stack.

2. Push the program counter's high-byte value to stack.

3. Push the FLAGS register values to stack.

4. Fetch the service routine's high-byte address from the vector address 0000H.

5. Fetch the service routine's low-byte address from the vector address 0001H.

6. Branch to the service routine specified by the 16-bit vector address.

S3C9234/P9234

INTERRUPT STRUCTURE

5-5

SYM.3

(EI, DI)

P1INT.0

P1.0 External Interript

P1INT.1

P1.1 External Interript

P1.2 External Interript

P1INT.2

INTPND.0

INTPND.1

INTPND.2

P2.4 External Interript

P2INT.4

P2.6 External Interript

P2.7 External Interrupt

P2.5 External Interript

P2INT.5

P2INT.6

P2INT.7

TACON.1

TBCON.1

INTPND.4

INTPND.5

INTPND.6

INTPND.7

TACON.0

TBCON.0

SIOCON.1

WTCON.6

SIOCON.0

WTCON.0

0000H
0001H

Vector

Enable/Disable

Pending

Sources

Timer B Interrupt

Timer 1/A Interrupt

Watch Timer Interrupt

SIO Interrupt

Figure 5-3. S3C9234/P9234 Interrupt Structure

S3C9234/P9234

SAM88RCRI INSTRUCTION SET

6-1

SAM88RCRI INSTRUCTION SET

OVERVIEW

The SAM88RCRI instruction set is designed to support the large register file. It includes a full complement of 8-bit
arithmetic and logic operations. There are 41 instructions. No special I/O instructions are necessary because I/O
control and data registers are mapped directly into the register file. Flexible instructions for bit addressing, rotate, and
shift operations complete the powerful data manipulation capabilities of the SAM88RCRI instruction set.

REGISTER ADDRESSING

To access an individual register, an 8-bit address in the range 0-255 or the 4-bit address of a working register is
specified. Paired registers can be used to construct 16-bit program memory or data memory addresses. For detailed
information about register addressing, please refer to Section 2, "Address Spaces".

ADDRESSING MODES

There are six addressing modes: Register (R), Indirect Register (IR), Indexed (X), Direct (DA), Relative (RA), and
Immediate (IM). For detailed descriptions of these addressing modes, please refer to Section 3, "Addressing Modes".

SAM88RI INSTRUCTION SET

S3C9234/P9234

6-2

Table 6-1. Instruction Group Summary

Mnemonic

Operands

Instruction

Load Instructions

CLR

dst

Clear

dst,src

Load

LDC

dst,src

Load program memory

LDE

dst,src

Load external data memory

LDCD

dst,src

Load program memory and decrement

LDED

dst,src

Load external data memory and decrement

LDCI

dst,src

Load program memory and increment

LDEI

dst,src

Load external data memory and increment

POP

dst

Pop from stack

PUSH

src

Push to stack

Arithmetic Instructions

ADC

dst,src

Add with carry

ADD

dst,src

Add

dst,src

Compare

DEC

dst

Decrement

INC

dst

Increment

SBC

dst,src

Subtract with carry

SUB

dst,src

Subtract

Logic Instructions

AND

dst,src

Logical AND

COM

dst

Complement

dst,src

Logical OR

XOR

dst,src

Logical exclusive OR

S3C9234/P9234

SAM88RCRI INSTRUCTION SET

6-3

Table 6-1. Instruction Group Summary (Continued)

Mnemonic

Operands

Instruction

Program Control Instructions

CALL

dst

Call procedure

IRET

Interrupt return

cc,dst

Jump on condition code

dst

Jump unconditional

cc,dst

Jump relative on condition code

RET

Return

Bit Manipulation Instructions

TCM

dst,src

Test complement under mask

dst,src

Test under mask

Rotate and Shift Instructions

dst

Rotate left

RLC

dst

Rotate left through carry

dst

Rotate right

RRC

dst

Rotate right through carry

SRA

dst

Shift right arithmetic

CPU Control Instructions

CCF

Complement carry flag

Disable interrupts

Enable interrupts

IDLE

Enter Idle mode

NOP

No operation

RCF

Reset carry flag

SCF

Set carry flag

STOP

Enter Stop mode

SAM88RI INSTRUCTION SET

S3C9234/P9234

6-4

FLAGS REGISTER (FLAGS)

The FLAGS register contains eight bits that describe the current status of CPU operations. Four of these bits,
FLAGS.4 FLAGS.7, can be tested and used with conditional jump instructions;

FLAGS register can be set or reset by instructions as long as its outcome does not affect the flags, such as, Load
instruction. Logical and Arithmetic instructions such as, AND, OR, XOR, ADD, and SUB can affect the Flags register.
For example, the AND instruction updates the Zero, Sign and Overflow flags based on the outcome of the AND
instruction. If the AND instruction uses the Flags register as the destination, then simultaneously, two write will occur
to the Flags register producing an unpredictable result.

LSB

MSB

System Flags Register (FLAGS)

D5H, R/W

Not mapped

Carry flag (C)

Zero flag (Z)

Sign flag (S)

Overflow flag (V)

Figure 6-1. System Flags Register (FLAGS)

FLAG DESCRIPTIONS

Overflow Flag (FLAGS.4, V)

The V flag is set to "1" when the result of a two's-complement operation is greater than + 127 or less than 128. It is
also cleared to "0" following logic operations.

Sign Flag (FLAGS.5, S)

Following arithmetic, logic, rotate, or shift operations, the sign bit identifies the state of the MSB of the result. A logic
zero indicates a positive number and a logic one indicates a negative number.

Zero Flag (FLAGS.6, Z)

For arithmetic and logic operations, the Z flag is set to "1" if the result of the operation is zero. For operations that
test register bits, and for shift and rotate operations, the Z flag is set to "1" if the result is logic zero.

Carry Flag (FLAGS.7, C)

The C flag is set to "1" if the result from an arithmetic operation generates a carry-out from or a borrow to the bit 7
position (MSB). After rotate and shift operations, it contains the last value shifted out of the specified register.
Program instructions can set, clear, or complement the carry flag.

S3C9234/P9234

SAM88RCRI INSTRUCTION SET

6-5

INSTRUCTION SET NOTATION

Table 6-2. Flag Notation Conventions

Flag

Description

Carry flag

Zero flag

Sign flag

Overflow flag

Cleared to logic zero

Set to logic one

Set or cleared according to operation

Value is unaffected

Value is undefined

Table 6-3. Instruction Set Symbols

Symbol

Description

dst

Destination operand

src

Source operand

Indirect register address prefix

Program counter

FLAGS

Flags register (D5H)

Immediate operand or register address prefix

Hexadecimal number suffix

Decimal number suffix

Binary number suffix

opc

Opcode

SAM88RI INSTRUCTION SET

S3C9234/P9234

6-6

Table 6-4. Instruction Notation Conventions

Notation

Description

Actual Operand Range

Condition code

See list of condition codes in Table 6-6.

Working register only

Rn (n = 015)

Working register pair

RRp (p = 0, 2, 4, ..., 14)

reg or Rn (reg = 0255, n = 015)

reg or RRp (reg = 0254, even number only, where
p = 0, 2, ..., 14)

Indirect working register only

@Rn (n = 015)

Indirect register or indirect working register

@Rn or @reg (reg = 0255, n = 015)

Irr

Indirect working register pair only

@RRp (p = 0, 2, ..., 14)

IRR

Indirect register pair or indirect working
register pair

@RRp or @reg (reg = 0254, even only, where
p = 0, 2, ..., 14)

Indexed addressing mode

#reg[Rn] (reg = 0255, n = 015)

Indexed (short offset) addressing mode

#addr[RRp] (addr = range 128 to +127, where
p = 0, 2, ..., 14)

Indexed (long offset) addressing mode

#addr [RRp] (addr = range 08191, where
p = 0, 2, ..., 14)

Direct addressing mode

addr (addr = range 08191)

Relative addressing mode

addr (addr = number in the range +127 to 128 that is
an offset relative to the address of the next instruction)

Immediate addressing mode

#data (data = 0255)

S3C9234/P9234

SAM88RCRI INSTRUCTION SET

6-7

Table 6-5. Opcode Quick Reference

OPCODE MAP

LOWER NIBBLE (HEX)

DEC

IR1

ADD
r1,r2

ADD

r1,Ir2

ADD

R2,R1

ADD

IR2,R1

ADD

R1,IM

RLC

IR1

ADC
r1,r2

ADC

r1,Ir2

ADC

R2,R1

ADC

IR2,R1

ADC

R1,IM

INC

IR1

SUB
r1,r2

SUB

r1,Ir2

SUB

R2,R1

SUB

IR2,R1

SUB

R1,IM

IRR1

SBC
r1,r2

SBC

r1,Ir2

SBC

R2,R1

SBC

IR2,R1

SBC

R1,IM

r1,r2

r1,Ir2

R2,R1

IR2,R1

R1,IM

POP

IR1

AND
r1,r2

AND

r1,Ir2

AND

R2,R1

AND

IR2,R1

AND

R1,IM

COM

IR1

TCM
r1,r2

TCM

r1,Ir2

TCM

R2,R1

TCM

IR2,R1

TCM

R1,IM

PUSH

IR2

r1,r2

r1,Ir2

R2,R1

IR2,R1

R1,IM

r1, x, r2

RL
R1

IR1

r2, x, r1

r1,r2

r1,Ir2

R2,R1

IR2,R1

R1,IM

LDC

r1, Irr2, xL

CLR

IR1

XOR
r1,r2

XOR

r1,Ir2

XOR

R2,R1

XOR

IR2,R1

XOR

R1,IM

LDC

r2, Irr2, xL

RRC

IR1

LDC

r1,Irr2

r1, Ir2

SRA

IR1

LDC

r2,Irr1

IR1,IM

Ir1, r2

RR
IR1

LDCD

r1,Irr2

LDCI

r1,Irr2

R2,R1

R2,IR1

R1,IM

LDC

r1, Irr2, xs

CALL

IRR1

IR2,R1

CALL

DA1

LDC

r2, Irr1, xs

S3C9234/P9234

SAM88RCRI INSTRUCTION SET

6-9

CONDITION CODES

The opcode of a conditional jump always contains a 4-bit field called the condition code (cc). This specifies under
which conditions it is to execute the jump. For example, a conditional jump with the condition code for "equal" after a
compare operation only jumps if the two operands are equal. Condition codes are listed in Table 6-6.

The carry (C), zero (Z), sign (S), and overflow (V) flags are used to control the operation of conditional jump
instructions.

Table 6-6. Condition Codes

Binary

Mnemonic

Description

Flags Set

0000

Always false

1000

Always true

0111

(1)

Carry

C = 1

1111

(1)

No carry

C = 0

0110

(1)

Zero

Z = 1

1110

(1)

Not zero

Z = 0

1101

Plus

S = 0

0101

Minus

S = 1

0100

Overflow

V = 1

1100

NOV

No overflow

V = 0

0110

(1)

Equal

Z = 1

1110

(1)

Not equal

Z = 0

1001

Greater than or equal

(S XOR V) = 0

0001

Less than

(S XOR V) = 1

1010

Greater than

(Z OR (S XOR V)) = 0

0010

Less than or equal

(Z OR (S XOR V)) = 1

1111

(1)

UGE

Unsigned greater than or equal

C = 0

0111

(1)

ULT

Unsigned less than

C = 1

1011

UGT

Unsigned greater than

(C = 0 AND Z = 0) = 1

0011

ULE

Unsigned less than or equal

(C OR Z) = 1

NOTES:
1.

Indicate condition codes that are related to two different mnemonics but which test the same flag.
For example, Z and EQ are both true if the zero flag (Z) is set, but after an ADD instruction, Z would probably be used;
after a CP instruction, however, EQ would probably be used.

For operations involving unsigned numbers, the special condition codes UGE, ULT, UGT, and ULE must be used.

SAM88RI INSTRUCTION SET

S3C9234/P9234

6-10

INSTRUCTION DESCRIPTIONS

This section contains detailed information and programming examples for each instruction in the SAM88RCRI
instruction set. Information is arranged in a consistent format for improved readability and for fast referencing. The
following information is included in each instruction description:

-- Instruction name (mnemonic)

-- Full instruction name

-- Source/destination format of the instruction operand

-- Shorthand notation of the instruction's operation

-- Textual description of the instruction's effect

-- Specific flag settings affected by the instruction

-- Detailed description of the instruction's format, execution time, and addressing mode(s)

-- Programming example(s) explaining how to use the instruction

S3C9234/P9234

SAM88RCRI INSTRUCTION SET

6-11

ADC

-- Add With Carry

ADC

dst,src

Operation:

dst ¨ dst + src + c

The source operand, along with the setting of the carry flag, is added to the destination operand and
the sum is stored in the destination. The contents of the source are unaffected. Two's-complement
addition is performed. In multiple precision arithmetic, this instruction permits the carry from the
addition of low-order operands to be carried into the addition of high-order operands.

Flags:

C: Set if there is a carry from the most significant bit of the result; cleared otherwise.
Z: Set if the result is "0"; cleared otherwise.
S: Set if the result is negative; cleared otherwise.
V: Set if arithmetic overflow occurs, that is, if both operands are of the same sign and the
result is of the opposite sign; cleared otherwise.
D: Always cleared to "0".
H: Set if there is a carry from the most significant bit of the low-order four bits of the result;
cleared otherwise.

Format:

Bytes

Cycles

Opcode

(Hex)

Addr Mode

dst src

opc

dst | src

opc

src

dst

opc

dst

src

Examples:

Given: R1 = 10H, R2 = 03H, C flag = "1", register 01H = 20H, register 02H = 03H, and register 03H
= 0AH:

ADC

R1,R2

R1 = 14H, R2 = 03H

ADC

R1,@R2

R1 = 1BH, R2 = 03H

ADC

01H,02H

ADC

01H,@02H

ADC

01H,#11H

In the first example, destination register R1 contains the value 10H, the carry flag is set to "1", and
the source working register R2 contains the value 03H. The statement "ADC R1,R2" adds 03H and
the carry flag value ("1") to the destination value 10H, leaving 14H in register R1.

SAM88RI INSTRUCTION SET

S3C9234/P9234

6-12

ADD

-- Add

ADD

dst,src

Operation:

dst ¨ dst + src

The source operand is added to the destination operand and the sum is stored in the destination.
The contents of the source are unaffected. Two's-complement addition is performed.

Flags:

C: Set if there is a carry from the most significant bit of the result; cleared otherwise.
Z: Set if the result is "0"; cleared otherwise.
S: Set if the result is negative; cleared otherwise.
V: Set if arithmetic overflow occurred, that is, if both operands are of the same sign and the
result is of the opposite sign; cleared otherwise.
D: Always cleared to "0".
H: Set if a carry from the low-order nibble occurred.

Format:

Bytes

Cycles

Opcode

(Hex)

Addr Mode

dst src

opc

dst | src

opc

src

dst

opc

dst

src

Examples:

Given: R1 = 12H, R2 = 03H, register 01H = 21H, register 02H = 03H, register 03H = 0AH:

ADD

R1,R2

R1 = 15H, R2 = 03H

ADD

R1,@R2

R1 = 1CH, R2 = 03H

ADD

01H,02H

ADD

01H,@02H

ADD

01H,#25H

In the first example, destination working register R1 contains 12H and the source working register R2
contains 03H. The statement "ADD R1,R2" adds 03H to 12H, leaving the value 15H in register R1.

S3C9234/P9234

SAM88RCRI INSTRUCTION SET

6-13

AND

-- Logical AND

AND

dst,src

Operation:

dst ¨ dst AND src

The source operand is logically ANDed with the destination operand. The result is stored in the
destination. The AND operation results in a "1" bit being stored whenever the corresponding bits in
the two operands are both logic ones; otherwise a "0" bit value is stored. The contents of the source
are unaffected.

Flags:

C: Unaffected.
Z: Set if the result is "0"; cleared otherwise.
S: Set if the result bit 7 is set; cleared otherwise.
V: Always cleared to "0".
D: Unaffected.
H: Unaffected.

Format:

Bytes

Cycles

Opcode

(Hex)

Addr Mode

dst src

opc

dst | src

opc

src

dst

opc

dst

src

Examples:

Given: R1 = 12H, R2 = 03H, register 01H = 21H, register 02H = 03H, register 03H = 0AH:

AND

R1,R2

R1 = 02H, R2 = 03H

AND

R1,@R2

R1 = 02H, R2 = 03H

AND

01H,02H

AND

01H,@02H

AND

01H,#25H

In the first example, destination working register R1 contains the value 12H and the source working
register R2 contains 03H. The statement "AND R1,R2" logically ANDs the source operand 03H with
the destination operand value 12H, leaving the value 02H in register R1.

SAM88RI INSTRUCTION SET

S3C9234/P9234

6-14

CALL

-- Call Procedure

CALL

dst

Operation:

SP 1

@SP

PCL

SP 1

@SP

PCH

dst

The current contents of the program counter are pushed onto the top of the stack. The program
counter value used is the address of the first instruction following the CALL instruction. The specified
destination address is then loaded into the program counter and points to the first instruction of a
procedure. At the end of the procedure the return instruction (RET) can be used to return to the
original program flow. RET pops the top of the stack back into the program counter.

Flags:

No flags are affected.

Format:

Bytes

Cycles

Opcode

(Hex)

Addr Mode

dst

opc

dst

opc

dst

IRR

Examples:

Given: R0 = 15H, R1 = 21H, PC = 1A47H, and SP = 0B2H:

CALL

1521H

SP = 0B0H
(Memory locations 00H = 1AH, 01H = 4AH, where 4AH
is the address that follows the instruction.)

CALL

@RR0

SP = 0B0H (00H = 1AH, 01H = 49H)

In the first example, if the program counter value is 1A47H and the stack pointer contains the value
0B2H, the statement "CALL 1521H" pushes the current PC value onto the top of the stack. The
stack pointer now points to memory location 00H. The PC is then loaded with the value 1521H, the
address of the first instruction in the program sequence to be executed.

If the contents of the program counter and stack pointer are the same as in the first example, the
statement "CALL @RR0" produces the same result except that the 49H is stored in stack location
01H (because the two-byte instruction format was used). The PC is then loaded with the value
1521H, the address of the first instruction in the program sequence to be executed.

S3C9234/P9234

SAM88RCRI INSTRUCTION SET

6-15

CCF

-- Complement Carry Flag

CCF

Operation:

C ¨ NOT C

The carry flag (C) is complemented. If C = "1", the value of the carry flag is changed to logic zero; if
C = "0", the value of the carry flag is changed to logic one.

Flags:

C: Complemented.

No other flags are affected.

Format:

Bytes

Cycles

Opcode

(Hex)

opc

Example:

Given: The carry flag = "0":

CCF

If the carry flag = "0", the CCF instruction complements it in the FLAGS register (0D5H), changing
its value from logic zero to logic one.

SAM88RI INSTRUCTION SET

S3C9234/P9234

6-16

CLR

-- Clear

CLR

dst

Operation:

dst ¨ "0"

The destination location is cleared to "0".

Flags:

No flags are affected.

Format:

Bytes

Cycles

Opcode

(Hex)

Addr Mode

dst

opc

dst

Examples:

Given: Register 00H = 4FH, register 01H = 02H, and register 02H = 5EH:

CLR

00H

CLR

@01H

In Register (R) addressing mode, the statement "CLR 00H" clears the destination register 00H value
to 00H. In the second example, the statement "CLR @01H" uses Indirect Register (IR) addressing
mode to clear the 02H register value to 00H.

S3C9234/P9234

SAM88RCRI INSTRUCTION SET

6-17

COM

-- Complement

COM

dst

Operation:

dst ¨ NOT dst

The contents of the destination location are complemented (one's complement); all "1s" are changed
to "0s", and vice-versa.

Flags:

C: Unaffected.
Z: Set if the result is "0"; cleared otherwise.
S: Set if the result bit 7 is set; cleared otherwise.
V: Always reset to "0".
D: Unaffected.
H: Unaffected.

Format:

Bytes

Cycles

Opcode

(Hex)

Addr Mode

dst

opc

dst

Examples:

Given: R1 = 07H and register 07H = 0F1H:

COM

R1 = 0F8H

COM

@R1

R1 = 07H, register 07H = 0EH

In the first example, destination working register R1 contains the value 07H (00000111B). The
statement "COM R1" complements all the bits in R1: all logic ones are changed to logic zeros, and
vice-versa, leaving the value 0F8H (11111000B).

In the second example, Indirect Register (IR) addressing mode is used to complement the value of
destination register 07H (11110001B), leaving the new value 0EH (00001110B).

SAM88RI INSTRUCTION SET

S3C9234/P9234

6-18

-- Compare

dst,src

Operation:

dst src

The source operand is compared to (subtracted from) the destination operand, and the appropriate
flags are set accordingly. The contents of both operands are unaffected by the comparison.

Flags:

C: Set if a "borrow" occurred (src > dst); cleared otherwise.
Z: Set if the result is "0"; cleared otherwise.
S: Set if the result is negative; cleared otherwise.
V: Set if arithmetic overflow occurred, that is, if the operands were of opposite signs and the
sign of the result is of the same as the sign of the source operand; cleared otherwise.
D: Unaffected.
H: Unaffected.

Format:

Bytes

Cycles

Opcode

(Hex)

Addr Mode

dst src

opc

dst | src

opc

src

dst

opc

dst

src

Examples:

1. Given: R1 = 02H and R2 = 03H:

R1,R2

Set the C and S flags

Destination working register R1 contains the value 02H and source register R2 contains the value
03H. The statement "CP R1,R2" subtracts the R2 value (source/subtrahend) from the R1 value
(destination/minuend). Because a "borrow" occurs and the difference is negative, C and S are "1".

2. Given: R1 = 05H and R2 = 0AH:

R1,R2

UGE,SKIP

INC

SKIP

R3,R1

In this example, destination working register R1 contains the value 05H which is less than the
contents of the source working register R2 (0AH). The statement "CP R1,R2" generates C = "1" and
the JP instruction does not jump to the SKIP location. After the statement "LD R3,R1" executes,
the value 06H remains in working register R3.

S3C9234/P9234

SAM88RCRI INSTRUCTION SET

6-19

DEC

-- Decrement

DEC

dst

Operation:

dst ¨ dst 1

The contents of the destination operand are decremented by one.

Flags:

C: Unaffected.
Z: Set if the result is "0"; cleared otherwise.
S: Set if result is negative; cleared otherwise.
V: Set if arithmetic overflow occurred, that is, dst value is 128(80H) and result value is
+127(7FH); cleared otherwise.
D: Unaffected.
H: Unaffected.

Format:

Bytes

Cycles

Opcode

(Hex)

Addr Mode

dst

opc

dst

Examples:

Given: R1 = 03H and register 03H = 10H:

DEC

R1 = 02H

DEC

@R1

In the first example, if working register R1 contains the value 03H, the statement "DEC R1"
decrements the hexadecimal value by one, leaving the value 02H. In the second example, the
statement "DEC @R1" decrements the value 10H contained in the destination register 03H by one,
leaving the value 0FH.

SAM88RI INSTRUCTION SET

S3C9234/P9234

6-20

-- Disable Interrupts

Operation:

SYM (2) ¨ 0

Bit zero of the system mode register, SYM.2, is cleared to "0", globally disabling all interrupt
processing. Interrupt requests will continue to set their respective interrupt pending bits, but the CPU
will not service them while interrupt processing is disabled.

Flags:

No flags are affected.

Format:

Bytes

Cycles

Opcode

(Hex)

opc

Example:

Given: SYM = 04H:

If the value of the SYM register is 04H, the statement "DI" leaves the new value 00H in the register
and clears SYM.2 to "0", disabling interrupt processing.

S3C9234/P9234

SAM88RCRI INSTRUCTION SET

6-21

-- Enable Interrupts

Operation:

SYM (2) ¨ 1

An EI instruction sets bit 2 of the system mode register, SYM.2 to "1". This allows interrupts to be
serviced as they occur. If an interrupt's pending bit was set while interrupt processing was disabled
(by executing a DI instruction), it will be serviced when you execute the EI instruction.

Flags:

No flags are affected.

Format:

Bytes

Cycles

Opcode

(Hex)

opc

Example:

Given: SYM = 00H:

If the SYM register contains the value 00H, that is, if interrupts are currently disabled, the statement
"EI" sets the SYM register to 04H, enabling all interrupts (SYM.2 is the enable bit for global interrupt
processing).

S3C9234/P9234

SAM88RCRI INSTRUCTION SET

6-23

INC

-- Increment

INC

dst

Operation:

dst ¨ dst + 1

The contents of the destination operand are incremented by one.

Flags:

C: Unaffected.
Z: Set if the result is "0"; cleared otherwise.
S: Set if the result is negative; cleared otherwise.
V: Set if arithmetic overflow occurred, that is dst value is +127(7FH) and result is 128(80H);
cleared otherwise.
D: Unaffected.
H: Unaffected.

Format:

Bytes

Cycles

Opcode

(Hex)

Addr Mode

dst

dst | opc

r = 0 to F

opc

dst

Examples:

Given: R0 = 1BH, register 00H = 0CH, and register 1BH = 0FH:

INC

R0 = 1CH

INC

00H

INC

@R0

R0 = 1BH, register 01H = 10H

In the first example, if destination working register R0 contains the value 1BH, the statement "INC
R0" leaves the value 1CH in that same register.

The next example shows the effect an INC instruction has on register 00H, assuming that it contains
the value 0CH.

In the third example, INC is used in Indirect Register (IR) addressing mode to increment the value of
register 1BH from 0FH to 10H.

SAM88RI INSTRUCTION SET

S3C9234/P9234

6-24

IRET

-- Interrupt Return

IRET

IRET

Operation:

FLAGS ¨ @SP
SP ¨ SP + 1
PC ¨ @SP
SP ¨ SP + 2
SYM(2) ¨ 1

This instruction is used at the end of an interrupt service routine. It restores the flag register and the
program counter. It also re-enables global interrupts.

Flags:

All flags are restored to their original settings (that is, the settings before the interrupt occurred).

Format:

IRET

(Normal)

Bytes

Cycles

Opcode

(Hex)

opc

S3C9234/P9234

SAM88RCRI INSTRUCTION SET

6-25

-- Jump

cc,dst

(Conditional)

dst

(Unconditional)

Operation:

If cc is true, PC ¨ dst

The conditional JUMP instruction transfers program control to the destination address if the condition
specified by the condition code (cc) is true; otherwise, the instruction following the JP instruction is
executed. The unconditional JP simply replaces the contents of the PC with the contents of the
specified register pair. Control then passes to the statement addressed by the PC.

Flags:

No flags are affected.

Format:

(1)

(2)

Bytes

Cycles

Opcode

(Hex)

Addr Mode

dst

cc | opc

dst

(3)

ccD

cc = 0 to F

opc

dst

IRR

NOTES:
1.

The 3-byte format is used for a conditional jump and the 2-byte format for an unconditional jump.

In the first byte of the three-byte instruction format (conditional jump), the condition code and the opcode are both four
bits.

Examples:

Given: The carry flag (C) = "1", register 00 = 01H, and register 01 = 20H:

C,LABEL_W

LABEL_W = 1000H, PC = 1000H

@00H

PC = 0120H

The first example shows a conditional JP. Assuming that the carry flag is set to "1", the statement
"JP C,LABEL_W" replaces the contents of the PC with the value 1000H and transfers control to that
location. Had the carry flag not been set, control would then have passed to the statement
immediately following the JP instruction.

The second example shows an unconditional JP. The statement "JP @00" replaces the contents of
the PC with the contents of the register pair 00H and 01H, leaving the value 0120H.

SAM88RI INSTRUCTION SET

S3C9234/P9234

6-26

-- Jump Relative

cc,dst

Operation:

If cc is true, PC ¨ PC + dst

If the condition specified by the condition code (cc) is true, the relative address is added to the
program counter and control passes to the statement whose address is now in the program counter;
otherwise, the instruction following the JR instruction is executed (See list of condition codes).

The range of the relative address is +127, 128, and the original value of the program counter is
taken to be the address of the first instruction byte following the JR statement.

Flags:

No flags are affected.

Format:

(1)

Bytes

Cycles

Opcode

(Hex)

Addr Mode

dst

cc | opc

dst

(2)

ccB

cc = 0 to F

NOTE:

In the first byte of the two-byte instruction format, the condition code and the opcode are each four
bits.

Example:

Given: The carry flag = "1" and LABEL_X = 1FF7H:

C,LABEL_X

PC = 1FF7H

If the carry flag is set (that is, if the condition code is true), the statement "JR C,LABEL_X" will pass
control to the statement whose address is now in the PC. Otherwise, the program instruction
following the JR would be executed.

S3C9234/P9234

SAM88RCRI INSTRUCTION SET

6-27

-- Load

dst,src

Operation:

dst ¨ src

The contents of the source are loaded into the destination. The source's contents are unaffected.

Flags:

No flags are affected.

Format:

Bytes

Cycles

Opcode

(Hex)

Addr Mode

dst src

dst | opc

src

src | opc

dst

r = 0 to F

opc

dst | src

opc

src

dst

opc

dst

src

opc

src

dst

opc

dst | src

x [r]

opc

src | dst

x [r]

SAM88RI INSTRUCTION SET

S3C9234/P9234

6-28

-- Load

(Continued)

Examples:

Given: R0 = 01H, R1 = 0AH, register 00H = 01H, register 01H = 20H,
register 02H = 02H, LOOP = 30H, and register 3AH = 0FFH:

R0,#10H

R0 = 10H

R0,01H

R0 = 20H, register 01H = 20H

01H,R0

R1,@R0

R1 = 20H, R0 = 01H

@R0,R1

R0 = 01H, R1 = 0AH, register 01H = 0AH

00H,01H

02H,@00H

00H,#0AH

@00H,#10H

@00H,02H

R0,#LOOP[R1]

R0 = 0FFH, R1 = 0AH

#LOOP[R0],R1

S3C9234/P9234

SAM88RCRI INSTRUCTION SET

6-29

LDC/LDE

-- Load Memory

LDC/LDE

dst,src

Operation:

dst ¨ src

This instruction loads a byte from program or data memory into a working register or vice-versa. The
source values are unaffected. LDC refers to program memory and LDE to data memory. The
assembler makes 'Irr' or 'rr' values an even number for program memory and an odd number for data
memory.

Flags:

No flags are affected.

Format:

Bytes

Cycles

Opcode

(Hex)

Addr Mode

dst src

opc

dst | src

Irr

opc

src | dst

Irr

opc

dst | src

XS [rr]

opc

src | dst

XS [rr]

opc

dst | src

XL [rr]

opc

src | dst

XL [rr]

opc

dst | 0000

opc

src | 0000

opc

dst | 0001

10.

opc

src | 0001

NOTES:
1.

The source (src) or working register pair [rr] for formats 5 and 6 cannot use register pair 01.

For formats 3 and 4, the destination address 'XS [rr]' and the source address 'XS [rr]' are each one byte.

For formats 5 and 6, the destination address 'XL [rr] and the source address 'XL [rr]' are each two bytes.

The DA and r source values for formats 7 and 8 are used to address program memory; the second set of values, used

in formats 9 and 10, are used to address data memory.

SAM88RI INSTRUCTION SET

S3C9234/P9234

6-30

LDC/LDE

-- Load Memory

LDC/LDE

(Continued)

Examples:

Given: R0 = 11H, R1 = 34H, R2 = 01H, R3 = 04H, R4 = 00H, R5 = 60H; Program memory locations
0061 = AAH, 0103H = 4FH, 0104H = 1A, 0105H = 6DH, and 1104H = 88H. External data memory
locations 0061H = BBH, 0103H = 5FH, 0104H = 2AH, 0105H = 7DH, and
1104H = 98H:

LDC

R0,@RR2

; R0 ¨ contents of program memory location 0104H
; R0 = 1AH, R2 = 01H, R3 = 04H

LDE

R0,@RR2

; R0 ¨ contents of external data memory location 0104H
; R0 = 2AH, R2 = 01H, R3 = 04H

LDC *

@RR2,R0

; 11H (contents of R0) is loaded into program memory
; location 0104H (RR2),
; working registers R0, R2, R3 Æ no change

LDE

@RR2,R0

; 11H (contents of R0) is loaded into external data memory
; location 0104H (RR2),
; working registers R0, R2, R3 Æ no change

LDC

R0,#01H[RR4]

; R0 ¨ contents of program memory location 0061H
; (01H + RR4),
; R0 = AAH, R2 = 00H, R3 = 60H

LDE

R0,#01H[RR4]

; R0 ¨ contents of external data memory location 0061H
; (01H + RR4), R0 = BBH, R4 = 00H, R5 = 60H

LDC

(note)

#01H[RR4],R0

; 11H (contents of R0) is loaded into program memory
; location 0061H (01H + 0060H)

LDE

#01H[RR4],R0

; 11H (contents of R0) is loaded into external data memory
; location 0061H (01H + 0060H)

LDC

R0,#1000H[RR2]

; R0 ¨ contents of program memory location 1104H
; (1000H + 0104H), R0 = 88H, R2 = 01H, R3 = 04H

LDE

R0,#1000H[RR2]

; R0 ¨ contents of external data memory location 1104H
; (1000H + 0104H), R0 = 98H, R2 = 01H, R3 = 04H

LDC

R0,1104H

; R0 ¨ contents of program memory location 1104H,
; R0 = 88H

LDE

R0,1104H

; R0 ¨ contents of external data memory location 1104H,
; R0 = 98H

LDC

(note)

1105H,R0

; 11H (contents of R0) is loaded into program memory
; location 1105H, (1105H) ¨ 11H

LDE

1105H,R0

; 11H (contents of R0) is loaded into external data memory

;

location 1105H, (1105H) ¨ 11H

NOTE: These instructions are not supported by masked ROM type devices.

S3C9234/P9234

SAM88RCRI INSTRUCTION SET

6-31

LDCD/LDED

-- Load Memory and Decrement

LDCD/LDED

dst,src

Operation:

dst ¨ src

rr ¨ rr 1

These instructions are used for user stacks or block transfers of data from program or data memory
to the register file. The address of the memory location is specified by a working register pair. The
contents of the source location are loaded into the destination location. The memory address is then
decremented. The contents of the source are unaffected.

LDCD references program memory and LDED references external data memory. The assembler
makes `Irr' an even number for program memory and an odd number for data memory.

Flags:

No flags are affected.

Format:

Bytes

Cycles

Opcode

(Hex)

Addr Mode

dst src

opc

dst | src

Irr

Examples:

Given: R6 = 10H, R7 = 33H, R8 = 12H, program memory location 1033H = 0CDH, and
external data memory location 1033H = 0DDH:

LDCD

R8,@RR6

; 0CDH (contents of program memory location 1033H) is
; loaded into R8 and RR6 is decremented by one
; R8 = 0CDH, R6 = 10H, R7 = 32H (RR6

RR6 - 1)

LDED

R8,@RR6

; 0DDH (contents of data memory location 1033H) is
; loaded into R8 and RR6 is decremented by one
; (RR6

RR6 - 1) R8 = 0DDH, R6 = 10H, R7 = 32H

SAM88RI INSTRUCTION SET

S3C9234/P9234

6-32

LDCI/LDEI

-- Load Memory and Increment

LDCI/LDEI

dst,src

Operation:

dst ¨ src

rr ¨ rr + 1

These instructions are used for user stacks or block transfers of data from program or data memory
to the register file. The address of the memory location is specified by a working register pair. The
contents of the source location are loaded into the destination location. The memory address is then
incremented automatically. The contents of the source are unaffected.

LDCI refers to program memory and LDEI refers to external data memory. The assembler makes 'Irr'
even for program memory and odd for data memory.

Flags:

No flags are affected.

Format:

Bytes

Cycles

Opcode

(Hex)

Addr Mode

dst src

opc

dst | src

Irr

Examples:

Given: R6 = 10H, R7 = 33H, R8 = 12H, program memory locations 1033H = 0CDH and

1034H = 0C5H; external data memory locations 1033H = 0DDH and 1034H = 0D5H:

LDCI

R8,@RR6

; 0CDH (contents of program memory location 1033H) is
; loaded into R8 and RR6 is incremented by one
; (RR6 ¨ RR6 + 1) R8 = 0CDH, R6 = 10H, R7 = 34H

LDEI

R8,@RR6

; 0DDH (contents of data memory location 1033H) is
; loaded into R8 and RR6 is incremented by one
; (RR6 ¨ RR6 + 1) R8 = 0DDH, R6 = 10H, R7 = 34H

S3C9234/P9234

SAM88RCRI INSTRUCTION SET

6-33

NOP

-- No Operation

NOP

Operation:

No action is performed when the CPU executes this instruction. Typically, one or more NOPs are
executed in sequence in order to effect a timing delay of variable duration.

Flags:

No flags are affected.

Format:

Bytes

Cycles

Opcode

(Hex)

opc

Example:

When the instruction

NOP

is encountered in a program, no operation occurs. Instead, there is a delay in instruction execution
time.

SAM88RI INSTRUCTION SET

S3C9234/P9234

6-34

-- Logical OR

dst,src

Operation:

dst ¨ dst OR src

The source operand is logically ORed with the destination operand and the result is stored in the
destination. The contents of the source are unaffected. The OR operation results in a "1" being
stored whenever either of the corresponding bits in the two operands is a "1"; otherwise a "0" is
stored.

Flags:

C: Unaffected.
Z: Set if the result is "0"; cleared otherwise.
S: Set if the result bit 7 is set; cleared otherwise.
V: Always cleared to "0".
D: Unaffected.
H: Unaffected.

Format:

Bytes

Cycles

Opcode

(Hex)

Addr Mode

dst src

opc

dst | src

opc

src

dst

opc

dst

src

Examples:

Given: R0 = 15H, R1 = 2AH, R2 = 01H, register 00H = 08H, register 01H = 37H, and register 08H
= 8AH:

R0,R1

R0 = 3FH, R1 = 2AH

R0,@R2

R0 = 37H, R2 = 01H, register 01H = 37H

00H,01H

01H,@00H

00H,#02H

In the first example, if working register R0 contains the value 15H and register R1 the value 2AH, the
statement "OR R0,R1" logical-ORs the R0 and R1 register contents and stores the result (3FH) in
destination register R0.

The other examples show the use of the logical OR instruction with the various addressing modes
and formats.

S3C9234/P9234

SAM88RCRI INSTRUCTION SET

6-35

POP

Pop From Stack

POP

dst

Operation:

dst ¨ @SP

SP ¨ SP + 1

The contents of the location addressed by the stack pointer are loaded into the destination. The
stack pointer is then incremented by one.

Flags:

No flags affected.

Format:

Bytes

Cycles

Opcode

(Hex)

Addr Mode

dst

opc

dst

Examples:

Given: Register 00H = 01H, register 01H = 1BH, SP (0D9H) = 0BBH, and stack register
0BBH = 55H:

POP

00H

POP

@00H

In the first example, general register 00H contains the value 01H. The statement "POP 00H" loads
the contents of location 0BBH (55H) into destination register 00H and then increments the stack
pointer by one. Register 00H then contains the value 55H and the SP points to location 0BCH.

SAM88RI INSTRUCTION SET

S3C9234/P9234

6-36

PUSH

Push To Stack

PUSH

src

Operation:

SP ¨ SP 1

@SP ¨ src

A PUSH instruction decrements the stack pointer value and loads the contents of the source (src)
into the location addressed by the decremented stack pointer. The operation then adds the new
value to the top of the stack.

Flags:

No flags are affected.

Format:

Bytes

Cycles

Opcode

(Hex)

Addr Mode

dst

opc

src

Examples:

Given: Register 40H = 4FH, register 4FH = 0AAH, SP = 0C0H:

PUSH

40H

PUSH

@40H

In the first example, if the stack pointer contains the value 0C0H, and general register 40H the value
4FH, the statement "PUSH 40H" decrements the stack pointer from 0C0 to 0BFH. It then loads the
contents of register 40H into location 0BFH. Register 0BFH then contains the value 4FH and SP
points to location 0BFH.

SAM88RI INSTRUCTION SET

S3C9234/P9234

6-38

RET

-- Return

RET

Operation:

PC ¨ @SP

SP ¨ SP + 2

The RET instruction is normally used to return to the previously executing procedure at the end of a
procedure entered by a CALL instruction. The contents of the location addressed by the stack
pointer are popped into the program counter. The next statement that is executed is the one that is
addressed by the new program counter value.

Flags:

No flags are affected.

Format:

Bytes

Cycles

Opcode

(Hex)

opc

Example:

Given: SP = 0BCH, (SP) = 101AH, and PC = 1234:

RET

PC = 101AH, SP = 0BEH

The statement "RET" pops the contents of stack pointer location 0BCH (10H) into the high byte of
the program counter. The stack pointer then pops the value in location 0BDH (1AH) into the PC's low
byte and the instruction at location 101AH is executed. The stack pointer now points to memory
location 0BEH.

S3C9234/P9234

SAM88RCRI INSTRUCTION SET

6-39

Rotate Left

dst

Operation:

C ¨ dst (7)

dst (0) ¨ dst (7)

dst (n + 1) ¨ dst (n), n = 06

The contents of the destination operand are rotated left one bit position. The initial value of bit 7 is
moved to the bit zero (LSB) position and also replaces the carry flag.

Flags:

C: Set if the bit rotated from the most significant bit position (bit 7) was "1".
Z: Set if the result is "0"; cleared otherwise.
S: Set if the result bit 7 is set; cleared otherwise.
V: Set if arithmetic overflow occurred, that is, if the sign of the destination changed during
rotation; cleared otherwise.
D: Unaffected.
H: Unaffected.

Format:

Bytes

Cycles

Opcode

(Hex)

Addr Mode

dst

opc

dst

Examples:

Given: Register 00H = 0AAH, register 01H = 02H and register 02H = 17H:

00H

@01H

In the first example, if general register 00H contains the value 0AAH (10101010B), the statement "RL
00H" rotates the 0AAH value left one bit position, leaving the new value 55H (01010101B) and setting
the carry and overflow flags.

SAM88RI INSTRUCTION SET

S3C9234/P9234

6-40

RLC

-- Rotate Left Through Carry

RLC

dst

Operation:

dst (0) ¨ C

C ¨ dst (7)

dst (n + 1) ¨ dst (n), n = 06

The contents of the destination operand with the carry flag are rotated left one bit position. The initial
value of bit 7 replaces the carry flag (C); the initial value of the carry flag replaces bit zero.

Flags:

Format:

Bytes

Cycles

Opcode

(Hex)

Addr Mode

dst

opc

dst

Examples:

Given: Register 00H = 0AAH, register 01H = 02H, and register 02H = 17H, C = "0":

RLC

00H

RLC

@01H

In the first example, if general register 00H has the value 0AAH (10101010B), the statement "RLC
00H" rotates 0AAH one bit position to the left. The initial value of bit 7 sets the carry flag and the
initial value of the C flag replaces bit zero of register 00H, leaving the value 55H (01010101B). The
MSB of register 00H resets the carry flag to "1" and sets the overflow flag.

S3C9234/P9234

SAM88RCRI INSTRUCTION SET

6-41

-- Rotate Right

dst

Operation:

C ¨ dst (0)

dst (7) ¨ dst (0)

dst (n) ¨ dst (n + 1), n = 06

The contents of the destination operand are rotated right one bit position. The initial value of bit zero
(LSB) is moved to bit 7 (MSB) and also replaces the carry flag (C).

Flags:

C: Set if the bit rotated from the least significant bit position (bit zero) was "1".
Z: Set if the result is "0"; cleared otherwise.
S: Set if the result bit 7 is set; cleared otherwise.
V: Set if arithmetic overflow occurred, that is, if the sign of the destination changed during
rotation; cleared otherwise.
D: Unaffected.
H: Unaffected.

Format:

Bytes

Cycles

Opcode

(Hex)

Addr Mode

dst

opc

dst

Examples:

Given: Register 00H = 31H, register 01H = 02H, and register 02H = 17H:

00H

@01H

In the first example, if general register 00H contains the value 31H (00110001B), the statement "RR
00H" rotates this value one bit position to the right. The initial value of bit zero is moved to bit 7,
leaving the new value 98H (10011000B) in the destination register. The initial bit zero also resets the
C flag to "1" and the sign flag and overflow flag are also set to "1".

SAM88RI INSTRUCTION SET

S3C9234/P9234

6-42

RRC

Rotate Right Through Carry

RRC

dst

Operation:

dst (7) ¨ C

C ¨ dst (0)

dst (n) ¨ dst (n + 1), n = 06

The contents of the destination operand and the carry flag are rotated right one bit position. The initial
value of bit zero (LSB) replaces the carry flag; the initial value of the carry flag replaces bit 7 (MSB).

Flags:

C: Set if the bit rotated from the least significant bit position (bit zero) was "1".
Z: Set if the result is "0" cleared otherwise.
S: Set if the result bit 7 is set; cleared otherwise.
V: Set if arithmetic overflow occurred, that is, if the sign of the destination changed during
rotation; cleared otherwise.
D: Unaffected.
H: Unaffected.

Format:

Bytes

Cycles

Opcode

(Hex)

Addr Mode

dst

opc

dst

Examples:

Given: Register 00H = 55H, register 01H = 02H, register 02H = 17H, and C = "0":

RRC

00H

RRC

@01H

In the first example, if general register 00H contains the value 55H (01010101B), the statement "RRC
00H" rotates this value one bit position to the right. The initial value of bit zero ("1") replaces the carry
flag and the initial value of the C flag ("1") replaces bit 7. This leaves the new value 2AH (00101010B)
in destination register 00H. The sign flag and overflow flag are both cleared to "0".

S3C9234/P9234

SAM88RCRI INSTRUCTION SET

6-43

SBC

Subtract With Carry

SBC

dst,src

Operation:

dst ¨ dst src c

The source operand, along with the current value of the carry flag, is subtracted from the destination
operand and the result is stored in the destination. The contents of the source are unaffected.
Subtraction is performed by adding the two's-complement of the source operand to the destination
operand. In multiple precision arithmetic, this instruction permits the carry ("borrow") from the
subtraction of the low-order operands to be subtracted from the subtraction of high-order operands.

Flags:

C: Set if a borrow occurred (src > dst); cleared otherwise.
Z: Set if the result is "0"; cleared otherwise.
S: Set if the result is negative; cleared otherwise.
V: Set if arithmetic overflow occurred, that is, if the operands were of opposite sign and the sign
f the result is the same as the sign of the source; cleared otherwise.
D: Always set to "1".
H: Cleared if there is a carry from the most significant bit of the low-order four bits of the result;

set otherwise, indicating a "borrow".

Format:

Bytes

Cycles

Opcode

(Hex)

Addr Mode

dst src

opc

dst | src

opc

src

dst

opc

dst

src

Examples:

Given: R1 = 10H, R2 = 03H, C = "1", register 01H = 20H, register 02H = 03H, and register
03H = 0AH:

SBC

R1,R2

R1 = 0CH, R2 = 03H

SBC

R1,@R2

R1 = 05H, R2 = 03H, register 03H = 0AH

SBC

01H,02H

SBC

01H,@02H

SBC

01H,#8AH

In the first example, if working register R1 contains the value 10H and register R2 the value 03H, the
statement "SBC R1,R2" subtracts the source value (03H) and the C flag value ("1") from the
destination (10H) and then stores the result (0CH) in register R1.

S3C9234/P9234

SAM88RCRI INSTRUCTION SET

6-45

SRA

-- Shift Right Arithmetic

SRA

dst

Operation:

dst (7) ¨ dst (7)

C ¨ dst (0)

dst (n) ¨ dst (n + 1), n = 06

An arithmetic shift-right of one bit position is performed on the destination operand. Bit zero (the
LSB) replaces the carry flag. The value of bit 7 (the sign bit) is unchanged and is shifted into bit
position 6.

Flags:

C: Set if the bit shifted from the LSB position (bit zero) was "1".
Z: Set if the result is "0"; cleared otherwise.
S: Set if the result is negative; cleared otherwise.
V: Always cleared to "0".
D: Unaffected.
H: Unaffected.

Format:

Bytes

Cycles

Opcode

(Hex)

Addr Mode

dst

opc

dst

Examples:

Given: Register 00H = 9AH, register 02H = 03H, register 03H = 0BCH, and C = "1":

SRA

00H

SRA

@02H

In the first example, if general register 00H contains the value 9AH (10011010B), the statement "SRA
00H" shifts the bit values in register 00H right one bit position. Bit zero ("0") clears the C flag and bit
7 ("1") is then shifted into the bit 6 position (bit 7 remains unchanged). This leaves the value 0CDH
(11001101B) in destination register 00H.

SAM88RI INSTRUCTION SET

S3C9234/P9234

6-46

STOP

-- Stop Operation

STOP

Operation:

The STOP instruction stops both the CPU clock and system clock and causes the microcontroller to
enter Stop mode. During Stop mode, the contents of on-chip CPU registers, peripheral registers, and
I/O port control and data registers are retained. Stop mode can be released by an external reset
operation or External interrupt input. For the reset operation, the RESET pin must be held to Low
level until the required oscillation stabilization interval has elapsed.

Flags:

No flags are affected.

Format:

Bytes

Cycles

Opcode

(Hex)

Addr Mode

dst src

opc

Example:

The statement

STOP

halts all microcontroller operations.

S3C9234/P9234

SAM88RCRI INSTRUCTION SET

6-47

SUB

-- Subtract

SUB

dst,src

Operation:

dst ¨ dst src

The source operand is subtracted from the destination operand and the result is stored in the
destination. The contents of the source are unaffected. Subtraction is performed by adding the two's
complement of the source operand to the destination operand.

Flags:

C: Set if a "borrow" occurred; cleared otherwise.
Z: Set if the result is "0"; cleared otherwise.
S: Set if the result is negative; cleared otherwise.
V: Set if arithmetic overflow occurred, that is, if the operands were of opposite signs and the sign
of the result is of the same as the sign of the source operand; cleared otherwise.
D: Always set to "1".
H: Cleared if there is a carry from the most significant bit of the low-order four bits of the result;
set otherwise indicating a "borrow".

Format:

Bytes

Cycles

Opcode

(Hex)

Addr Mode

dst src

opc

dst | src

opc

src

dst

opc

dst

src

Examples:

Given: R1 = 12H, R2 = 03H, register 01H = 21H, register 02H = 03H, register 03H = 0AH:

SUB

R1,R2

R1 = 0FH, R2 = 03H

SUB

R1,@R2

R1 = 08H, R2 = 03H

SUB

01H,02H

SUB

01H,@02H

SUB

01H,#90H

SUB

01H,#65H

In the first example, if working register R1 contains the value 12H and if register R2 contains the
value 03H, the statement "SUB R1,R2" subtracts the source value (03H) from the destination value
(12H) and stores the result (0FH) in destination register R1.

SAM88RI INSTRUCTION SET

S3C9234/P9234

6-48

TCM

Test Complement Under Mask

TCM

dst,src

Operation:

(NOT dst) AND src

This instruction tests selected bits in the destination operand for a logic one value. The bits to be
tested are specified by setting a "1" bit in the corresponding position of the source operand (mask).
The TCM statement complements the destination operand, which is then ANDed with the source
mask. The zero (Z) flag can then be checked to determine the result. The destination and source
operands are unaffected.

Flags:

C: Unaffected.
Z: Set if the result is "0"; cleared otherwise.
S: Set if the result bit 7 is set; cleared otherwise.
V: Always cleared to "0".
D: Unaffected.
H: Unaffected.

Format:

Bytes

Cycles

Opcode

(Hex)

Addr Mode

dst src

opc

dst | src

opc

src

dst

opc

dst

src

Examples:

Given: R0 = 0C7H, R1 = 02H, R2 = 12H, register 00H = 2BH, register 01H = 02H, and register 02H
= 23H:

TCM

R0,R1

R0 = 0C7H, R1 = 02H, Z = "1"

TCM

R0,@R1

R0 = 0C7H, R1 = 02H, register 02H = 23H, Z = "0"

TCM

00H,01H

TCM

00H,@01H

TCM

00H,#34

In the first example, if working register R0 contains the value 0C7H (11000111B) and register R1 the
value 02H (00000010B), the statement "TCM R0,R1" tests bit one in the destination register for a "1"
value. Because the mask value corresponds to the test bit, the Z flag is set to logic one and can be
tested to determine the result of the TCM operation.

S3C9234/P9234

SAM88RCRI INSTRUCTION SET

6-49

-- Test Under Mask

dst,src

Operation:

dst AND src

This instruction tests selected bits in the destination operand for a logic zero value. The bits to be
tested are specified by setting a "1" bit in the corresponding position of the source operand (mask),
which is ANDed with the destination operand. The zero (Z) flag can then be checked to determine the
result. The destination and source operands are unaffected.

Flags:

C: Unaffected.
Z: Set if the result is "0"; cleared otherwise.
S: Set if the result bit 7 is set; cleared otherwise.
V: Always reset to "0".
D: Unaffected.
H: Unaffected.

Format:

Bytes

Cycles

Opcode

(Hex)

Addr Mode

dst src

opc

dst | src

opc

src

dst

opc

dst

src

Examples:

Given: R0 = 0C7H, R1 = 02H, R2 = 18H, register 00H = 2BH, register 01H = 02H, and register 02H
= 23H:

R0,R1

R0 = 0C7H, R1 = 02H, Z = "0"

R0,@R1

R0 = 0C7H, R1 = 02H, register 02H = 23H, Z = "0"

00H,01H

00H,@01H

00H,#54H

In the first example, if working register R0 contains the value 0C7H (11000111B) and register R1 the
value 02H (00000010B), the statement "TM R0,R1" tests bit one in the destination register for a "0"
value. Because the mask value does not match the test bit, the Z flag is cleared to logic zero and
can be tested to determine the result of the TM operation.

SAM88RI INSTRUCTION SET

S3C9234/P9234

6-50

XOR

-- Logical Exclusive OR

XOR

dst,src

Operation:

dst ¨ dst XOR src

The source operand is logically exclusive-ORed with the destination operand and the result is stored
in the destination. The exclusive-OR operation results in a "1" bit being stored whenever the
corresponding bits in the operands are different; otherwise, a "0" bit is stored.

Flags:

C: Unaffected.
Z: Set if the result is "0"; cleared otherwise.
S: Set if the result bit 7 is set; cleared otherwise.
V: Always reset to "0".
D: Unaffected.
H: Unaffected.

Format:

Bytes

Cycles

Opcode

(Hex)

Addr Mode

dst src

opc

dst | src

opc

src

dst

opc

dst

src

Examples:

Given: R0 = 0C7H, R1 = 02H, R2 = 18H, register 00H = 2BH, register 01H = 02H, and register 02H
= 23H:

XOR

R0,R1

R0 = 0C5H, R1 = 02H

XOR

R0,@R1

R0 = 0E4H, R1 = 02H, register 02H = 23H

XOR

00H,01H

XOR

00H,@01H

XOR

00H,#54H

In the first example, if working register R0 contains the value 0C7H and if register R1 contains the
value 02H, the statement "XOR R0,R1" logically exclusive-ORs the R1 value with the R0 value and
stores the result (0C5H) in the destination register R0.

S3C9234/P9234

CLOCK CIRCUITS

7-1

CLOCK CIRCUITS

OVERVIEW

The S3C9234/P9234 microcontroller has two oscillator circuits: a main clock, and a sub clock circuit. The CPU and
peripheral hardware operate on the system clock frequency supplied through these circuits. The maximum CPU
clock frequency, is determined by CLKCON register settings.

SYSTEM CLOCK CIRCUIT

The system clock circuit has the following components:

-- Crystal, ceramic resonator, RC oscillation source (main clock only), or an external clock

-- Oscillator stop and wake-up functions

-- Programmable frequency divider for the CPU clock (fxx divided by 1, 2, 8, or 16)

-- Clock circuit control register, CLKCON

-- Oscillator control register, OSCCON

-- Clock output control register, CLOCON

CPU CLOCK NOTATION

In this document, the following notation is used for descriptions of the CPU clock:

fx main clock

fxt sub clock

fxx selected system clock

S3C9234/P9234

CLOCK CIRCUITS

7-3

CLOCK STATUS DURING POWER-DOWN MODES

The two power-down modes, Stop mode and Idle mode, affect the system clock as follows:

-- In Stop mode, the main oscillator is halted. Stop mode is released, and the oscillator started, by a reset

operation, by an external interrupt, or by an internal interrupt if sub clock is selected as the clock source (When
the fx is selected as system clock).

-- In Idle mode, the internal clock signal is gated away from the CPU, but continues to be supplied to the interrupt

structure, timer A/B, and watch timer. Idle mode is released by a reset or by an external or
internal interrupts.

1/1-1/4096

Frequency

Dividing

Circuit

Stop Release

Main-System

Oscillator

Circuit

Selector 1

Stop

Sub-system

Oscillator

Circuit

INT

OSCCON.0

OSCCON.3

OSCCON.2

1/1

1/16

1/2

1/8

Selector 2

STPCON

STOP OSC

inst.

CLKCON.4-.3

CPU

Stop

Watch Timer

Basic Timer
Timer/Counters
Watch Timer

LCD Controller

SIO

LCD Controller

Figure 7-6. System Clock Circuit Diagram

CLOCK CIRCUITS

S3C9234/P9234

7-4

SYSTEM CLOCK CONTROL REGISTER (CLKCON)

The system clock control register, CLKCON, is located in address D4H. It is read/write addressable and has the
following functions:

-- Oscillator IRQ wake-up function enable/disable

-- Oscillator frequency divide-by value

CLKCON register settings control whether or not an external interrupt can be used to trigger a Stop mode release
(This is called the "IRQ wake-up" function). The IRQ "wake-up" enable bit is CLKCON.7.

After a reset, the external interrupt oscillator wake-up function is enabled, the main oscillator is activated, and the
fx/16 (the slowest clock speed) is selected as the CPU clock. If necessary, you can then increase the CPU clock
speed to fx, fx/2, or fx/8 by setting the CLKCON, and you can change system clock from main clock to sub clock
by setting the OSCCON.

System Clock Control Register (CLKCON)

D4H, R/W

MSB

LSB

Not used for S3C9234/P9234 (must keep always "0")

Divide-by selection bits for
CPU clock frequency:
00 = fxx/16
01 = fxx/8
10 = f

x/2

11 = fxx

Oscillator IRQ wake-up enable bit:
0 = Enable IRQ for main oscillator
wake-up function in power down
mode
1 = Disable IRQ for main oscillator
wake-up function in power down
mode

Not used for S3C9234/P9234 (must keep always "0")

Figure 7-7. System Clock Control Register (CLKCON)

S3C9234/P9234

CLOCK CIRCUITS

7-5

CLOCK OUTPUT CONTROL REGISTER (CLOCON)

The clock output control register, CLOCON, is located in address FEH. It is read/write addressable and has the
following functions;

-- Clock Output Frequency Selection

After a reset, fxx/64 is select for Clock Output Frequency because the reset value of CLOCON.1-.0 is "0".

Clock Output Control Register (CLOCON)

FEH, R/W

MSB

LSB

Not used for S3C9234/P9234.

(Must keep always "0")

Clock Output Frequency Selection Bits:
00 = Select fxx/64
01 = Select fxx/16
10 = Select fxx/8
11 = Select fxx/4

Figure 7-8. Clock Output Control Register (CLOCON)

CLOCON.1-.0

CLKOUT

MUX

fxx/64

fxx/16

fxx/8

fxx/4

P1CONH.5-.4

Figure 7-9. Clock Output Block Diagram

CLOCK CIRCUITS

S3C9234/P9234

7-6

OSCILLATOR CONTROL REGISTER (OSCCON)

The oscillator control register, OSCCON, is located in address D3H. It is read/write addressable and has the
following functions:

-- System clock selection

-- Main oscillator control

-- Sub oscillator control

OSCCON.0 register settings select Main clock or Sub clock as system clock.
After a reset, Main clock is selected for system clock because the reset value of OSCCON.0 is "0".

The main oscillator can be stopped or run by setting OSCCON.3.

The sub oscillator can be stopped or run by setting OSCCON.2.

Oscillator Control Register (OSCCON)

D3H, R/W

MSB

LSB

Not used for S3C9234/P9234

Main oscillator control bit:
0 = Main oscillator RUN
1 = Main oscillator STOP

Sub oscillator control bit:
0 = Sub oscillator RUN
1 = Sub oscillator STOP

Not used for S3C9234/P9234

System clock selection bit:
0 = Main oscillator select
1 = Sub oscillator select

Figure 7-10. Oscillator Control Register (OSCCON)

S3C9234/P9234

CLOCK CIRCUITS

7-7

SWITCHING THE CPU CLOCK

Data loadings in the oscillator control register, OSCCON, determine whether a main or a sub clock is selected as
the CPU clock, and also how this frequency is to be divided by setting CLKCON. This makes it possible to switch
dynamically between main and sub clocks and to modify operating frequencies.

OSCCON.0 select the main clock (fx) or the sub clock (fxt) for the system clock. OSCCON .3 start or stop main
clock oscillation, and OSCCON.2 start or stop sub clock oscillation. CLKCON.4.3 control the frequency divider
circuit, and divide the selected fxx clock by 1, 2, 8, or 16.

For example, you are using the default system clock (normal operating mode and a main clock of fx/16) and you
want to switch from the fx clock to a sub clock and to stop the main clock. To do this, you need to set OSCCON.0
to "1", take a delay, and OSCCON.3 to "1" sequently. This switches the clock from fx to fxt and stops main clock
oscillation.

The following steps must be taken to switch from a sub clock to the main clock: first, set OSCCON.3 to "0" to
enable main system clock oscillation. Then, after a certain number of machine cycles has elapsed, select the main
clock by setting OSCCON.0 to "0".

PROGRAMMING TIP -- Switching the CPU clock

1. This example shows how to change from the main clock to the sub clock:

MA2SUB

OSCCON,#01H

; Switches to the sub clock

CALL

DLY16

; Delay 16ms

OSCCON,#08H

; Stop the main clock oscillation

RET

2. This example shows how to change from sub clock to main clock:

SUB2MA

AND

OSCCON,#0F7H

; Start the main clock oscillation

CALL

DLY16

; Delay 16 ms

AND

OSCCON,#0FEH

; Switch to the main clock

RET

DLY16

R0,#20H

DEL

NOP
DEC

NZ,DEL

RET

CLOCK CIRCUITS

S3C9234/P9234

7-8

STOP CONTROL REGISTER (STPCON)

The STOP control register, STPCON, is located in address D6H. It is read/write addressable and has the following
functions:

-- Enable/Disable STOP instruction

After a reset, the STOP instruction is disabled, because the value of STPCON is "other values".
If necessary, you can use the STOP instruction by setting the value of STPCON to "10100101B".

Stop Control Register (STPCON)

D6H, R/W

MSB

LSB

STOP control bits:
10100101 = Enable STOP instruction
Other values = Disable STOP instruction

Figure 7-11. STOP Control Register (STPCON)

PROGRAMMING TIP -- How to Use Stop Instruction

This example shows how to go STOP mode when a main clock is selected as the system clock.

STOPCON,#1010010B

; Enable STOP instruction

STOP

; Enter STOP mode

NOP
NOP
NOP

; Release STOP mode

STOPCON,#00000000B

; Disable STOP instruction

S3C9234/P9234

RESET

and POWER-DOWN

8-1

RESET

and POWER-DOWN

SYSTEM RESET

OVERVIEW

During a power-on reset, the voltage at V

goes to High level and the

RESET

pin is forced to Low level. The

RESET

signal is input through a schmitt trigger circuit where it is then synchronized with the CPU clock. This procedure
brings S3C9234/P9234 into a known operating status.

To allow time for internal CPU clock oscillation to stabilize, the

RESET

pin must be held to Low level for a minimum

time interval after the power supply comes within tolerance. The minimum required oscillation stabilization time for a
reset operation is 1 millisecond.

Whenever a reset occurs during normal operation (that is, when both V

and

RESET

are High level), the

RESET

pin is forced Low and the reset operation starts. All system and peripheral control registers are then reset to their
default hardware values (see Table 8-1).

In summary, the following sequence of events occurs during a reset operation:

-- All interrupts are disabled.

-- The watchdog function (basic timer) is enabled.

-- Ports 0-6 are set to schmitt trigger input mode and all pull-up resistors are disabled for the I/O port pin circuits.

-- Peripheral control and data registers are disabled and reset to their default hardware values.

-- The program counter (PC) is loaded with the program reset address in the ROM, 0100H.

-- When the programmed oscillation stabilization time interval has elapsed, the instruction stored in ROM location

0100H (and 0101H) is fetched and executed.

NOTE

To program the duration of the oscillation stabilization interval, you make the appropriate settings to the
basic timer control register, BTCON, before entering Stop mode. Also, if you do not want to use the basic
timer watchdog function (which causes a system reset if a basic timer counter overflow occurs), you can
disable it by writing '1010B' to the upper nibble of BTCON.

RESET

and POWER-DOWN

S3C9234/P9234

8-2

POWER-DOWN MODES

STOP MODE

Stop mode is invoked by the instruction STOP. In Stop mode, the operation of the CPU and main oscillator is halted.
All peripherals which the main oscillator is selected as a clock source stop also because main oscillator stops. But
the watch timer and LCD controller will not halted in stop mode if the sub clock is selected as watch timer clock
source. The data stored in the internal register file are retained in stop mode. Stop mode can be released in one of
three ways: by a system reset, by an internal watch timer interrupt (when sub clock is selected as clock source of
watch timer), or by an external interrupt.

Example:

STOPCON,#10100101B

STOP
NOP
NOP
NOP
LD

STOPCON,#00000000B

NOTES

1. Do not use stop mode if you are using an external clock source because X

input must be restricted

internally to V

to reduce current leakage.

2. In application programs, a STOP instruction must be immediately followed by at least three NOP
instructions. This ensures an adequate time interval for the clock to stabilize before the next
instruction is executed. If three or more NOP instructions are not used after STOP instruction,
leakage current could be flown because of the floating state in the internal bus.
3. To enable/disable STOP instruction, the STOPCON register should be written with
10100101B/other values before/after stop instruction.

Using

RESET

to Release Stop Mode

Stop mode is released when the

RESET

signal goes active (Low level): all system and peripheral control registers

are reset to their default hardware values and the contents of all data registers are retained. When the programmed
oscillation stabilization interval has elapsed, the CPU starts the system initialization routine by fetching the program
instruction stored in ROM location 0100H.

Using an External Interrupt to Release Stop Mode

External interrupts can be used to release stop mode. For the S3C9234 microcontroller, we recommend using the
INT interrupt, P1 and P2.

S3C9234/P9234

RESET

and POWER-DOWN

8-3

Using an Internal Interrupt to Release Stop Mode

An internal interrupt, watch timer, can be used to release stop mode because the watch timer operates in stop mode
if the clock source of watch timer is sub clock. If system clock is sub clock, you can't use any interrupts to release
stop mode. That is, you had better use the idle instruction instead of stop one when sub clock is selected as the
system clock.

Please note the following conditions for Stop mode release:

-- If you release stop mode using an internal or external interrupt, the current values in system and peripheral

control registers are unchanged.

-- If you use an internal or external interrupt for stop mode release, you can also program the duration of the

oscillation stabilization interval. To do this, you must make the appropriate control and clock settings before
entering stop mode.

-- If you use an interrupt to release stop mode, the bit-pair setting for CLKCON.4/CLKCON.3 remains unchanged

and the currently selected clock value is used.

-- The internal or external interrupt is serviced when the stop mode release occurs. Following the IRET from the

service routine, the instruction immediately following the one that initiated stop mode is executed.

IDLE MODE

Idle mode is invoked by the instruction IDLE (opcode 6FH). In Idle mode, CPU operations are halted while some
peripherals remain active. During Idle mode, the internal clock signal is gated away from the CPU and from all but
the following peripherals, which remain active:

-- Interrupt logic

-- Basic timer

-- Timer 1 (Timer A and B)

-- Watch timer

-- LCD controller

I/O port pins retain the mode (input or output) they had at the time Idle mode was entered.

Idle Mode Release

You can release Idle mode in one of two ways:

1. Execute a reset. All system and peripheral control registers are reset to their default values and the contents of

all data registers are retained. The reset automatically selects the slowest clock (1/16) because of the hardware
reset value for the CLKCON register. If all external interrupts are masked in the IMR register, a reset is the only
way you can release Idle mode.

2. Activate any enabled interrupt -- internal or external. When you use an interrupt to release Idle mode,

the 2-bit CLKCON.4/CLKCON.3 value remains unchanged, and the currently selected clock value is
used. The interrupt is then serviced. When the return-from-interrupt condition (IRET) occurs, the
instruction immediately following the one which initiated Idle mode is executed.

RESET

and POWER-DOWN

S3C9234/P9234

8-4

HARDWARE

RESET

VALUES

Table 8-1 list the values for CPU and system registers, peripheral control registers, and peripheral data registers
following a

RESET

operation in normal operating mode. The following notation is used in these table to represent

specific

RESET

values:

-- A "1" or a "0" shows the

RESET

bit value as logic one or logic zero, respectively.

-- An 'x' means that the bit value is undefined following

RESET

-- A dash ('') means that the bit is either not used or not mapped.

Table 8-1. Register Values after

RESET

Register Name

Mnemonic

Address

Bit Values after

RESET

Dec

Hex

SIO Control Register

SIOCON

208

D0H

SIO Data Register

SIODATA

209

D1H

SIO Prescaler Register

SIOPS

210

D2H

Oscillator Control Register

OSCCON

211

D3H

System Clock Control Register

CLKCON

212

D4H

System Flags Register

FLAGS

213

D5H

Stop Control Register

STPCON

214

D6H

LCD Control Register

LCON

215

D7H

Interrupt Pending Register

INTPND

216

D8H

Stack Pointer

217

D9H

Watch Timer Control Register

WTCON

218

DAH

Locations DBH is not mapped.

Basic Timer Control Register

BTCON

220

DCH

Basic Timer Counter

BTCNT

221

DDH

Locations DEH is not mapped.

System Mode Register

SYM

223

DFH

Port 0 Data Register

224

E0H

Port 1 Data Register

225

E1H

Port 2 Data Register

226

E2H

Port 3 Data Register

227

E3H

Port 4 Data Register

228

E4H

Port 5 Data Register

229

E5H

Port 6 Data Register

230

E6H

S3C9234/P9234

RESET

and POWER-DOWN

8-5

Table 8-1. Register Values after

RESET

(Continued)

Register Name

Mnemonic

Address

Bit Values after

RESET

Dec

Hex

Timer A Counter

TACNT

231

E7H

Timer B Counter

TBCNT

232

E8H

Timer A Data Register

TADATA

233

E9H

Timer B Data Register

TBDATA

234

EAH

Timer 1/A Control Register

TACON

235

EBH

Timer B Control Register

TBCON

236

ECH

Port 0 Control Register

P0CON

237

EDH

Port 1 Control Register(High Byte)

P1CONH

238

EEH

Port 1 Control Register(Low Byte)

P1CONL

239

EFH

Port 1 Pull-up Resistor Enable Register

P1PUR

240

F0H

Port 1 Interrupt Control Register

P1INT

241

F1H

Port 2 Control Register(High Byte)

P2CONH

242

F2H

Port 2 Control Register(Low Byte)

P2CONL

243

F3H

Port 2 Pull-up Resistor Enable Register

P2PUR

244

F4H

Port 2 Interrupt Control Register

P2INT

245

F5H

Port 3 Control Register(High Byte)

P3CONH

246

F6H

Port 3 Control Register(Low Byte)

P3CONL

247

F7H

Port 3 Pull-up Resistor Enable Register

P3PUR

248

F8H

Port 4 Control Register(High Byte)

P4CONH

249

F9H

Port 4 Control Register(Low Byte)

P4CONL

250

FAH

Port 5 Control Register(High Byte)

P5CONH

251

FBH

Port 5 Control Register(Low Byte)

P5CONL

252

FCH

Port 6 Control Register

P6CON

253

FDH

Clock Output Control Register

CLOCON

254

FEH

Location FFH is not mapped.

S3C9234/P9234

I/O PORTS

9-1

I/O PORTS

OVERVIEW

The S3C9234/P9234 microcontroller has seven bit-programmable I/O ports, P0-P6. Port 0 is 4-bit, port 1-port 6 are 8-
bit ports. This gives a total of 52 I/O pins. Each port can be flexibly configured to meet application design
requirements.

The CPU accesses ports by directly writing or reading port registers. No special I/O instructions are required. All
ports of the S3C9234/P9234 can be configured to input or output mode. P0 and P3-P6 are shared with LCD signals.

Table 9-1 gives you a general overview of S3C9234/P9234 I/O port functions.

Table 9-1. S3C9234/P9234 Port Configuration Overview

Port

Configuration Options

1-bit programmable I/O port.
Input or push-pull output and software assignable pull-ups.
P0.0-P0.3 can alternately used as outputs for LCD common signals.

1-bit programmable I/O port.
Schmitt trigger input or push-pull, open-drain output and software assignable pull-ups.
Alternatively P1.0-P1.2 can be used as input for external interrupts INT and P1.3-P1.7 can be
used as T1CLK, TAOUT, TBOUT, CLKOUT, BUZ.

1-bit programmable I/O port.
Schmitt trigger input or push-pull, open-drain output and software assignable pull-ups.
Alternatively P2.4-P2.7 can be used as input for external interrupts INT and P2.0-P2.2 can be
used as SCK, SO, and SI.

1-bit programmable I/O port.
Input or push-pull, open-drain output and software assignable pull-ups.
Alternatively P3 can be used as outputs for LCD segment signals.

1-bit programmable I/O port.
Input or push-pull output and software assignable pull-ups.
Alternatively P4 can be used as outputs for LCD segment signals.

1-bit programmable I/O port.
Input or push-pull output and software assignable pull-ups.
Alternatively P5 can be used as outputs for LCD segment signals.

2-bit programmable I/O port.
Input or push-pull output and software assignable pull-ups.
Alternatively P6 can be used as outputs for LCD segment signals.

I/O PORTS

S3C9234/P9234

9-2

PORT DATA REGISTERS

Table 9-2 gives you an overview of the register locations of all seven S3C9234/P9234 I/O port data registers. Data
registers for ports 0, 1, 2, 3, 4, 5, and 6 have the general format shown in Figure 9-1.

Table 9-2. Port Data Register Summary

Register Name

Mnemonic

Decimal

Hex

R/W

Port 0 data register

224

E0H

R/W

Port 1 data register

225

E1H

R/W

Port 2 data register

226

E2H

R/W

Port 3 data register

227

E3H

R/W

Port 4 data register

228

E4H

R/W

Port 5 data register

229

E5H

R/W

Port 6 data register

230

E6H

R/W

MSB

S3C9234/P9234 I/O Port Data Register Format (n = 0-6)

LSB

Pn.7

Pn.6 Pn.5

Pn.4

Pn.3 Pn.2

Pn.1

Pn.0

Figure 9-1. S3C9234/P9234 I/O Port Data Register Format

S3C9234/P9234

I/O PORTS

9-3

PORT 0

Port 0 is an 4-bit I/O port with individually configurable pins. Port 0 pins are accessed directly by writing or reading
the port 0 data register, P0 at location E0H in page 0. P0.0-P0.3 can serve as inputs (with or without pull-up), as
push-pull output. You can be configured the following alternative functions.

-- Low-nibble pins (P0.0-P0.3): COM0-COM3

Port 0 Control register (P0CON)

Port 0 has a 8-bit control register: P0CON for P0.0-P0.3. A reset clears the P0CON register to "00H", configuring
pins to input mode. You use control register setting to select input (with or without pull-up) or push-pull output mode
and enable the alternative functions.

When programming this port, please remember that any alternative peripheral I/O function you configure using the
port 0 control register must also be enabled in the associated peripheral module.

Port 0 Control Register (P0CON)

EDH, Page 0, R/W

MSB

LSB

P0.3/COM3

P0CON bit-pair pin configuration settings:

00
01
10
11

Push-pull output mode
Alternative function (CPM3-COM0)

P0.2/COM2 P0.1/COM1

P0.0/COM0

Input with pull-up resistor

Input mode

Figure 9-2. Port 0 Control Register (P0CON)

I/O PORTS

S3C9234/P9234

9-4

PORT 1

Port 1 is an 8-bit I/O port with individually configurable pins. Port 1 pins are accessed directly by writing or reading
the port 1 data register, P1 at location E1H in page 0. P1.0-P1.7 can serve as inputs (with or without pull-up), as
outputs (push-pull or open-drain) or you can be configured the following functions.

-- Low-nibble pins (P1.0-P1.3): INT, T1CLK

-- High-nibble pins (P1.4-P1.7): TAOUT, TBOUT, CLKOUT, BUZ

Port 1 Control Register (P1CONH, P1CONL)

Port 1 has two 8-bit control register: P1CONH for P1.4-P1.7 and P1CONL for P1.0-P1.3. A reset clears the P1CONH
and P1CONL register to "00H", configuring P1.0-P1.2 pins to input mode with interrupt and P1.3-P1.7 input mode.
You use control register setting to select input or output mode (push-pull or open-drain) and enable the alternative
functions.

When programming this port, please remember that any alternative peripheral I/O function you configure using the
port 1 control register must also be enabled in the associated peripheral module.

Port 1 Pull-up Resistor Control Register (P1PUR)

Using the port 1 pull-up resistor control register, P1PUR (F0H, page 0), you can configure pull-up resistors to
individual port 1 pins.

Port 1 Interrupt Control Registers (P1INT, INTPND.2-.0)

To process external interrupts at the port 1 pins, two additional control registers are provided: the port 1 interrupt
control register P1INT (F1H, page 0), the port 1 interrupt pending bits INTPND.2-.0 (D8H, page 0).

The port 1 interrupt pending register bits lets you check for interrupt pending conditions and clear the pending
condition when the interrupt service routine has been initiated. The application program detects interrupt requests by
polling the INTPND.2-.0 register at regular intervals.

When the interrupt enable bit of any port 1 pin is "1", a rising or falling edge at that pin will generate an interrupt
request. The corresponding INTPND bit is then automatically set to "1" and the IRQ level goes low to signal the CPU
that an interrupt request is waiting. When the CPU acknowledges the interrupt request, application software must the
clear the pending condition by writing a "0" to the corresponding INTPND bit.

S3C9234/P9234

I/O PORTS

9-5

Port 1 Control Register, High Byte (P1CONH)

EEH, Page 0, R/W

MSB

LSB

P1.7/BUZ

P1CONH bit-pair pin configuration settings:

00
01
10
11

Push-pull output mode
Alternative function
(BUZ, CLKOUT, TBOUT, TAOUT)

P1.6/CLKOUT P1.5/TBOUT P1.4/TAOUT

N-channel open-drain output mode

Schmitt trigger input mode

Figure 9-3. Port 1 High-Byte Control Register (P1CONH)

Port 1 Control Register, Low Byte (P1CONL)

EFH, Page 0, R/W

MSB

LSB

P1.3/T1CLK

P1CONL bit-pair pin configuration settings:

00
01
10
11

Not available

P1.2/INT

P1.1/INT

P1.0/INT

Schmitt trigger input mode (T1CLK)
N-channel open-drain output mode
Push-pull output mode

Figure 9-4. Port 1 Low-Byte Control Register (P1CONL)

I/O PORTS

S3C9234/P9234

9-6

Port 1 Pull-up Control Register (P1PUR)

F0H, Page 0, R/W

MSB

LSB

P1PUR bit configuration settings:

0
1

Enable pull-up resistor

Disable pull-up resistor

P1.3

P1.2

P1.1 P1.0

P1.7 P1.6

P1.5

P1.4

NOTE:

A pull-up resistor of port1 is automatically disabled when the
corresponding pin is selected as push-pull output or alternative
function.

Figure 9-5. Port 1 Pull-up Control Register (P1PUR)

Port 1 Interrupt Control Register (P1INT)

F1H, Page 0, R/W

MSB

LSB

Not used

P1INT bit configuration settings:

00
01

Enable interrupt by falling edge

Disable interrupt

10
11

Enable interrupt by both falling and rising edge

Enable interrupt by rising edge

P1.2 (INT)

P1.1 (INT)

P1.0 (INT)

Figure 9-6. Port 1 Interrupt Control Register (P1INT)

I/O PORTS

S3C9234/P9234

9-8

PORT 2

Port 2 is an 8-bit I/O port with individually configurable pins. Port 2 pins are accessed directly by writing or reading
the port 2 data register, P2 at location E2H in page 0. P2.0-P2.7 can serve as inputs (with or without pull-up), as
outputs (push-pull or open-drain) or you can be configured the following functions.

-- Low-nibble pins (P2.0-P2.3): SCK, SO, SI

-- High-nibble pins (P2.4-P2.7): INT

Port 2 Control Register (P2CONH, P2CONL)

Port 2 has two 8-bit control register: P2CONH for P2.4-P2.7 and P2CONL for P2.0-P2.3. A reset clears the
P2CONH/P2CONL register to "00H", configuring P2.4-P2.7 pins to input mode with interrupt and P2.0-P2.3 input
mode. You use control register setting to select input or output mode (push-pull or open-drain) and enable the
alternative functions.

When programming this port, please remember that any alternative peripheral I/O function you configure using the
port 2 control register must also be enabled in the associated peripheral module.

Port 2 Pull-up Resistor Control Register (P2PUR)

Using the port 2 pull-up resistor control register, P2PUR (F4H, page 0), you can configure pull-up resistors to
individual port 2 pins.

Port 2 Interrupt Control Registers (P2INT, INTPND.4-.7)

To process external interrupts at the port 2 pins, two additional control registers are provided: the port 2 interrupt
control register P2INT (F5H, page 0), the port 2 interrupt pending bits INTPND.4-.7 (D8H, page 0).

The port 2 interrupt pending register bits lets you check for interrupt pending conditions and clear the pending
condition when the interrupt service routine has been initiated. The application program detects interrupt requests by
polling the INTPND.4-.7 register at regular intervals.

When the interrupt enable bit of any port 2 pin is "1", a rising or falling edge at that pin will generate an interrupt
request. The corresponding INTPND bit is then automatically set to "1" and the IRQ level goes low to signal the CPU
that an interrupt request is waiting. When the CPU acknowledges the interrupt request, application software must the
clear the pending condition by writing a "0" to the corresponding INTPND bit.

S3C9234/P9234

I/O PORTS

9-9

Port 2 Control Register, High Byte (P2CONH)

F2H, Page 0, R/W

MSB

LSB

P2.7 (INT)

P2CONH bit-pair pin configuration settings:

00
01
10
11

Not available

P2.6 (INT)

P2.5 (INT)

P2.4 (INT)

Schmitt trigger input mode
N-channel open-drain output mode
Push-pull output mode

Figure 9-8. Port 2 High-byte Control Register (P2CONH)

Port 2 Control Register, Low Byte (P2CONL)

F3H, Page 0, R/W

MSB

LSB

P2.3

P2CONL bit-pair pin configuration settings:

00
01
10
11

Alternative function (SCK, SO)

P2.2/SI

P2.1/SO

P2.0/SCK

Schmitt trigger input mode (SI,SCK)
N-channel open-drain output mode
Push-pull output mode

Figure 9-9. Port 2 Low-byte Control Register (P2CONL)

S3C9234/P9234

I/O PORTS

9-11

Port 2 Interrupt Control Register (P2INT)

F5H, Page 0, R/W

MSB

LSB

INT bit configuration settings:

0
1

Enable interrupt

Disable interrupt

EDG

INT

EDG

INT

EDG

INT

EDG

INT

EDG bit configuration settings:

0
1

Select rising edge

Select falling edge

Figure 9-11. Port 2 Interrupt Control Register (P2INT)

Port 2 Interrupt Pending Bits (INTPND.7-.4)

D8H, Page 0, R/W

MSB

LSB

INTPND bit configuration settings:

0
1

Not

used

Interrupt is pending (when read)

No interrupt pending (when read), clear pending bit (when write)

P1.2

(INT)

P1.1

(INT)

P1.0

(INT)

P2.7

(INT)

P2.6

(INT)

P2.5

(INT)

P2.4

(INT)

Figure 9-12. Port 2 Interrupt Pending Bits (INTPND.7-.4)

I/O PORTS

S3C9234/P9234

9-12

PORT 3

Port 3 is an 8-bit I/O port with individually configurable pins. Port 3 pins are accessed directly by writing or reading
the port 3 data register, P3 at location E3H in page 0. P3.0-P3.7 can serve as inputs (with or without pull-up), as
outputs (push-pull or open-drain) or you can be configured the following functions.

-- Low-nibble pins (P3.0-P3.3): SEG31-SEG28

-- High-nibble pins (P3.4-P3.7): SEG27-SEG24

Port 3 Control Register (P3CONH, P3CONL)

Port 3 has two 8-bit control register: P3CONH for P3.4-P3.7 and P3CONL for P3.0-P3.1. A reset clears the P3CON
register to "00H", configuring all pins to input mode. You use control register setting to select input or output mode
(push-pull or open-drain).

When programming this port, please remember that any alternative peripheral I/O function you configure using the
port 3 control register must also be enabled in the associated peripheral module.

Port 3 Pull-up Resistor Control Register (P3PUR)

Using the port 3 pull-up resistor control register, P3PUR (F8H, page 0), you can configure pull-up resistors to
individually port 3 pins.

Port 3 Control Register, High Byte (P3CONH)

F6H, Page 0, R/W

MSB

LSB

P3.5/SEG26 P3.4/SEG27

P3CONH bit-pair pin configuration settings:

00
01
10
11

Alternative fumction (SEG24-SEG27)

Input mode
N-channel open-drain output mode
Push-pull output mode

P3.6/SEG25

P3.7/SEG24

Figure 9-13. Port 3 High Byte Control Register (P3CONH)

S3C9234/P9234

I/O PORTS

9-13

Port 3 Control Register, Low Byte (P3CONL)

F7H, Page 0, R/W

MSB

LSB

P3.1/SEG30 P3.0/SEG31

P3CONL bit-pair pin configuration settings:

00
01
10
11

Alternative function (SEG28-SEG31)

Input mode
N-channel open-drain output mode
Push-pull output mode

P3.3/SEG28 P3.2/SEG29

Figure 9-14. Port 3 Low Byte Control Register (P3CONL)

Port 3 Pull-up Control Register (P3PUR)

F8H, Page 0, R/W

MSB

LSB

P3PUR bit configuration settings:

0
1

Enable pull-up resistor

Disable pull-up resistor

P3.1 P3.0

P3.3

P3.2

P3.5

P3.4

P3.7 P3.6

NOTE:

A pull-up resistor of port3 is automatically disabled when the
corresponding pin is selected as push-pull output or alternative
function.

Figure 9-15. Port 3 Pull-up Control Register (P3PUR)

I/O PORTS

S3C9234/P9234

9-14

PORT 4

Port 4 is an 8-bit I/O port with individually configurable pins. Port 4 pins are accessed directly by writing or reading
the port 4 data register, P4 at location E4H in page 0. P4.0-P4.7 can serve as inputs (with or without pull-up), as
push-pull outputs:

-- Low-nibble pins (P4.0-P4.3): SEG23-SEG20

-- High-nibble pins (P4.4-P4.7): SEG19-SEG16

Port 4 Control Registers (P4CONH, P4CONL)

Port 4 has two 8-bit control registers: P4CONH for P4.4-P4.7 and P4CONL for P4.0-P4.3. A reset clears the
P4CONH and P4CONL registers to "00H", configuring all pins to input mode. You use control registers setting to
select input or output mode.

Port 3 Control Register, High Byte (P4CONH)

F9H, Page 0, R/W

MSB

LSB

P4.5/SEG18 P4.4/SEG19

P4CONH bit-pair pin configuration settings:

00
01
10
11

Push-pull output mode
Alternative function (SEG16-SEG19)

Input with pull-up resistor

Input mode

P4.7/SEG16 P4.6/SEG17

Figure 9-16. Port 4 High-Byte Control Register (P4CONH)

Port 4 Control Register, Low Byte (P4CONL)

FAH, Page 0, R/W

MSB

LSB

P4.1/SEG22 P4.0/SEG23

P4CONH bit-pair pin configuration settings:

00
01
10
11

Push-pull output mode
Alternative function (SEG20-SEG23)

Input with pull-up resistor

Input mode

P4.2/SEG21

P4.3/SEG20

Figure 9-17. Port 4 Low-Byte Control Register (P4CONL)

S3C9234/P9234

I/O PORTS

9-15

PORT 5

Port 5 is an 8-bit I/O port with individually configurable pins. Port 5 pins are accessed directly by writing or reading
the port 5 data register, P5 at location E5H in page 0. P5.0-P5.7 can serve as inputs (with or without pull-up), as
push-pull outputs.

-- Low-nibble pins (P5.0-P5.3): SEG15-SEG12

-- High-nibble pins (P5.4-P5.7): SEG11-SEG8

Port 5 Control Registers (P5CONH, P5CONL)

Port 5 has two 8-bit control registers: P5CONH for P5.4-P5.7 and P5CONL for P5.0-P5.3. A reset clears the
P5CONH and P5CONL registers to "00H", configuring all pins to input mode. You use control registers setting to
select input or output mode.

Port 5 Control Register, High Byte (P5CONH)

FBH, Page 0, R/W

MSB

LSB

P5.5/SEG10 P5.4/SEG11

P5CONH bit-pair pin configuration settings:

00
01
10
11

Push-pull output mode
Alternative function (SEG8-SEG11)

Input with pull-up resistor

Input mode

P5.6/SEG9

P5.7/SEG8

Figure 9-18. Port 5 High-Byte Control Register (P5CONH)

Port 5 Control Register, Low Byte (P5CONL)

FCH, Page 0, R/W

MSB

LSB

P5.1/SEG14 P5.0/SEG15

P5CONL bit-pair pin configuration settings:

00
01
10
11

Push-pull output mode
Alternative function (SEG12-SEG15)

Input with pull-up resistor

Input mode

P5.2/SEG13

P5.3/SEG12

Figure 9-19. Port 5 Low-Byte Control Register (P5CONL)

I/O PORTS

S3C9234/P9234

9-16

PORT 6

Port 6 is an 8-bit I/O port with bit-pair configurable pins. Port 6 pins are accessed directly by writing or reading the
port 6 data register, P6 at location E6H in page 0. P6.0-P6.7 can serve as inputs or as push-pull outputs:

-- Low-nibble pins (P6.0-P6.3): SEG7-SEG4

-- High-nibble pins (P6.4-P6.7): SEG3-SEG0

Port 6 Control Register (P6CON)

Port 6 has a 8-bit control register: P6CON for P6.0-P6.7. A reset clears the P6CON registers to "00H", configuring all
pins to input mode. You use control registers setting to select input or output mode.

Port 6 Control Register (P6CON)

FDH, Page 0, R/W

MSB

LSB

P6.3-P6.2/

SEG4-SEG5

P6.1-P6.0/

SEG6-SEG7

P6CON bit-pair pin configuration settings:

00
01
10
11

Push-pull output mode
Alternative function (SEG0-SEG7)

Input with pull-up resistor

Input mode

P6.5-P6.4/

SEG2-SEG3

P6.7-P6.6/

SEG0-SEG1

Figure 9-20. Port 6 Control Register (P6CON)

S3C9234/P9234

BASIC TIMER

10-1

BASIC TIMER

OVERVIEW

Basic timer (BT) can be used in two different ways:

-- As a watchdog timer to provide an automatic reset mechanism in the event of a system malfunction.

-- To signal the end of the required oscillation stabilization interval after a reset or a stop mode release.

The functional components of the basic timer block are:

-- Clock frequency divider (f

divided by 4096, 1024, 128, or 16) with multiplexer

-- 8-bit basic timer counter, BTCNT (DDH, read-only)

-- Basic timer control register, BTCON (DCH, read/write)

BASIC TIMER

S3C9234/P9234

10-2

BASIC TIMER CONTROL REGISTER (BTCON)

The basic timer control register, BTCON, is used to select the input clock frequency, to clear the basic timer counter
and frequency dividers, and to enable or disable the watchdog timer function. It is located in page 0, address DCH,
and is read/write addressable using Register addressing mode.

A reset clears BTCON to "00H". This enables the watchdog function and selects a basic timer clock frequency of
f

/4096. To disable the watchdog function, you must write the signature code "1010B" to the basic timer register

control bits BTCON.7BTCON.4.

The 8-bit basic timer counter, BTCNT (page 0, DDH), can be cleared at any time during normal operation by writing a
"1" to BTCON.1. To clear the frequency dividers for the basic timer input clock and timer counters, you write a "1" to
BTCON.0.

Basic TImer Control Register (BTCON)

DCH, R/W

MSB

LSB

Divider clear bit for basic timer
and timer counters:
0 = No effect
1 = Clear divider

Basic timer counter clear bit:
0 = No effect
1 = Clear BTCNT

Basic timer input clock selection bits:
00 = f

/4096

01 = f

/1024

10 = f

/128

11 = f

/16

Watchdog function enable bits:
1010B
Other Value

= Disable watchdog timer
= Enable watchdog timer

Figure 10-1. Basic Timer Control Register (BTCON)

S3C9234/P9234

BASIC TIMER

10-3

BASIC TIMER FUNCTION DESCRIPTION

Watchdog Timer Function

You can program the basic timer overflow signal (BTOVF) to generate a reset by setting BTCON.7BTCON.4 to any
value other than "1010B". (The "1010B" value disables the watchdog function.) A reset clears BTCON to "00H",
automatically enabling the watchdog timer function. A reset also selects the CPU clock (as determined by the
current CLKCON register setting), divided by 4096, as the BT clock.

A reset whenever a basic timer counter overflow occurs. During normal operation, the application program must
prevent the overflow, and the accompanying reset operation, from occurring. To do this, the BTCNT value must be
cleared (by writing a "1" to BTCON.1) at regular intervals.

If a system malfunction occurs due to circuit noise or some other error condition, the BT counter clear operation will
not be executed and a basic timer overflow will occur, initiating a reset. In other words, during normal operation, the
basic timer overflow loop (a bit 7 overflow of the 8-bit basic timer counter, BTCNT) is always broken by a BTCNT clear
instruction. If a malfunction does occur, a reset is triggered automatically.

Oscillation Stabilization Interval Timer Function

You can also use the basic timer to program a specific oscillation stabilization interval following a reset or when stop
mode has been released by an external interrupt.

In stop mode, whenever a reset or an internal and an external interrupt occurs, the oscillator starts. The BTCNT value
then starts increasing at the rate of fxx/4096 (for reset), or at the rate of the preset clock source (for an internal and
an external interrupt). When BTCNT.3 overflows, a signal is generated to indicate that the stabilization interval has
elapsed and to gate the clock signal off to the CPU so that it can resume normal operation.

In summary, the following events occur when stop mode is released:

1. During stop mode, a power-on reset or an internal and an external interrupt occurs to trigger the stop mode

release and oscillation starts.

2. If a power-on reset occurred, the basic timer counter will increase at the rate of fx

/4096. If an internal and an

external interrupt is used to release stop mode, the BTCNT value increases at the rate of the preset clock
source.

3. Clock oscillation stabilization interval begins and continues until bit 3 of the basic timer counter overflows.

4. When a BTCNT.3 overflow occurs, normal CPU operation resumes.

S3C9234/P9234

TIMER 1

11-1

TIMER 1

ONE 16-BIT TIMER MODE (TIMER 1)

The 16-bit timer 1 is used in one 16-bit timer or two 8-bit timers mode. If TACON.7 is set to "1", timer 1 is used as a
16-bit timer. If TACON.7 is set to "0", timer 1 is used as two 8-bit timers.

-- One 16-bit timer mode (Timer 1)

-- Two 8-bit timers mode (Timer A and B)

OVERVIEW

The 16-bit timer 1 is an 16-bit general-purpose timer. Timer 1 has the interval timer mode by using the appropriate
TACON setting.

Timer 1 has the following functional components:

-- Clock frequency divider (fxx divided by 512, 256, 64, 8, or 1, fxt, and T1CLK: External clock) with multiplexer

-- 16-bit counter (TACNT, TBCNT), 16-bit comparator, and 16-bit reference data register (TADATA, TBDATA)

-- Timer 1 match interrupt generation

-- Timer 1 control register, TACON (page 0, EBH, read/write)

FUNCTION DESCRIPTION

Interval Timer Function

The timer 1 module can generate an interrupt: the timer 1 match interrupt (T1INT).

The T1INT pending condition should be cleared by software when it has been serviced. Even though T1INT is
disabled, the application's service routine can detect a pending condition of T1INT by the software and execute it's
sub-routine. When this case is used, the T1INT pending bit must be cleared by the application sub-routine by writing
a "0" to the TACON.0 pending bit.

In interval timer mode, a match signal is generated when the counter value is identical to the values written to the
timer 1 reference data registers, TADATA and TBDATA. The match signal generates a timer 1 match interrupt and
clears the counter.

If, for example, you write the value 32H and 10H to TADATA and TBDATA, respectively, and 8EH to TACON, the
counter will increment until it reaches 3210H. At this point, the timer 1 interrupt request is generated, the counter
value is reset, and counting resumes.

TIMER 1

S3C9234/P9234

11-2

Timer 1 Control Register (TACON)

You use the timer 1 control register, TACON, to

-- Enable the timer 1 operating (interval timer)

-- Select the timer 1 input clock frequency

-- Clear the timer 1 counter, TACNT and TBCNT

-- Enable the timer 1 interrupt

TACON is located in page 0, at address EBH, and is read/write addressable using register addressing mode.

A reset clears TACON to "00H". This sets timer 1 to disable interval timer mode, selects an input clock frequency of
fxx/512, and disables timer 1 interrupt. You can clear the timer 1 counter at any time during normal operation by
writing a "1" to TACON.3.

To enable the timer 1 interrupt, you must write TACON.7, TACON.2, and TACON.1 to "1".
To generate the exact time interval, you should write TACON.3 and TACON.0 to "10B", which cleared counter and
interrupt pending bit. To detect an interrupt pending condition when T1INT is disabled, the application program polls
pending bit, TACON.0. When a "1" is detected, a timer 1 interrupt is pending. When the T1INT sub-routine has been
serviced, the pending condition must be cleared by software by writing a "0" to the timer 1 interrupt pending bit,
TACON.0.

Timer A Control Register (TACON)

EBH, R/W

MSB

LSB

Timer 1/A interrupt enable bit:
0 = Disable interrupt
1 = Enable interrupt

Timer 1 interrupt pending bit:
0 = No interrupt pending (when read)
Clear pending bit (when write)
1 = Interrupt is pending (when read)
No effect (when write)

Timer 1/A counter enable bit:
0 = Disable counting operation
1 = Enable counting operation

Timer 1/A counter clear bit:
0 = No affect
1 = Clear the timer 1/A counter (when write)

One 16-bit timer or Two 8-bit timers
mode:
0 = Two 8-bit timers mode (Timer A/B)
1 = One 16-bit timer mode (Timer 1)

Timer 1/A clock selection bits:
000 = fxx/512
001 = fxx/256
010 = fxx/64
011 = fxx/8
100 = fxx
101 = fxt (sub clock)
110 = T1CLK (external clock)
111 = Not available

Figure 11-1. Timer 1 Control Register (TACON)

TIMER 1

S3C9234/P9234

11-4

TWO 8-BIT TIMERS MODE (TIMER A and B)

OVERVIEW

The 8-bit timer A and B are the 8-bit general-purpose timers. Timer A and B have the interval timer mode by using
the appropriate TACON and TBCON setting, respectively.

Timer A and B have the following functional components:

-- Clock frequency divider with multiplexer

fxx divided by 512, 256, 64, 8 or 1, fxt, and T1CLK (External clock) for timer A
fxx divided by 512, 256, 64 or 8 and fxt for timer B

-- 8-bit counter (TACNT, TBCNT), 8-bit comparator, and 8-bit reference data register (TADATA, TBDATA)

-- Timer A have I/O pin for match output (TAOUT)

-- Timer A match interrupt generation

-- Timer A control register, TACON (page 0, EBH, read/write)

-- Timer B have I/O pin for match output (TBOUT)

-- Timer B match interrupt generation

-- Timer B control register, TBCON (page 0, ECH, read/write)

Timer A and B Control Register (TACON, TBCON)

You use the timer A and B control register, TACON and TBCON, to

-- Enable the timer A (interval timer mode) and B operating (interval timer mode)

-- Select the timer A and B input clock frequency

-- Clear the timer A and B counter, TACNT and TBCNT

-- Enable the timer A and B interrupt

S3C9234/P9234

TIMER 1

11-5

TACON and TBCON are located in page 0, at address EBH and ECH, and is read/write addressable using register
addressing mode.

A reset clears TACON to "00H". This sets timer A to disable interval timer mode, selects an input clock frequency of
fxx/512, and disables timer A interrupt. You can clear the timer A counter at any time during normal operation by
writing a "1" to TACON.3.

A reset clears TBCON to "00H". This sets timer B to disable interval timer mode, selects an input clock frequency of
fxx/512, and disables timer A interrupt. You can clear the timer B counter at any time during normal operation by
writing a "1" to TBCON.3.

To enable the timer A interrupt (TAINT) and timer B interrupt (TBINT), you must write TACON.7 to "0", TACON.2
(TBCON.2) and TACON.1 (TBCON.1) to "1". To generate the exact time interval, you should write TACON.3
(TBCON.3) and TACON.0 (TBCON.0), which cleared counter and interrupt pending bit. To detect an interrupt pending
condition when TAINT and TBINT is disabled, the application program polls pending bit, TACON.0 and TBCON.0.
When a "1" is detected, a timer A interrupt (TAINT) and timer B interrupt (TBINT) is pending. When the TAINT and
TBINT sub-routine has been serviced, the pending condition must be cleared by software by writing a "0" to the timer
A and B interrupt pending bit, TACON.0 and TBCON.0.

Timer A Control Register (TACON)

EBH, R/W

MSB

LSB

Timer A interrupt enable bit:
0 = Disable interrupt
1 = Enable interrupt

Timer A interrupt pending bit:
0 = No interrupt pending (when read)
Clear pending bit (when write)
1 = Interrupt is pending (when read)
No effect (when write)

Timer A counter enable bit:
0 = Disable counting operation
1 = Enable counting operation

Timer A counter clear bit:
0 = No affect
1 = Clear the timer 1/A counter (when write)

One 16-bit timer or Two 8-bit timers
mode:
0 = Two 8-bit timers mode (Timer A/B)
1 = One 16-bit timer mode (Timer 1)

Timer 1/A clock selection bits:
000 = fxx/512
001 = fxx/256
010 = fxx/64
011 = fxx/8
100 = fxx
101 = fxt (sub clock)
110 = T1CLK (external clock)
111 = Not available

Figure 11-3. Timer A Control Register (TACON)

TIMER 1

S3C9234/P9234

11-6

Timer B Control Register (TBCON)

ECH, R/W

MSB

LSB

Timer B match interrupt enable bit:
0 = Disable match interrupt
1 = Enable match interrupt

Timer B interrupt pending bits:
0 = No interrupt pending (when read)
Clear pending bit (when write)
1 = Interrupt is pending (when read)
No effect (when write)

Timer B count enable bit:
0 = Disable counting operating
1 = Enable counting operating

Timer B counter clear bit:
0 = No effect
1 = Clear the timer B counter (when write)

Not used

Timer B clock selection bits:
000 = fxx/512
001 = fxx/256
010 = fxx/64
011 = fxx/8
100 = fxt (sub clock)

Figure 11-4. Timer B Control Register (TBCON)

S3C9234/P9234

TIMER 1

11-7

FUNCTION DESCRIPTION

Interval Timer Function (Timer A and Timer B)

The timer A and B module can generate an interrupt: the timer A match interrupt (TAINT) and the timer B match
interrupt (TBINT).

The timer A match interrupt pending condition (TACON.0) and the timer B match interrupt pending condition
(TBCON.0) must be cleared by software in the application's interrupt service by means of writing a "0" to the
TACON.0 and TBCON.0 interrupt pending bit.

Even though TAINT and TBINT are disabled, the application's service routine can detect a pending condition of
TAINT and TBINT by the software and execute it's sub-routine. When this case is used, the TAINT and TBINT
pending bit must be cleared by the application sub-routine by writing a "0" to the corresponding pending bit
TACON.0 and TBCON.0.

In interval timer mode, a match signal is generated when the counter value is identical to the values written to the
timer A or timer B reference data registers, TADATA or TBDATA. The match signal generates corresponding match
interrupt and clears the counter.

If, for example, you write the value 20H to TADATA and 0EH to TACON, the counter will increment until it
reaches 20H. At this point, the timer A interrupt request is generated, the counter value is cleared, and counting
resumes and you write the value 10H to TBDATA, "0" to TACON.7, and 0EH to TBCON, the counter will increment
until it reaches 10H. At this point, TB interrupt request is generated, the counter value is cleared and
counting resumes.

S3P9234 (Preliminary Spec)

WATCH TIMER

12-1

WATCH TIMER

OVERVIEW

Watch timer functions include real-time and watch-time measurement and interval timing for the system clock. To
start watch timer operation, set bit 1 of the watch timer control register, WTCON.1 to "1".
And if you want to service watch timer overflow interrupt, then set the WTCON.6 to "1".
The watch timer overflow interrupt pending condition (WTCON.0) must be cleared by software in the application's
interrupt service routine by means of writing a "0" to the WTCON.0 interrupt pending bit.
After the watch timer starts and elapses a time, the watch timer interrupt pending bit (WTCON.0) is automatically
set to "1", and interrupt requests commence in 3.91ms, 0.25, 0.5 and 1-second intervals by setting Watch timer
speed selection bits (WTCON.3 .2).

The watch timer can generate a steady 0.5 kHz, 1 kHz, 2 kHz, or 4 kHz signal to BUZ output pin for Buzzer. By
setting WTCON.3 and WTCON.2 to "11b", the watch timer will function in high-speed mode, generating an interrupt
every 3.91 ms. High-speed mode is useful for timing events for program debugging sequences.

Also, you can select watch timer clock source by setting the WTCON.7 appropriately value.

The watch timer supplies the clock frequency for the LCD controller (f

LCD

). Therefore, if the watch timer is disabled,

the LCD controller does not operate.

Watch timer has the following functional components:

-- Real Time and Watch-Time Measurement

-- Using a Main or Sub Clock Source (Main clock divided by 2

(fx/128) or Sub clock(fxt))

-- Clock Source Generation for LCD Controller (f

LCD

)

-- I/O pin for Buzzer Output Frequency Generator (P1.7, BUZ)

-- Timing Tests in High-Speed Mode

-- Watch timer overflow interrupt generation

-- Watch timer control register, WTCON (page 0, DAH, read/write)

WATCH TIMER

S3P9234 (Preliminary Spec)

12-2

WATCH TIMER CONTROL REGISTER (WTCON)

The watch timer control register, WTCON is used to select the input clock source, the watch timer interrupt time and
Buzzer signal, to enable or disable the watch timer function. It is located in page 0 at address DAH, and is
read/write addressable using register addressing mode.
A reset clears WTCON to "00H". This disable the watch timer and select fx/128 as the watch timer clock.
So, if you want to use the watch timer, you must write appropriate value to WTCON.

Buzzer signal selection bits:
00 = 0.5 kHz
01 = 1 kHz
10 = 2 kHz
11 = 4 kHz

Watch Timer Control Register (WTCON)

DAH, R/W

MSB

LSB

Watch timer Enable/Disable bit:
0 = Disable watch timer;
clear frequency dividing circuits
1 = Enable watch timer

Watch timer interrupt pending bits:
0 = No interrupt pending (when read)
Clear pending bit (when write)
1 = Interrupt is pending (when read)
No effect (when write)

Watch timer speed selection bits:
00 = Set watch timer interrupt to 1 s
01 = Set watch timer interrupt to 0.5 s
10 = Set watch timer interrupt to 0.25 s
11 = Set watch timer interrupt to 3.91 ms

Watch timer clock selection bit:
0 = Main clock divided by
2

(fx/128)

1 = Sub clock (fxt)

Watch timer INT Enable/Disable bit:
0 = Disable watch timer INT
1 = Enable watch timer INT

Figure 12-1. Watch Timer Control Register (WTCON)

S3P9234 (Preliminary Spec)

WATCH TIMER

12-3

WATCH TIMER CIRCUIT DIAGRAM

WT INT Enable

WTCON.1

WTCON.2

WTCON.3

WTCON.4

WTCON.5

WTCON.6

Enable/Disable

Selector

Circuit

MUX

WTCON.0

WTINT

WTCON.6

/64 (0.5 kHz)

/32 (1 kHz)

/16 (2 kHz)

/8 (4 kHz)

(1 Hz)

= Main clock (where fx = 4.19 MHz)

fxt = Sub clock (32,768 Hz)
f

= Watch timer frequency

Clock

Selector

Frequency

Dividing

Circuit

32.768 kHz

fxt

LCD

= 2048 Hz

WTCON.7

WTCON.0

(Pending Bit)

BUZ (P1.7)

fx/128

Figure 12-2. Watch Timer Circuit Diagram

S3C9234/P9234

LCD CONTROLLER/DRIVER

13-1

LCD CONTROLLER/DRIVER

OVERVIEW

The S3C9234/P9234 microcontroller can directly drive an up-to-128-dot (32 segments x 4 commons) LCD panel. Its
LCD block has the following components:

-- LCD controller/driver

-- Display RAM (B0H-BFH of page 0) for storing display data

-- 32 segment output pins (SEG0SEG31)

-- 4 common output pins (COM0COM3)

-- Three LCD operating power supply pins (V

LC0

-V

LC2

)

-- Bias pin for controlling the driver and bias voltage

-- LCD bias by Internal/External register

Bit setting in the LCD control register, LCON, determine the LCD frame, duty and bias.

The LCD control register, LCON, is used to turn the LCD display on or off, to select LCD clock frequency, to select
bias and duty, and switch the current to the dividing resistor for the LCD display. Data written to the LCD display
RAM can be transferred to the segment signal pins automatically without program control.

When a sub clock is selected as the LCD clock source, the LCD display is enabled even during main clock stop and
idle modes.

Data BUS

Bias

SEG0-SEG31

COM0-COM3

LC0

-V

LC2

LCD

Controller/

Driver

Figure 13-1. LCD Function Diagram

S3C9234/P9234

LCD CONTROLLER/DRIVER

13-3

LCD RAM ADDRESS AREA

RAM addresses of page 0 are used as LCD data memory. When the bit value of a display segment is "1", the LCD
display is turned on; when the bit value is "0", the display is turned off.

Display RAM data are sent out through segment pins SEG0SEG31 using a direct memory access (DMA) method
that is synchronized with the f

LCD

signal. RAM addresses in this location that are not used for LCD

display can be allocated to general-purpose use.

COM0
COM1
COM2
COM3

b0 b4 b0 b4 b0 b4 b0 b4 b0 b4
b1 b5
b2 b6
b3 b7

b1 b5
b2 b6
b3 b7

0B0H 0B1H 0B2H 0B3H 0B4H

b0 b4 b0 b4 b0 b4
b1 b5
b2 b6
b3 b7

b1 b5
b2 b6
b3 b7

0BDH 0BEH 0BFH

SEG0

SEG1

SEG2

SEG3

SEG4

SEG5

SEG6

SEG7

SEG8

SEG9

SEG26

SEG27

SEG28

SEG29

SEG30

SEG31

Figure 13-3. LCD Display Data RAM Organization

Table 13-1. LCD Clock Signal Frame Frequency

LCDCK Frequency (f

LCD

)

Static

1/2 Duty

1/3 Duty

1/4 Duty

64 Hz

128 Hz

128

256Hz

256

128

512 Hz

512

256

171

128

LCD CONTROLLER/DRIVER

S3C9234/P9234

13-4

LCD CONTROL REGISTER (LCON)

A LCON is located in page 0, at address D7H, and is read/write addressable using register addressing mode. It has
the following control functions.

-- LCD duty and bias selection

-- LCD clock selection

-- LCD display control

-- Internal/External LCD dividing resistors selection

The LCON register is used to turn the LCD display on/off, to select duty and bias, to select LCD clock and control
the flow of the current to the dividing in the LCD circuit. Following a

RESET

, all LCON values are cleared to "0". This

turns off the LCD display, select 1/4 duty and 1/3 bias, select 64Hz for LCD clock, and Enable internal LCD dividing
resistors.

The LCD clock signal determines the frequency of COM signal scanning of each segment output. This is also
referred as the LCD frame frequency. Since the LCD clock is generated by watch timer clock (fw). The watch timer
should be enabled when the LCD display is turned on.

LCD Control Register (LCON)

D7H, R/W

MSB

LSB

Internal LCD dividing register enable bits:
0 = Enable internal LCD dividing resistors
1 = Disable internal LCD dividing resistors

Not used

LCD duty and bias selection bits:
000 = 1/4 duty, 1/3 bias
001 = 1/3 duty, 1/3 bias
010 = 1/3 duty, 1/2 bias
011 = 1/2 duty, 1/2 bias
1xx = static

LCD display control bit:
0 = All LCD signals are low
(Turn off the R-Tr)
1 = Turn display on
(Turn on the P-Tr)

LCD clock selection bits:
00 = fw/2

(64 Hz)

01 = fw/2

(128 Hz)

10 = fw/2

(256 Hz)

11 = fw/2

(512 Hz)

Figure 13-4. LCD Control Register (LCON)

S3C9234/P9234

LCD CONTROLLER/DRIVER

13-5

LCD VOLTAGE DIVIDING RESISTOR

NOTES:
1. R = Internal LCD dividing resistors. The resistors can be disconnected by LCON.7.
2. R' = External LCD dividing resistors.
3. R'' = External resistor to adjust V

LCD

S3C9234

Bias

LCON.0

LC0

LC2

LC1

LCD

LCON.7 = 0: Enable internal resistors

Static and 1/3 Bias (V

LCD

= 3V at V

= 5V)

1/2 Bias (V

LCD

= 2.5V at V

= 5V)

S3C9234

Bias

LCON.0

LC0

LC2

LC1

LCD

LCON.7 = 0: Enable internal resistors

S3C9234

Bias

LCON.0

LC0

LC2

LC1

LCD

LCON.7 = 0: Enable internal resistors

Static and 1/3 Bias (V

LCD

= 5V at V

= 5V)

Voltage Dividing Resistor Adjustment

S3C9234

Bias

LCON.0

LC0

LC2

LC1

R''

LCD

LCON.7 = 1: Disable internal resistors

Figure 13-5. Internal Voltage Dividing Resistor Connection

LCD CONTROLLER/DRIVER

S3C9234/P9234

13-6

COMMON (COM) SIGNALS

The common signal output pin selection (COM pin selection) varies according to the selected duty cycle.

-- In 1/4 duty mode, COM0-COM3 pins are selected

-- In 1/3 duty mode, COM0-COM2 pins are selected

-- In 1/2 duty mode, COM0-COM1 pins are selected

SEGMENT (SEG) SIGNALS

The 31 LCD segment signal pins are connected to corresponding display RAM locations at page 0. Bits of the
display RAM are synchronized with the common signal output pins.

When the bit value of a display RAM location is "1", a select signal is sent to the corresponding segment pin. When
the display bit is "0", a 'no-select' signal to the corresponding segment pin.

1 Frame

Select

Non-Select

COM

SEG

COM-SEG

LC0

-V

LC0

Figure 13-6. Select/No-Select Signals in Static Display Mode

S3C9234/P9234

LCD CONTROLLER/DRIVER

13-7

Select

Non-Select

1 Frame

COM

SEG

COM-SEG

LC1, 2

LC 0

-V

LC 0

-V

LC1, 2

LC 0

LC1, 2

LC 0

Figure 13-7. Select/No-Select Signal in 1/2 Duty, 1/2 Bias Display Mode

Select

Non-Select

1 Frame

SEG

COM

COM-SEG

LC0

LC1

LC2

LC0

LC1

LC2

LC0

LC1

LC2

-V

LC0

-V

LC1

-V

LC2

Figure 13-8. Select/No-Select Signal in 1/3 Duty, 1/3 Bias Display Mode

LCD CONTROLLER/DRIVER

S3C9234/P9234

13-8

1 Frame

COM0

COM1

SEG0

SEG1

COM0

-SEG0

COM0

-SEG1

COM1

-SEG0

COM1

-SEG1

NOTE:

LC2

= V

LC1

SEG1

SEG2

SEG3

SEG0

SEG3.1 x C1

.0 .1 .2 .3

.4 .5 .6 .7

.0 .1 .2 .3

.4 .5 .6 .7

Data Register page 4, address B0H

LD B0H, #31h

Data Register page 4, address B1H

LD B1H, #12h

COM0

COM1

SEG2.1 x C1

SEG0.0 x C0

SEG0.1 x C1

SEG1.0 x C0

SEG3.0 x C0

SEG2.1 x C1

SEG2.0 x C0

SEG1.1 x C1

-V

LC1, 2

-V

LC0

LC1, 2

LC0

LC1, 2

LC0

LC1, 2

LC0

LC1, 2

LC0

LC1, 2

LC0

LC1, 2

LC0

-V

LC1, 2

-V

LC0

LC1, 2

LC0

-V

LC1, 2

-V

LC0

LC1, 2

LC0

-V

LC1, 2

-V

LC0

Figure 13-9. LCD Signal and Wave Forms Example in 1/2 Duty, 1/2 Bias Display Mode

S3C9234/P9234

LCD CONTROLLER/DRIVER

13-9

COM0

COM1

SEG0

SEG1

COM0

-SEG0

COM0

-SEG1

COM1

-SEG0

COM1

-SEG1

COM2

1 Frame

SEG1.6 x C2

SEG2.1 x C1

SEG2.0 x C0

SEG0.0 x C0

SEG2.1 x C1

SEG1.4 x C0

SEG0.2 x C2

SEG2.0 x C0

SEG1.5 x C1

SEG0.1 x C1

COM0

COM1

SEG0

Data Register page 4, address B0H

LD B0H, #16h

SEG1

.4 .5 .6 .7

SEG2

.0 .1 .2 .3

COM2

.0 .1 .2 .3

SEG3

SEG4

.0 .1 .2 .3

Data Register page 4, address B2H

LD B2H, #33h

SEG5

.4 .5 .6 .7

Data Register page 4, address B1H

LD B1H, #43h

.4 .5 .6 .7

LC2

LC1

LC0

LC2

LC1

LC0

LC2

LC1

LC0

LC2

LC1

LC0

LC2

LC1

LC0

LC2

LC1

LC0

-V

LC1

-V

LC0

-V

LC2

LC1

LC0

-V

LC1

-V

LC0

-V

LC2

LC1

LC0

-V

LC1

-V

LC0

-V

LC2

LC1

LC0

-V

LC1

-V

LC0

-V

LC2

Figure 13-10. LCD Signals and Wave Forms Example in 1/3 Duty, 1/3 Bias Display Mode

LCD CONTROLLER/DRIVER

S3C9234/P9234

13-10

1 Frame

COM0

COM1

COM3

SEG0

COM0

-SEG0

COM0

-SEG1

COM1

-SEG1

COM2

SEG1

COM1

-SEG0

SEG1.7 x C3

SEG2.1 x C1

SEG1.4 x C0

SEG0.0 x C0

SEG0.1 x C1

SEG1.5 x C1

SEG0.3 x C3

SEG2.0 x C0

SEG1.6 x C2

SEG0.2 x C2

COM0

COM1

COM2

Data Register page 4, address B1H

LD B1H, #7Ah

SEG2

.0 .1 .2 .3

SEG3

.4 .5 .6 .7

Data Register page 4, address B2H

LD B2H, #63h

SEG4

.0 .1 .2 .3

SEG5

.4 .5 .6 .7

COM3

Data Register page 4, address B0H

LD B0H, #3Eh

SEG0

.0 .1 .2 .3

SEG1

.4 .5 .6 .7

LC2

LC1

LC0

LC2

LC1

LC0

LC2

LC1

LC0

LC2

LC1

LC0

LC2

LC1

LC0

LC2

LC1

LC0

LC2

LC1

LC0

-V

LC1

-V

LC0

-V

LC2

LC1

LC0

-V

LC1

-V

LC0

-V

LC2

LC1

LC0

-V

LC1

-V

LC0

-V

LC2

LC1

LC0

-V

LC1

-V

LC0

-V

LC2

Figure 13-11. LCD Signals and Wave Forms Example in 1/4 Duty, 1/3 Bias Display Mode

S3C9234/P9234

SERIAL I/O INTERFACE

14-1

SERIAL I/O INTERFACE

OVERVIEW

Serial I/O modules, SIO can interface with various types of external device that require serial data transfer. The
components of SIO function block are:

-- 8-bit control register (SIOCON)

-- Clock selector logic

-- 8-bit data buffer (SIODATA)

-- 8-bit prescaler (SIOPS)

-- 3-bit serial clock counter

-- Serial data I/O pins (SI, SO)

-- Serial clock input/output pin (SCK)

The SIO module can transmit or receive 8-bit serial data at a frequency determined by its corresponding control
register settings. To ensure flexible data transmission rates, you can select an internal or external clock source.

PROGRAMMING PROCEDURE

To program the SIO module, follow these basic steps:

1. Configure the I/O pins at port (SCK/SI/SO) by loading the appropriate value to the P2CON register if necessary.

2. Load an 8-bit value to the SIOCON control register to properly configure the serial I/O module. In this operation,

SIOCON.2 must be set to "1" to enable the data shifter.

3. For interrupt generation, set the serial I/O interrupt enable bit (SIOCON) to "1".

4. When you transmit data to the serial buffer, write data to SIODATA and set SIOCON.3 to 1, the shift operation

starts.

5. When the shift operation (transmit/receive) is completed, the SIO pending bit (SIOCON.0) are set to "1" and SIO

interrupt request is generated.

SERIAL I/O INTERFACE

S3C9234/P9234

14-2

SIO CONTROL REGISTERS (SIOCON)

The control register for serial I/O interface module, SIOCON, is located at D0H in page 0. It has the control setting
for SIO module.

-- Clock source selection (internal or external) for shift clock

-- Interrupt enable

-- Edge selection for shift operation

-- Clear 3-bit counter and start shift operation

-- Shift operation (transmit) enable

-- Mode selection (transmit/receive or receive-only)

-- Data direction selection (MSB first or LSB first)

A reset clears the SIOCON value to "00H". This configures the corresponding module with an internal clock source
at the SCK, selects receive-only operating mode, and clears the 3-bit counter. The data shift operation and the
interrupt are disabled. The selected data direction is MSB-first.

Serial I/O Module Control Register (SIOCON)

D0H, Page 0, R/W

MSB

LSB

SIO interrupt enable bit:
0 = Disable SIO interrupt
1 = Enable SIO interrupt

SIO interrupt pending bit:
0 = No interrupt pending (when read)
Clear pending bit (when write)
1 = Interrupt is pending

SIO shift operation enable bit:
0 = Disable shifter and clock counter
1 = Enable shifter and clock counter

Shift clock edge selection bit:
0 = t

at falling edeges, rx at rising edges.

1 = t

at rising edeges, rx at falling edges.

Data direction control bit:
0 = MSB-first mode
1 = LSB-first mode

SIO mode selection bit:
0 = Receive only mode
1 = Transmit/receive mode

SIO counter clear and shift start bit:
0 = No action
1 = Clear 3-bit counter and start shifting

SIO shift clock selection bit:
0 = Internal clock (P.S Clock)
1 = External clock (SCK)

Figure 14-1. Serial I/O Module Control Register (SIOCON)

S3C9234/P9234

SERIAL I/O INTERFACE

14-3

SIO PRE-SCALER REGISTER (SIOPS)

The prescaler register for serial I/O interface module, SIOPS, are located at D2H in page 0.
The value stored in the SIO pre-scaler register, SIOPS, lets you determine the SIO clock rate (baud rate) as follows:

Baud rate = Input clock (fxx/4)/(Prescaler value + 1), or SCK input clock.

SIO Pre-scaler Register (SIOPS)

D2H, Page 0, R/W

MSB

LSB

Baud rate = (f

/4)/(SIOPS + 1)

Figure 14-2. SIO Prescaler Register (SIOPS)

SIO BLOCK DIAGRAM

SIO INT

Pending

3-Bit Counter

Clear

SIOCON.0

fxx/2

SIOPS (D2H, page 0)

SCK

SIOCON.7

SIOCON.1

(Interrupt Enable)

CLK

SIOCON.3

Data Bus

1/2

8-bit P.S.

8-Bit SIO Shift Buffer

(SIODATA, D1H, page 0)

CLK

SIOCON.4

(Edge Select)

SIOCON.5

(Mode Select)

SIOCON.2

(Shift Enable)

SIOCON.6
(LSB/MSB First
Mode Select)

Figure 14-3. SIO Functional Block Diagram

SERIAL I/O INTERFACE

S3C9234/P9234

14-4

SERIAL I/O TIMING DIAGRAM (SIO)

Transmit
Complete

SIO INT

Set SIOCON.3

DO7

DO6

DO5

DO4

DO3

DO2

DO1

DO0

DI7

DI6

DI5

DI4

DI3

DI2

DI1

DI0

SCK

Figure 14-4. Serial I/O Timing in Transmit/Receive Mode (Tx at falling, SIOCON.4 = 0)

SIO INT

DO7

DO6

DO5

DO4

DO3

DO2

DO1

DO0

DI7

DI6

DI5

DI4

DI3

DI2

DI1

DI0

SCK

Transmit
Complete

Set SIOCON.3

Figure 14-5. Serial I/O Timing in Transmit/Receive Mode (Tx at rising, SIOCON.4 = 1)

S3C9234/P9234

ELECTRICAL DATA

15-1

ELECTRICAL DATA

OVERVIEW

In this chapter, S3C9234/P9234 electrical characteristics are presented in tables and graphs. The information is
arranged in the following order:

-- Absolute maximum ratings

-- D.C. electrical characteristics

-- Data retention supply voltage in Stop mode

-- Stop mode release timing when initiated by an external interrupt

-- Stop mode release timing when initiated by a Reset

-- I/O capacitance

-- A.C. electrical characteristics

-- Input timing for external interrupts

-- Input timing for

RESET

-- Serial data transfer timing

-- Oscillation characteristics

-- Oscillation stabilization time

-- Operating voltage range

ELECTRICAL DATA

S3C9234/P9234

15-2

Table 15-1. Absolute Maximum Ratings

= 25

Parameter

Symbol

Conditions

Rating

Unit

Supply voltage

0.3 to + 6.5

Input voltage

Ports 06

0.3 to

+ 0.3

Output voltage

0.3 to V

+ 0.3

Output current High

One I/O pin active

All I/O pins active

Output current Low

One I/O pin active

+ 30

Total pin current for ports

+ 100

Operating temperature

25 to + 85

Storage temperature

STG

65 to + 150

Table 15-2. D.C. Electrical Characteristics

= 25

C to + 85

C, V

= 2.0 V to 5.5 V)

Parameter

Symbol

Conditions

Min

Typ

Max

Unit

Operating Voltage

fx = 0 4.2MHz, fxt = 32.8kHz

2.0

5.5

fx = 0 8.0MHz

2.7

5.5

Input High

IH1

All input pins except for V

IH2

, V

IH3

0.7 V

voltage

IH2

Ports 1-2,

RESET

0.8 V

IH3

, X

OUT

and XT

, XT

OUT

0.1

Input Low voltage

IL1

All input pins except for V

IL2

, V

IL3

0.3 V

IL2

Ports 1-2,

RESET

0.2 V

IL3

, X

OUT

, XT

OUT

0.1

Output High
voltage

= 4.5 to 5.5 V;

All output ports; I

= 1 mA

1.0

Output Low
voltage

OL1

= 4.5 to 5.5 V

= 15mA

Ports 1-2

2.0

OL2

= 4.5 to 5.5 V

= 10mA

All output ports except for V

OL1

2.0

Input High leakage
current

LIH1

= V

All input pins except for I

LIH2

= V

, X

OUT

, XT

OUT

S3C9234/P9234

ELECTRICAL DATA

15-3

Table 15-2. D.C. Electrical Characteristics (Continued)

= 25

C to + 85

C, V

= 2.0 V to 5.5 V)

Parameter

Symbol

Conditions

Min

Typ

Max

Unit

Input Low
leakage current

LIL1

= 0 V;

All input pins except

RESET

, I

LIL2

= 0 V;

, X

OUT

, XT

OUT

Output High
leakage current

LOH

= V

All output pins

Output Low
leakage current

LOL

= 0 V

All output pins

Pull-Up Resistor

= 0 V; V

= 5V, T

= 25

Ports 06

100

= 3V, T

= 25

100

150

= 0 V; V

= 5V, T

= 25

RESET

150

250

400

= 3V, T

= 25

300

500

700

Oscillator Feed
back Resistors

OSC1

= 5 V, T

= 25

= V

, X

OUT

= 0V

300

600

1500

OSC2

= 5 V, T

= 25

= V

, XT

OUT

= 0 V

1500

3000

4500

LCD Voltage
Dividing Resistor

LCD

= 25

100

150

200

LCD

-COMi

Voltage Drop
(i = 0-3)

- 15

A per common pin

120

LCD

SEG

Voltage Drop
(x = 031)

- 15

A per common pin

120

Middle Output
Voltage

(1)

LC0

2.7 V to 5.5 V, 1/3 bias

LCD clock = 0Hz, V

LC1

= V

0.6V

0.2

0.6V

0.2

LC1

0.4V

0.2

0.4V

0.2

LC2

0.2V

0.2

0.2V

0.2

NOTE: It is middle output voltage when the Bias pin and the V

LC0

pin are opened.

ELECTRICAL DATA

S3C9234/P9234

15-4

Table 15-2. D.C. Electrical Characteristics (Concluded)

= 25

C to + 85

C, V

= 2.0 V to 5.5 V)

Parameter

Symbol

Conditions

Min

Typ

Max

Unit

Supply current

(1)

DD1

(2)

Run mode:
V

= 5 V

10%

8.0 MHz

6.0

12.0

Crystal oscillator
C1 = C2 = 22pF

4.0 MHz

2.6

5.2

= 3 V

10%

8.0 MHz

2.5

5.0

4.0 MHz

1.2

2.4

DD2

(2)

Idle mode:
V

= 5 V

10%

8.0 MHz

1.3

3.0

Crystal oscillator
C1 = C2 = 22pF

4.0 MHz

0.9

1.8

= 3 V

10%

8.0 MHz

0.8

1.6

4.0 MHz

0.4

0.8

DD3

(3)

Run mode: V

= 3 V

10%,

32 kHz crystal oscillator

15.0

30.0

DD4

(3)

Idle mode: V

= 3 V

10%,

32 kHz crystal oscillator

6.0

15.0

DD5

(4)

Stop mode; V

= 5 V

10%,

= 25

0.5

3.0

Stop mode; V

= 3 V

10%,

= 25

0.3

2.0

NOTES:
1. Supply current does not include current drawn through internal pull-up resistors, LCD voltage dividing resistors, and

external output current loads.

2. I

DD1

and I

DD2

include power consumption for subsystem clock oscillation.

3. I

DD3

and I

DD4

are current when main system clock oscillation stops and the subsystem clock is used.

DD5

is current when main system clock and subsystem clock oscillation stops.

Every values in this table is measured when bits 4-3 of the system clock control register (CLKCON.4-.3) is set to 11B.

S3C9234/P9234

ELECTRICAL DATA

15-5

Table 15-3. Data Retention Supply Voltage in Stop Mode

= 25

C to + 85

Parameter

Symbol

Conditions

Min

Typ

Max

Unit

Data retention supply
voltage

DDDR

2.0

5.5

Data retention supply
current

DDDR

Stop mode, T

= 25

DDDR

= 2.0 V

Execution of

STOP Instruction

Idle Mode

(Basic Timer Active)

~ ~

DDDR

~ ~

Stop Mode

Normal
Operating Mode

Data Retention Mode

0.8 V

WAIT

NOTE:

WAIT

is the same as 16 x 1/BT clock.

Figure 15-1. Stop Mode Release Timing When Initiated by an External Interrupt

ELECTRICAL DATA

S3C9234/P9234

15-6

Execution of

STOP Instrction

RESET

Occurs

~ ~

DDDR

~ ~

Stop Mode

Oscillation

Stabilization

TIme

Normal
Operating Mode

Data Retention Mode

WAIT

RESET

0.2 V

0.8 V

NOTE:

WAIT

is the same as 16

1/BT clock.

Figure 15-2. Stop Mode Release Timing When Initiated by a

RESET

Table 15-4. Input/Output Capacitance

= 25

C, V

0 V)

Parameter

Symbol

Conditions

Min

Typ

Max

Unit

Input
capacitance

f = 1 MHz; unmeasured pins

are connected to V

Output
capacitance

OUT

I/O capacitance

S3C9234/P9234

ELECTRICAL DATA

15-7

Table 15-5. A.C. Electrical Characteristics

= 25

C to + 85

C, V

= 2.0 V to 5.5 V)

Parameter

Symbol

Conditions

Min

Typ

Max

Unit

SCK cycle time

KCY

External SCK source

1,000

Internal SCK source

1,000

SCK high, low width

, t

External SCK source

500

Internal SCK source

KCY

/250

SI setup time to SCK
high

SIK

External SCK source

250

Internal SCK source

250

SI hold time to SCK high

KSI

External SCK source

400

Internal SCK source

400

Output delay for SCK to
SO

KSO

External SCK source

300

Internal SCK source

250

Interrupt input, High, Low
width

INTH

INTL

All interrupt
V

= 3 V

500

700

RESET

input Low width

RSL

Input
V

= 3 V

INTH

INTL

0.8 V

0.2 V

NOTE:

The unit t

CPU

means one CPU clock period.

External

Interrupt

Figure 15-3. Input Timing for External Interrupts

S3C9234/P9234

ELECTRICAL DATA

15-9

Table 15-6. Main Oscillation Characteristics

= 25

C to + 85

Oscillator

Clock Configuration

Parameter

Test Condition

Min

Typ

Max

Units

Crystal

OUT

Main oscillation
frequency

2.7 V 5.5 V

0.4

MHz

2.0 V 5.5 V

0.4

4.2

Ceramic
Oscillator

OUT

Main oscillation
frequency

2.7 V 5.5 V

0.4

2.0 V 5.5 V

0.4

4.2

External
Clock

OUT

input frequency

2.7 V 5.5 V

0.4

2.0 V 5.5 V

0.4

4.2

RC
Oscillator

OUT

Frequency

5.0 V

0.4

MHz

Frequency

3.0 V

0.4

Table 15-7. Sub Oscillation Characteristics

= 25

C to + 85

Oscillator

Clock Configuration

Parameter

Test Condition

Min

Typ

Max

Units

Crystal

OUT

Sub oscillation
frequency

2.0 V 5.5 V

32.768

kHz

External
clock

OUT

input

frequency

2.0 V 5.5 V

100

ELECTRICAL DATA

S3C9234/P9234

15-10

Table 15-8. Main Oscillation Stabilization Time

= 25

C to + 85

C, V

= 2.0 V to 5.5 V)

Oscillator

Test Condition

Min

Typ

Max

Unit

Crystal

fx > 1 MHz

Ceramic

Oscillation stabilization occurs when VDD is
equal to the minimum oscillator voltage
range.

External clock

input high and low width (t

, t

)

62.5

1250

-0.1 V

0.1 V

1/fx

Figure 15-6. Clock Timing Measurement at X

S3P9234 OTP

S3C9234/P9234

17-2

S3P9234

(64-QFP-1420F)

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19

51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33

COM0/P0.0
COM1/P0.1
COM2/P0.2
COM3/P0.3

BIAS

VLC0

SDAT/VLC1

SCLK/VLC2

OUT

/TEST

OUT

RESET/RESET

P1.0/INT
P1.1/INT
P1.2/INT

SEG0/P6.7

SEG1/P6.6

SEG2/P6.5

SEG3/P6.4

SEG4/P6.3

SEG5/P6.2

SEG6/P6.1

SEG7/P6.0

SEG8/P5.7

SEG9/P5.6

SEG10/P5.5

SEG11/P5.4

SEG12/P5.3

P1.3/T1CLK

P1.4/TAOUT

P1.5/TBOUT

P1.6/CLKOUT

P1.7/BUZ

P2.0/SCK

P2.1/SO

P2.2/SI

P2.3

P2.4/INT

P2.5/INT

P2.6/INT

P2.7/INT

Figure 17-1. S3P9234 Pin Assignments (64-QFP-1420F)

S3C9234/P9234

S3P9234 OTP

17-3

Table 17-1. Descriptions of Pins Used to Read/Write the EPROM

Main Chip

During Programming

Pin Name

Pin No.

I/O

Function

VLC1

SDAT

I/O

Serial data pin. Output port when reading and
input port when writing. Can be assigned as a
Input/push-pull output port.

VLC2

SCLK

I/O

Serial clock pin. Input only pin.

TEST

(TEST)

Power supply pin for EPROM cell writing
(indicates that OTP enters into the writing mode).
When 12.5 V is applied, OTP is in writing mode
and when 5 V is applied, OTP is in reading mode.
(Option)

RESET

Chip initialization

9 / 10

Logic power supply pin. V

should be tied to

+ 5 V during programming.

NOTE:

Parentheses indicate pin number for 64-pin-QFP-1420F package.

Table 17-2. Comparison of S3P9234 and S3C9234 Features

Characteristic

S3P9234

S3C9234

Program Memory

4 Kbyte EPROM

4 Kbyte mask ROM

Operating Voltage (V

)

2.0 V to 5.5 V

OTP Programming Mode

= 5 V, V

(TEST)=12.5V

Pin Configuration

64-QFP

EPROM Programmability

User Program 1 time

Programmed at the factory

OPERATING MODE CHARACTERISTICS

When 12.5 V is supplied to the V

(TEST) pin of the S3P72C8, the EPROM programming mode is entered.

The operating mode (read, write, or read protection) is selected according to the input signals to the pins listed in
Table 17-3 below.

Table 17-3. Operating Mode Selection Criteria

(TEST)

REG/

MEM

Address
(A15-A0)

R/W

Mode

5 V

0000H

EPROM read

12.5 V

0000H

EPROM program

12.5 V

0000H

EPROM verify

12.5 V

0E3FH

EPROM read protection

NOTE:

"0" means Low level; "1" means High level.

S3P9234 OTP

S3C9234/P9234

17-4

Table 17-4. D.C. Electrical Characteristics

= 25

C to + 85

C, V

= 2.0 V to 5.5 V)

Parameter

Symbol

Conditions

Min

Typ

Max

Unit

Supply current

(1)

DD1

Run mode:
V

= 5 V

10%

8.0 MHz

6.0

12.0

Crystal oscillator
C1 = C2 = 22pF

4.0 MHz

2.6

5.2

= 3 V

10%

8.0 MHz

2.5

5.0

4.0 MHz

1.2

2.4

DD2

Idle mode:
V

= 5 V

10%

8.0 MHz

1.3

3.0

Crystal oscillator
C1 = C2 = 22pF

4.0 MHz

0.9

1.8

= 3 V

10%

8.0 MHz

0.8

1.6

4.0 MHz

0.4

0.8

DD3

Run mode: V

= 3 V

10%,

32 kHz crystal oscillator

15.0

30.0

DD4

Idle mode: V

= 3 V

10%,

32 kHz crystal oscillator

6.0

15.0

DD5

Stop mode; V

= 5 V

10%,

= 25

0.5

3.0

Stop mode; V

= 3 V

10%,

= 25

0.3

2.0

NOTES:
1. Supply current does not include current drawn through internal pull-up resistors, LCD voltage dividing resistors, and

external output current loads.

2. I

DD1

and I

DD2

include power consumption for subsystem clock oscillation.

3. I

DD3

and I

DD4

are current when main system clock oscillation stops and the subsystem clock is used.

DD5

is current when main system clock and subsystem clock oscillation stops.

Every values in this table is measured when bits 4-3 of the system clock control register (CLKCON.4-.3) is set to 11B.

S3C9234/P9234

DEVELOPMENT TOOLS

18-1

DEVELOPMENT TOOLS

OVERVIEW

Samsung provides a powerful and easy-to-use development support system in turn key form. The development
support system is configured with a host system, debugging tools, and support software. For the host system, any
standard computer that operates with MS-DOS as its operating system can be used. One type of debugging tool
including hardware and software is provided: the sophisticated and powerful in-circuit emulator, SMDS2+, for S3C7,
S3C8, S3C9 families of microcontrollers. The SMDS2+ is a new and improved version of SMDS2. Samsung also
offers support software that includes debugger, assembler, and a program for setting options.

SHINE

Samsung Host Interface for In-Circuit Emulator, SHINE, is a multi-window based debugger for SMDS2+. SHINE
provides pull-down and pop-up menus, mouse support, function/hot keys, and context-sensitive hyper-linked help. It
has an advanced, multiple-windowed user interface that emphasizes ease of use. Each window can be sized, moved,
scrolled, highlighted, added, or removed completely.

SAMA ASSEMBLER

The Samsung Arrangeable Microcontroller (SAM) Assembler, SAMA, is a universal assembler, and generates object
code in standard hexadecimal format. Assembled program code includes the object code that is used for ROM data
and required SMDS program control data. To assemble programs, SAMA requires a source file and an auxiliary
definition (DEF) file with device specific information.

SASM86

The SASM86 is an relocatable assembler for Samsung's S3C9-series microcontrollers. The SASM86 takes a source
file containing assembly language statements and translates into a corresponding source code, object code and
comments. The SASM86 supports macros and conditional assembly. It runs on the MS-DOS operating system. It
produces the relocatable object code only, so the user should link object file. Object files can be linked with other
object files and loaded into memory.

HEX2ROM

HEX2ROM file generates ROM code from HEX file which has been produced by assembler. ROM code must be
needed to fabricate a microcontroller which has a mask ROM. When generating the ROM code (.OBJ file) by
HEX2ROM, the value "FF" is filled into the unused ROM area up to the maximum ROM size of the target device
automatically.

TARGET BOARDS

Target boards are available for all S3C9-series microcontrollers. All required target system cables and adapters are
included with the device-specific target board.

S3C9234/P9234

DEVELOPMENT TOOLS

18-3

TB9234 TARGET BOARD

The TB9234 target board is used for the S3C9234 microcontroller. It is supported by the SMDS2+ development
system.

TB9234

GND

To User_V

OFF

SMDS2

SMDS2+

J101

64QFP

J102

64QFP

160

150

140

130

100 110 120

RESET

7411

R7
R8

CB+

C15

C16

IDLE

STOP

76 26

REV.0

'2003. 05. 28

CN1

C12

JP6

C14

C11

R10

Figure 18-2. TB9234 Target Board Configuration

DEVELOPMENT TOOLS

S3C9234/P9234

18-4

Table 18-1. Power Selection Settings for TB9234

"To User_V

Settings

Operating Mode

Comments

To User_V

Off

Target

System

SMDS2/SMDS2+

TB9234

The SMDS2/SMDS2+ supplies
V

to the target board

(evaluation chip) and the target
system.

To User_V

Off

Target

System

SMDS2/SMDS2+

TB9234

External

The SMDS2/SMDS2+ supplies
V

only to the target board

(evaluation chip). The target
system must have its own
power supply.

NOTE:

The following symbol in the "To User_V

" Setting column indicates the electrical short (off) configuration:

S3C9234/P9234

DEVELOPMENT TOOLS

18-5

SMDS2+ Selection (SAM8)

In order to write data into program memory that is available in SMDS2+, the target board should be selected to be for
SMDS2+ through a switch as follows. Otherwise, the program memory writing function is not available.

Table 18-2. The SMDS2+ Tool Selection Setting

"SW1" Setting

Operating Mode

SMDS2

SMDS2+

Target

Board

R/W

SMDS2+

Table 18-3. Using Single Header Pins as the Input Path for External Trigger Sources

Target Board Part

Comments

External
Triggers

Ch1

Ch2

Connector from
External Trigger
Sources of the
Application System

You can connect an external trigger source to one of the two external
trigger channels (CH1 or CH2) for the SMDS2+ breakpoint and trace
functions.

IDLE LED

The Green LED is ON when the evaluation chip (S3E9230) is in idle mode.

STOP LED

The Red LED is ON when the evaluation chip (S3E9230) is in stop mode.

DEVELOPMENT TOOLS

S3C9234/P9234

18-6

SEG31/P3.0
SEG29/P3.2
SEG27/P3.4
SEG25/P3.6
SEG23/P4.0
SEG21/P4.2
SEG19/P4.4
SEG17/P4.6
SEG15/P5.0
SEG13/P5.2
SEG11/P5.4

SEG9/P5.6
SEG7/P6.0
SEG5/P6.2
SEG3/P6.4
SEG1/P6.6

N.C
N.C
N.C
N.C

COM1/P0.1
COM3/P0.3
VLC0
VLC2
GND
X

RESET

P1.1/INT
P1.3/T1CLK
P1.5/TBOUT
P1.7/BUZ
P2.1/SO
P2.3
P2.5/INT
P2.7/INT
N.C
N.C
N.C
N.C

J101

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39

2
4
6
8

10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40

J102

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39

2
4
6
8

10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40

COM0/P0.0
COM2/P0.2

BIAS

VLC1

OUT

TEST

OUT

P1.0/INT
P1.2/INT

P1.4/TAOUT

P1.6/CLKOUT

P2.0/SCK

P2.2/SI

P2.4/INT
P2.6/INT

N.C
N.C
N.C
N.C

SEG30/P3.1
SEG28/P3.3
SEG26/P3.5
SEG24/P3.7
SEG23/P4.1
SEG20/P4.3
SEG18/P4.5
SEG16/P4.7
SEG14/P5.1
SEG12/P5.3
SEG10/P5.5
SEG8/P5.7
SEG6/P6.1
SEG4/P6.3
SEG2/P6.5
SEG0/P6.7
N.C
N.C
N.C
N.C

Figure 18-3. Connectors (J101, J102) for TB9234

Target Board

40-Pin Connector

Target Cable for 40-pin Connector

Part Name: AS40D-A
Order Code: SM6306

J102

33 34

63 64

J101

31 32

Target Board

40-Pin Connector

J102

J101

33 34

63 64 31

Figure 18-4. S3C9234 Probe Adapter for 64-QFP Package

(For duplicate copies of this form, and for additional ordering information, please contact your local
Samsung sales representative. Samsung sales offices are listed on the back cover of this book.)

S3C9 SERIES MASK ROM ORDER FORM

Product description:

Device Number: S3C9__________- ___________(write down the ROM code number)
Product Order Form:

Package

Pellet Wafer

Package Type: __________

Package Marking (Check One):

Standard

Custom A

Custom B

(Max 10 chars)

(Max 10 chars each line)

@ : Assembly site code, Y : Last number of assembly year, WW : Week of assembly

@ YWW

Device Name

SEC

Device Name

@ YWW

Delivery Dates and Quantities:

Deliverable

Required Delivery Date

Quantity

Comments

ROM code

Not applicable

See ROM Selection Form

Customer sample

Risk order

See Risk Order Sheet

Please answer the following questions:

For what kind of product will you be using this order?

New product

Upgrade of an existing product

Replacement of an existing product

Other

If you are replacing an existing product, please indicate the former product name

(

)

What are the main reasons you decided to use a Samsung microcontroller in your product?

Please check all that apply.

Price

Product quality

Features and functions

Development system

Technical support

Delivery on time

Used same micom before

Quality of documentation

Samsung reputation

Mask Charge (US$ / Won):

____________________________

Customer Information:

Company Name:

___________________ Telephone number

_________________________

Signatures:

________________________

__________________________________

(Person placing the order)

(Technical Manager)

(For duplicate copies of this form, and for additional ordering information, please contact your local
Samsung sales representative. Samsung sales offices are listed on the back cover of this book.)

S3C9 SERIES

REQUEST FOR PRODUCTION AT CUSTOMER RISK

Customer Information:

Company Name:

________________________________________________________________

Department:

________________________________________________________________

Telephone Number:

__________________________

Fax: _____________________________

Date:

__________________________

Risk Order Information:

Device Number:

S3C9________- ________ (write down the ROM code number)

Package:

Number of Pins: ____________

Package Type: _____________________

Intended Application:

________________________________________________________________

Product Model Number:

________________________________________________________________

Customer Risk Order Agreement:

We hereby request SEC to produce the above named product in the quantity stated below. We believe our risk order
product to be in full compliance with all SEC production specifications and, to this extent, agree to assume
responsibility for any and all production risks involved.

Order Quantity and Delivery Schedule:

Risk Order Quantity:

_____________________ PCS

Delivery Schedule:

Delivery Date (s)

Quantity

Comments

Signatures:

_______________________________

_______________________________________

(Person Placing the Risk Order)

(SEC Sales Representative)

(For duplicate copies of this form, and for additional ordering information, please contact your local
Samsung sales representative. Samsung sales offices are listed on the back cover of this book.)

S3C9234 MASK OPTION SELECTION FORM

Device Number:

S3C9234-__________(write down the ROM code number)

Attachment (Check one):

Diskette

PROM

Customer Checksum:

________________________________________________________________

Company Name:

________________________________________________________________

Signature (Engineer):

________________________________________________________________

Please answer the following questions:

Application (Product Model ID: _______________________)

Audio

Video

Telecom

LCD Databank

Caller ID

LCD

Game

Industrials

Home Appliance

Office Automation

Remocon

Other

Please describe in detail its application

__________________________________________________________________________

(For duplicate copies of this form, and for additional ordering information, please contact your local
Samsung sales representative. Samsung sales offices are listed on the back cover of this book.)

S3P9 SERIES OTP FACTORY WRITING ORDER FORM (1/2)

Product Description:

Device Number:

S3P9________-________(write down the ROM code number)

Product Order Form:

Package

Pellet

Wafer

If the product order form is package:

Package Type: _____________________

Package Marking (Check One):

Standard

Custom A

Custom B

(Max 10 chars)

(Max 10 chars each line)

@ : Assembly site code, Y : Last number of assembly year, WW : Week of assembly

@ YWW

Device Name

SEC

Device Name

@ YWW

Delivery Dates and Quantity:

ROM Code Release Date

Required Delivery Date of Device

Quantity

Please answer the following questions:

What is the purpose of this order?

New product development

Upgrade of an existing product

Replacement of an existing microcontroller

Other

If you are replacing an existing microcontroller, please indicate the former microcontroller name

(

)

What are the main reasons you decided to use a Samsung microcontroller in your product?

Please check all that apply.

Price

Product quality

Features and functions

Development system

Technical support

Delivery on time

Used same micom before

Quality of documentation

Samsung reputation

Customer Information:

Company Name:

___________________ Telephone number

_________________________

Signatures:

________________________

__________________________________

(Person placing the order)

(Technical Manager)

(For duplicate copies of this form, and for additional ordering information, please contact your local
Samsung sales representative. Samsung sales offices are listed on the back cover of this book.)

S3P9234 OTP FACTORY WRITING ORDER FORM (2/2)

Device Number:

S3P9234 - __________(write down the ROM code number)

Customer Checksums:

_______________________________________________________________

Company Name:

________________________________________________________________

Signature (Engineer):

________________________________________________________________

Read Protection

(1)

: Yes

Please answer the following questions:

Are you going to continue ordering this device?

Yes

If so, how much will you be ordering? _________________pcs

Application (Product Model ID: _______________________)

Audio

Video

Telecom

LCD Databank

Caller ID

LCD Game

Industrials

Home Appliance

Office Automation

Remocon

Other

Please describe in detail its application

__________________________________________________________________________

NOTES
1.

Once you choose a read protection, you cannot read again the programming code from the EPROM.

OTP Writing will be executed in our manufacturing site.

The writing program is completely verified by a customer. Samsung does not take on any responsibility for errors
occurred from the writing program.

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: S3P9234

Document Outline

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: S3P9234

Document Outline

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: S3P9234