21-S3-C830A/P830A-032002
USER'S MANUAL
S3C830A/P830A
8-Bit CMOS
Microcontroller
Revision 1
S3C830A/P830A
PRODUCT OVERVIEW
1-1
1
PRODUCT OVERVIEW
S3C8-SERIES MICROCONTROLLERS
Samsung's S3C8 series of 8-bit single-chip CMOS microcontrollers offers a fast and efficient CPU, a wide range
of integrated peripherals, and various mask-programmable ROM sizes. Among the major CPU features are:
-- Efficient register-oriented architecture
-- Selectable CPU clock sources
-- Idle and Stop power-down mode release by interrupt
-- Built-in basic timer with watchdog function
A sophisticated interrupt structure recognizes up to eight interrupt levels. Each level can have one or more
interrupt sources and vectors. Fast interrupt processing (within a minimum of four CPU clocks) can be assigned
to specific interrupt levels.
S3C830A MICROCONTROLLER
The S3C830A single-chip microcontroller are fabricated using the highly advanced CMOS process. Its design is
based on the powerful SAM88RC CPU core. Stop and idle (power-down) modes were implemented to reduce
power consumption.
The S3C830A is a microcontroller with a 48K-byte mask-programmable ROM embedded.
The S3P830A is a microcontroller with a 48K-byte one-time-programmable ROM embedded.
Using the SAM88RC modular design approach, the following peripherals were integrated with the SAM88RC
CPU core:
-- Large number of programable I/O ports (Total 72 pins)
-- PLL frequency synthesizer
-- 16-bits intermediate frequency counter
-- Two synchronous SIO modules
-- Two 8-bit timer/counters
-- One 16-bit timer/counter
-- Low voltage reset
-- A/D converter with 4 selectable input pins
OTP
The S3C830A microcontroller is also available in OTP (One Time Programmable) version, S3P830A.
The S3P830A microcontroller has an on-chip 48K-byte one-time-programmable EPROM instead of masked
ROM. The S3P830A is comparable to S3C830A, both in function and in pin configuration.
PRODUCT OVERVIEW
S3C830A/P830A
1-2
FEATURES
CPU
SAM88RC CPU core
Memory
2064-byte internal register file (including LCD
display RAM)
48K-byte internal program memory area
Instruction Set
78 instructions
Idle and Stop instructions
72 I/O Pins
32 normal I/O pins
40 pins sharing with LCD segment signals
Interrupts
8 interrupt levels and 17 internal sources
Fast interrupt processing feature
8-Bit Basic Timer
Watchdog timer function
4 kinds of clock source
Timer/Counter 0
Programmable 8-bit internal timer
External event counter function
PWM and capture function
Timer/Counter 1
Programmable 8-bit interval timer
External event counter function
Timer/Counter 2
Programmable 16-bit interval timer
External event counter function
Watch Timer
Interval Time: 50ms, 0.5s, 1.0s at 4.5 MHz
1/1.5/3/6 kHz buzzer output selectable
Analog to Digital Converter
4-channel analog input
8-bit conversion resolution
Two 8-bit Serial I/O Interface
8-bit transmit/receive mode
8-bit receive mode
Selectable baud rate or external clock source
PLL Frequency Synthesizer
V
IN
level: 300mVpp (minimum)
AMVCO range: 0.5 MHz30 MHz
FMVCO range: 30 MHz150 MHz
16-Bit Intermediate Frequency (IF) Counter
V
IN
level: 300mVpp (minimum)
AMIF range: 100 kHz1 MHz
FMIF range: 5 MHz15 MHz
LCD Controller/Driver
40 segments and 4 common terminals
4/3/2 common and static selectable
Internal or external resistor circuit for LCD bias
Low Voltage Reset (LVR)
Low voltage check to make system reset
V
LVR
: 3.5 V (typical)
Two Power-Down Modes
Idle mode: only CPU clock stops
Stop mode: system clock and CPU clock stop
Oscillation Source
Crystal or ceramic for system clock (fx)
Instruction Execution Time
890 ns at 4.5 MHz (minimum)
Operating Temperature Range
25
C to +85
C
Operating Voltage Range
3.0 V to 5.5 V at 0.4 MHz4.5 MHz
4.5 V to 5.5 V in PLL/IFC block
Package Type
100-pin QFP package
S3C830A/P830A
PRODUCT OVERVIEW
1-3
BLOCK DIAGRAM
I/O Port and Interrupt Control
SAM88RC Core
48K-byte
ROM
2064-byte
Register File
Port 8
Low Voltage
Reset
P3.3/SI0
AMIF
AVDD
P8.0/SEG7
P8.1/SEG6
P8.2/SEG5
P8.3/SEG4
P8.4/SEG3
P8.5/SEG2
P8.6/SEG1
P8.7/SEG0
LVREN
8-Bit Timer/
Counter0
P0.2/T0CAP
P0.1/T0CLK
P0.3/T0OUT/T0PWM
8-Bit Timer/
Counter1
P0.4/T1CLK
P0.5/T1OUT
16-Bit Timer/
Counter2
P0.6/T2CLK
P0.7/T2OUT
SIO 1
P3.4/SCK1
P3.5/SO1
P3.6/SI1
Basic Timer
Watchdog
Timer
Watch Timer
P3.0/BUZ
LCD Driver/
Controller
COM0-3
P8.7-P4.0/SEG0-39
BIAS
V
LC0
-V
LC2
PLL
Synthesizer
VCOAM
VCOFM
EO0/EO1
IF Counter
FMIF
8-Bit ADC
P2.0-P2.3/AD0-AD3
X
IN
X
OUT
OSC
SIO 0
P3.1/SCK0
P3.2/SO0
Port 7
Port 6
Port 5
Port 4
P4.0/SEG39
P4.1/SEG38
P4.2/SEG37
P4.3/SEG36
P4.4/SEG35
P4.5/SEG34
P4.6/SEG33
P4.7/SEG32
Port 3
P3.0/BUZ
P3.1/SCK0
P3.2/SO0
P3.3/SI0
P3.4/SCK1
P3.5/SO1
P3.6/SI1
P3.7
Port 2
P2.0/AD0
P2.1/AD1
P2.2/AD2
P2.3/AD3
P2.4
P2.5
P2.6
P2.7
Port 1
P1.0/INT0
P1.1/INT1
P1.2/INT2
P1.3/INT3
P1.4/INT4
P1.5/INT5
P1.6/INT6
P1.7/INT7
Port 0
P0.0
P0.1/T0CLK
P0.2/T0CAP
P0.3/T0OUT/T0PWM
P0.4/T1CLK
P0.5/T1OUT
P0.6/T2CLK
P0.7/T2OUT
RESET
P1.0-P1.7/
INT0-INT7
CE
TEST1
TEST2
TEST3 VDD
VDDPLL0
VDDPLL1
VSS
VSSPLL
P5.0/SEG31
P5.1/SEG30
P5.2/SEG29
P5.3/SEG28
P5.4/SEG27
P5.5/SEG26
P5.6/SEG25
P5.7/SEG24
P6.0/SEG23
P6.1/SEG22
P6.2/SEG21
P6.3/SEG20
P6.4/SEG19
P6.5/SEG18
P6.6/SEG17
P6.7/SEG16
P7.0/SEG15
P7.1/SEG14
P7.2/SEG13
P7.3/SEG12
P7.4/SEG11
P7.5/SEG10
P7.6/SEG9
P7.7/SEG8
Figure 1-1. Block Diagram
PRODUCT OVERVIEW
S3C830A/P830A
1-4
PIN ASSIGNMENT
FMIF
VDDPLL0
EO0
EO1
CE
P0.0
P0.1/T0CLK
P0.2/T0CAP
P0.3/T0OUT/T0PWM
P0.4/T1CLK
P0.5/T1OUT
P0.6/T2CLK
P0.7/T2OUT
P1.0/INT0
P1.1/INT1
P1.2/INT2
P1.3/INT3
P1.4/INT4
P1.5/INT5
P1.6/INT6
P1.7/INT7
P2.0/AD0
P2.1/AD1
P2.2/AD2
P2.3/AD3
P2.4
P2.5
P2.6
P2.7
AV
DD
P3.0/BUZ
P3.1/SCK0
P3.2/SO0
P3.3/SI0
V
DD
V
SS
X
OUT
X
IN
TEST1
TEST2
P3.4/SCK1
RESET
P3.5/SO1
P3.6/SI1
P3.7
P4.0/SEG39
P4.1/SEG38
P4.2/SEG37
P4.3/SEG36
P4.4/SEG35
S3C830A
100-QFP-1420C
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
AMIF
VSSPLL
VCOAM
VCOFM
VDDPLL1
LVREN
TEST3
BIAS
VLC0
VLC1
VLC2
COM0
COM1
COM2
COM3
SEG0/P8.7
SEG1/P8.6
SEG2/P8.5
SEG3/P8.4
SEG4/P8.3
SEG5/P8.2
SEG6/P8.1
SEG7/P8.0
SEG8/P7.7
SEG9/P7.6
SEG10/P7.5
SEG11/P7.4
SEG12/P7.3
SEG13/P7.2
SEG14/P7.1
SEG15/P7.0
SEG16/P6.7
SEG17/P6.6
SEG18/P6.5
SEG19/P6.4
SEG20/P6.3
SEG21/P6.2
SEG22/P6.1
SEG23/P6.0
SEG24/P5.7
SEG25/P5.6
SEG26/P5.5
SEG27/P5.4
SEG28/P5.3
SEG29/P5.2
SEG30/P5.1
SEG31/P5.0
SEG32/P4.7
SEG33/P4.6
SEG34/P4.5
Figure 1-2. S3C830A Pin Assignments (100-QFP)
S3C830A/P830A
PRODUCT OVERVIEW
1-5
PIN DESCRIPTIONS
Table 1-1. S3C830A Pin Descriptions
Pin
Names
Pin
Type
Pin
Description
Circuit
Type
Pin No.
Share
Pins
P0.0
P0.1
P0.2
P0.3
P0.4
P0.5
P0.6
P0.7
I/O
I/O port with bit programmable pins; Schmitt
trigger input or push-pull, open-drain output
and software assignable pull-ups.
E-4
86
87
88
89
90
91
92
93
T0CLK
T0CAP
T0OUT/T0PWM
T1CLK
TOUT
T2CLK
T2OUT
P1.0-P1.7
I/O
I/O port with bit programmable pins; Schmitt
trigger Input or push-pull output and software
assignable pull-ups;
Alternately used for external interrupt input
(noise filters, interrupt enable and pending
control).
D-7
94-1
INT0-INT7
P2.0-P2.3
P2.4-P2.7
I/O
I/O port with bit programmable pins; Schmitt
trigger input or push-pull output and software
assignable pull-ups.
F-16
D-4
2-5
6-9
AD0-AD3
P3.0
P3.1
P3.2
P3.3
P3.4
P3.5
P3.6
P3.7
I/O
I/O port with bit programmable pins; Schmitt
trigger input or push-pull, open-drain output
and software assignable pull-ups.
E-4
11
12
13
14
21
23
24
25
BUZ
SCLK0
SO0
SI0
SCK1
SO1
SI1
P4.0-P4.7
I/O
I/O port with nibble programmable pins;
Schmitt trigger input or push-pull, open-drain
output and software assignable pull-ups.
H-41
26-33
SEG39-SEG32
P5.0-P5.7
I/O
I/O port with nibble programmable pins;
Schmitt trigger input or push-pull, open-drain
output and software assignable pull-ups.
H-41
34-41
SEG31-SEG24
P6.0-P6.7
I/O
I/O port with nibble programmable pins;
Schmitt trigger input or push-pull, open-drain
output and software assignable pull-ups.
H-41
42-49
SEG23-SEG16
P7.0-P7.7
I/O
I/O port with nibble programmable pins;
Schmitt trigger input or push-pull, open-drain
output and software assignable pull-ups.
H-41
50-57
SEG15-SEG8
P8.0-P8.7
I/O
I/O port with nibble programmable pins;
Schmitt trigger input or push-pull, open-drain
output and software assignable pull-ups.
H-41
58-65
SEG7-SEG0
PRODUCT OVERVIEW
S3C830A/P830A
1-6
Table 1-1. S3C830A Pin Descriptions (Continued)
Pin
Names
Pin
Type
Pin
Description
Circuit
Type
Pin No.
Share
Pins
COM0-COM3
O
Common signal output for LCD display
H
69-66
SEG0-SEG39
I/O
LCD segment signal output
H-41
65-26
P8-P4
BIAS
I
LCD power control
73
VLC0
VLC1
VLC2
I
LCD power supply
Voltage dividing resistors are assignable by
software
72-70
V
DD
Main power supply
15
V
SS
Main ground
16
VDDPLL0-1
PLL/IFC power supply
82, 76
VSSPLL
PLL/IFC ground
79
AV
DD
A/D converter power supply
10
X
OUT
, X
IN
Main oscillator pins for CPU oscillation
17, 18
TEST1,
TEST2
I
Test signal input pin
(Must be connected to V
SS
)
19, 20
TEST3
O
Test signal output pin
(Must be remained to open)
74
LVREN
I
LVR enable pin
(Must be connected to V
DD
or V
SS
)
A
75
RESET
I
System reset pin
B
22
CE
I
Input pin for checking device power
Normal operation is high level and PLL/IFC
Operation is stopped at low power
B-5
85
EO0
O
PLL's phase error output0
A-2
83
EO1
O
PLL's phase error output1
A-2
84
VCOAM
VCOFM
I
External VCOAM/VCOFM signal inputs
B-4
78, 77
S3C830A/P830A
PRODUCT OVERVIEW
1-7
Table 1-1. S3C830A Pin Descriptions (Continued)
Pin
Names
Pin
Type
Pin
Description
Circuit
Type
Pin No.
Share
Pins
FMIF, AMIF
I
FM/AM intermediate frequency signal inputs
B-4
81, 80
AD0-AD3
I/O
ADC input pins
F-16
2-5
P2.0-P2.3
BUZ
I/O
1, 1.5, 3 or 6 kHz frequency output for buzzer
sound at 4.5 MHz clock
E-4
11
P3.0
SCK0
I/O
SIO0 interface signal
E-4
12
P3.1
SO0
I/O
SIO0 interface data output signal
E-4
13
P3.2
SI0
I/O
SIO0 interface data input signal
E-4
14
P3.3
SCK1
I/O
SIO1 interface signal
E-4
21
P3.4
SO1
I/O
SIO1 interface data output signal
E-4
23
P3.5
SI1
I/O
SIO1 interface data input signal
E-4
24
P3.6
T0CLK
I/O
Timer 0 clock input
E-4
87
P0.1
T0CAP
I/O
Timer 0 capture input
E-4
88
P0.2
T0OUT
I/O
Timer 0 clock output
E-4
89
P0.3
T0PWM
I/O
Timer 0 PWM output
E-4
89
P0.3
T1CLK
I/O
Timer 1 clock input
E-4
90
P0.4
T1OUT
I/O
Timer 1 clock output
E-4
91
P0.5
T2CLK
I/O
Timer 2 clock input
E-4
92
P0.6
T2OUT
I/O
Timer 2 clock output
E-4
93
P0.7
INT0-INT7
I/O
External interrupt input pins
D-7
94-1
P1.0-P1.7
PRODUCT OVERVIEW
S3C830A/P830A
1-8
PIN CIRCUITS
P-Channel
N-Channel
In
V
DD
Figure 1-3. Pin Circuit Type A
P-Channel
N-Channel
Up
V
DD
Out
Down
Figure 1-4. Pin Circuit Type A-2 (EO)
In
V
DD
Pull-up
Resistor
Schmitt Trigger
Figure 1-5. Pin Circuit Type B (
RESET
RESET
)
In
Type A
Feedback
Enable
N-CH
Pull-down
Enable
Figure 1-6. Pin Circuit Type B-4
In
Figure 1-7. Pin Circuit Type B-5 (CE)
P-Channel
N-Channel
V
DD
Out
Output
Disable
Data
Figure 1-8. Pin Circuit Type C
S3C830A/P830A
PRODUCT OVERVIEW
1-9
V
DD
Output
Disable
Data
Pull-up
Resistor
V
DD
I/O
P-CH
N-CH
Schmitt Trigger
Open-Drain
Enable
Pull-up
Enable
V
SS
Figure 1-9. Pin Circuit Type E-4 (P0, P3)
I/O
Output
Disable
Data
V
DD
P-Channel
Pull-up
Enable
Circuit
Type C
Port
Enable
(PG2CON.4-5)
Schmitt Trigger
Figure 1-10. Pin Circuit Type D-7 (P1)
Pull-up
Enable
Data
Output
Disable
ADCEN
Data
ADC Select
V
DD
I/O
Circuit
Type C
To ADC
Figure 1-11. Pin Circuit Type F-16 (P2.0-P2.3)
Out
V
LC1
COM
V
LC2
V
LC0
Figure 1-12. Pin Circuit Type H (COM0-COM3)
PRODUCT OVERVIEW
S3C830A/P830A
1-10
Out
SEG
V
LC0
V
LC1
V
LC2
Output
Disable
Figure 1-13. Pin Circuit Type H-39
V
DD
Open
Drain
Data
SEG
Output
Disable2
Resistor
Enable
V
DD
Circuit
Type H-39
Output
Disable1
P-CH
N-CH
Pull-up
Resistor
I/O
Figure 1-14. Pin Circuit Type H-41 (P4-P8)
I/O
Output
Disable
Data
Circuit
Type C
Pull-up
Enable
V
DD
Figure 1-15. Pin Circuit Type D-4 (P2.4-P2.7)
S3C830A/P830A
ADDRESS SPACES
2-1
2
ADDRESS SPACES
OVERVIEW
The S3C830A microcontroller has two types of address space:
-- Internal program memory (ROM)
-- Internal register file
A 16-bit address bus supports program memory operations. A separate 8-bit register bus carries addresses and
data between the CPU and the register file.
The S3C830A has an internal 48-Kbyte mask-programmable ROM.
The 256-byte physical register space is expanded into an addressable area of 320 bytes using addressing modes.
A 20-byte LCD display register file is implemented.
There are 2,134 mapped registers in the internal register file. Of these, 2,064 are for general-purpose.
(This number includes a 16-byte working register common area used as a "scratch area" for data operations,
eight 192-byte prime register areas, and eight 64-byte areas (Set 2)). Thirteen 8-bit registers are used for the
CPU and the system control, and 57 registers are mapped for peripheral controls and data registers. Ten register
locations are not mapped.
ADDRESS SPACES
S3C830A/P830A
2-2
PROGRAM MEMORY (ROM)
Program memory (ROM) stores program codes or table data. The S3C830A has 48K bytes internal mask-
programmable program memory.
The first 256 bytes of the ROM (0H0FFH) are reserved for interrupt vector addresses. Unused locations in this
address range can be used as normal program memory. If you use the vector address area to store a program
code, be careful not to overwrite the vector addresses stored in these locations.
The ROM address at which a program execution starts after a reset is 0100H.
(Decimal)
49,151
(HEX)
BFFFH
48K-bytes
Internal
Program
Memory Area
FFH
255
Interrupt
Vector Area
0H
0
Figure 2-1. Program Memory Address Space
S3C830A/P830A
ADDRESS SPACES
2-3
REGISTER ARCHITECTURE
In the S3C830A implementation, the upper 64-byte area of register files is expanded two 64-byte areas, called
set 1 and set 2. The upper 32-byte area of set 1 is further expanded two 32-byte register banks (bank 0 and bank
1), and the lower 32-byte area is a single 32-byte common area.
In case of S3C830A the total number of addressable 8-bit registers is 2134. Of these 2134 registers, 13 bytes are
for CPU and system control registers, 57 bytes are for peripheral control and data registers, 16 bytes are used as
a shared working registers, and 2048 registers are for general-purpose use, page 0-page 7 (including 20 bytes for
LCD display registers).
You can always address set 1 register locations, regardless of which of the eight register pages is currently
selected. Set 1 locations, however, can only be addressed using register addressing modes.
The extension of register space into separately addressable areas (sets, banks, and pages) is supported by
various addressing mode restrictions, the select bank instructions, SB0 and SB1, and the register page pointer
(PP).
Specific register types and the area (in bytes) that they occupy in the register file are summarized in Table 21.
Table 2-1. S3C830A Register Type Summary
Register Type
Number of Bytes
General-purpose registers (including the 16-byte
common working register area, eight 192-byte prime
register area (including LCD data registers), and eight
64-byte set 2 area).
CPU and system control registers
Mapped clock, peripheral, I/O control, and data registers
2,064
13
57
Total Addressable Bytes
2,134
ADDRESS SPACES
S3C830A/P830A
2-4
System Registers
(Register Addressing Mode)
Working Registers
(Working Register
Addressing Only)
Bank 1
System and
Peripheral Control
Registers
Bank 0
System and
Peripheral Control
Registers
(Register Addressing Mode)
Set 1
FFH
32
Bytes
E0H
DFH
D0H
CFH
C0H
Prime
Data Registers
(All Addressing Modes)
LCD Display Register
~
~
Page 7
13H
00H
20
Bytes
~
Page 1
~
Page 7
~
~
Page 1
Page 0
Prime
Data Registers
(All Addressing Modes)
Page 0
Set 2
Registers
(Indirect Register,
Indexed Mode,
and Stack Operations)
~
~
~
C0H
BFH
00H
FFH
FFH
FFH
FFH
192
Bytes
64
Bytes
256
Bytes
FFH
Figure 2-2. Internal Register File Organization
S3C830A/P830A
ADDRESS SPACES
2-5
REGISTER PAGE POINTER (PP)
The S3C8-series architecture supports the logical expansion of the physical 256-byte internal register file (using
an 8-bit data bus) into as many as 16 separately addressable register pages. Page addressing is controlled by the
register page pointer (PP, DFH). In the S3C830A microcontroller, a paged register file expansion is implemented
for LCD data registers, and the register page pointer must be changed to address other pages.
After a reset, the page pointer's source value (lower nibble) and the destination value (upper nibble) are always
"0000", automatically selecting page 0 as the source and destination page for register addressing.
Register Page Pointer (PP)
DFH ,Set 1, R/W
LSB
MSB
.7
.6
.5
.4
.3
.2
.1
.0
Destination register page selection bits:
0000
Destination: Page 0
Source register page selection bits:
0000
Source: Page 0
NOTE:
A hardware reset operation writes the 4-bit destination and
source values shown above to the register page pointer. These values should
be modified to address other pages.
Figure 2-3. Register Page Pointer (PP)
+
+
PROGRAMMING TIP -- Using the Page Pointer for RAM clear (Page 0, Page 1)
LD
PP,#00H
; Destination
0, Source
0
SRP
#0C0H
LD
R0,#0FFH
; Page 0 RAM clear starts
RAMCL0
CLR
@R0
DJNZ
R0,RAMCL0
CLR
@R0
; R0 = 00H
LD
PP,#10H
; Destination
1, Source
0
LD
R0,#0FFH
; Page 1 RAM clear starts
RAMCL1
CLR
@R0
DJNZ
R0,RAMCL1
CLR
@R0
; R0 = 00H
NOTE: You should refer to page 6-39 and use DJNZ instruction properly when DJNZ instruction is used in your program.
ADDRESS SPACES
S3C830A/P830A
2-6
REGISTER SET 1
The term set 1 refers to the upper 64 bytes of the register file, locations C0HFFH.
The upper 32-byte area of this 64-byte space (E0HFFH) is expanded two 32-byte register banks, bank 0 and
bank 1. The set register bank instructions, SB0 or SB1, are used to address one bank or the other. A hardware
reset operation always selects bank 0 addressing.
The upper two 32-byte areas (bank 0 and bank 1) of set 1 (E0HFFH) contains 57 mapped system and
peripheral control registers. The lower 32-byte area contains 16 system registers (D0HDFH) and a 16-byte
common working register area (C0HCFH). You can use the common working register area as a "scratch" area
for data operations being performed in other areas of the register file.
Registers in set 1 locations are directly accessible at all times using Register addressing mode. The 16-byte
working register area can only be accessed using working register addressing (For more information about
working register addressing, please refer to Chapter 3, "Addressing Modes.")
REGISTER SET 2
The same 64-byte physical space that is used for set 1 locations C0HFFH is logically duplicated to add another
64 bytes of register space. This expanded area of the register file is called set 2. For the S3C830A,
the set 2 address range (C0HFFH) is accessible on pages 0-7.
The logical division of set 1 and set 2 is maintained by means of addressing mode restrictions. You can use only
Register addressing mode to access set 1 locations. In order to access registers in set 2, you must use Register
Indirect addressing mode or Indexed addressing mode.
The set 2 register area of page 0 is commonly used for stack operations.
S3C830A/P830A
ADDRESS SPACES
2-7
PRIME REGISTER SPACE
The lower 192 bytes (00HBFH) of the S3C830A's eight 256-byte register pages is called prime register area.
Prime registers can be accessed using any of the seven addressing modes
(see Chapter 3, "Addressing Modes.")
The prime register area on page 0 is immediately addressable following a reset. In order to address prime
registers on pages 0, 1, 2, 3, 4, 5, 6, or 7 you must set the register page pointer (PP) to the appropriate source
and destination values.
FFH
Page 7
FFH
Page 6
FFH
Page 5
FFH
C0H
00H
BFH
Page 4
Page 0
Prime
Space
FFH
FCH
E0H
D0H
C0H
Set 1
Bank 0
Peripheral and I/O
General-purpose
CPU and system control
LCD data register
Bank 1
FFH
Page 3
Set 2
FFH
Page 2
Set 2
FFH
Page 1
Set 2
FFH
C0H
00H
BFH
Page 0
Set 2
Page 0
Prime
Space
LCD Data
Register Area
Page 7
00H
13H
Figure 2-4. Set 1, Set 2, Prime Area Register, and LCD Data Register Map
ADDRESS SPACES
S3C830A/P830A
2-8
WORKING REGISTERS
Instructions can access specific 8-bit registers or 16-bit register pairs using either 4-bit or 8-bit address fields.
When 4-bit working register addressing is used, the 256-byte register file can be seen by the programmer as one
that consists of 32 8-byte register groups or "slices." Each slice comprises of eight 8-bit registers.
Using the two 8-bit register pointers, RP1 and RP0, two working register slices can be selected at any one time to
form a 16-byte working register block. Using the register pointers, you can move this 16-byte register block
anywhere in the addressable register file, except the set 2 area.
The terms slice and block are used in this manual to help you visualize the size and relative locations of selected
working register spaces:
-- One working register slice is 8 bytes (eight 8-bit working registers, R0R7 or R8R15)
-- One working register block is 16 bytes (sixteen 8-bit working registers, R0R15)
All the registers in an 8-byte working register slice have the same binary value for their five most significant
address bits. This makes it possible for each register pointer to point to one of the 24 slices in the register file.
The base addresses for the two selected 8-byte register slices are contained in register pointers RP0 and RP1.
After a reset, RP0 and RP1 always point to the 16-byte common area in set 1 (C0HCFH).
Each register pointer points to
one 8-byte slice of the register
space, selecting a total 16-byte
working register block.
1 1 1 1 1 X X X
RP1 (Registers R8-R15)
RP0 (Registers R0-R7)
Slice 32
Slice 31
~
~
CFH
C0H
FFH
F8H
F7H
F0H
FH
8H
7H
0H
Slice 2
Slice 1
10H
Set 1
Only
0 0 0 0 0 X X X
Figure 2-5. 8-Byte Working Register Areas (Slices)
S3C830A/P830A
ADDRESS SPACES
2-9
USING THE REGISTER POINTS
Register pointers RP0 and RP1, mapped to addresses D6H and D7H in set 1, are used to select two movable
8-byte working register slices in the register file. After a reset, they point to the working register common area:
RP0 points to addresses C0HC7H, and RP1 points to addresses C8HCFH.
To change a register pointer value, you load a new value to RP0 and/or RP1 using an SRP or LD instruction.
(see Figures 2-6 and 2-7).
With working register addressing, you can only access those two 8-bit slices of the register file that are currently
pointed to by RP0 and RP1. You cannot, however, use the register pointers to select a working register space in
set 2, C0HFFH, because these locations can be accessed only using the Indirect Register or Indexed
addressing modes.
The selected 16-byte working register block usually consists of two contiguous 8-byte slices. As a general
programming guideline, it is recommended that RP0 point to the "lower" slice and RP1 point to the "upper" slice
(see Figure 2-6). In some cases, it may be necessary to define working register areas in different (non-
contiguous) areas of the register file. In Figure 2-7, RP0 points to the "upper" slice and RP1 to the "lower" slice.
Because a register pointer can point to either of the two 8-byte slices in the working register block, you can
flexibly define the working register area to support program requirements.
+
+
PROGRAMMING TIP -- Setting the Register Pointers
SRP
#70H
; RP0
70H, RP1
78H
SRP1
#48H
; RP0
no change, RP1
48H,
SRP0
#0A0H
; RP0
A0H, RP1
no change
CLR
RP0
; RP0
00H, RP1
no change
LD
RP1,#0F8H
; RP0
no change, RP1
0F8H
FH (R15)
0H (R0)
16-Byte
Contiguous
Working
Register block
Register File
Contains 32
8-Byte Slices
RP0
RP1
8H
7H
0 0 0 0 1 X X X
0 0 0 0 0 X X X
8-Byte Slice
8-Byte Slice
Figure 2-6. Contiguous 16-Byte Working Register Block
ADDRESS SPACES
S3C830A/P830A
2-10
16-Byte
Contiguous
working
Register block
Register File
Contains 32
8-Byte Slices
0 0 0 0 0 X X X
RP1
1 1 1 1 0 X X X
RP0
0H (R0)
7H (R15)
F0H (R0)
F7H (R7)
8-Byte Slice
8-Byte Slice
Figure 2-7. Non-Contiguous 16-Byte Working Register Block
+
+
PROGRAMMING TIP -- Using the RPs to Calculate the Sum of a Series of Registers
Calculate the sum of registers 80H85H using the register pointer. The register addresses from 80H through 85H
contain the values 10H, 11H, 12H, 13H, 14H, and 15 H, respectively:
SRP0
#80H
; RP0
80H
ADD
R0,R1
; R0
R0 + R1
ADC
R0,R2
; R0
R0 + R2 + C
ADC
R0,R3
; R0
R0 + R3 + C
ADC
R0,R4
; R0
R0 + R4 + C
ADC
R0,R5
; R0
R0 + R5 + C
The sum of these six registers, 6FH, is located in the register R0 (80H). The instruction string used in this
example takes 12 bytes of instruction code and its execution time is 36 cycles. If the register pointer is not used
to calculate the sum of these registers, the following instruction sequence would have to be used:
ADD
80H,81H
; 80H
(80H) + (81H)
ADC
80H,82H
; 80H
(80H) + (82H) + C
ADC
80H,83H
; 80H
(80H) + (83H) + C
ADC
80H,84H
; 80H
(80H) + (84H) + C
ADC
80H,85H
; 80H
(80H) + (85H) + C
Now, the sum of the six registers is also located in register 80H. However, this instruction string takes 15 bytes of
instruction code rather than 12 bytes, and its execution time is 50 cycles rather than 36 cycles.
S3C830A/P830A
ADDRESS SPACES
2-11
REGISTER ADDRESSING
The S3C8-series register architecture provides an efficient method of working register addressing that takes full
advantage of shorter instruction formats to reduce execution time.
With Register (R) addressing mode, in which the operand value is the content of a specific register or register
pair, you can access any location in the register file except for set 2. With working register addressing, you use a
register pointer to specify an 8-byte working register space in the register file and an 8-bit register within that
space.
Registers are addressed either as a single 8-bit register or as a paired 16-bit register space. In a 16-bit register
pair, the address of the first 8-bit register is always an even number and the address of the next register is always
an odd number. The most significant byte of the 16-bit data is always stored in the even-numbered register, and
the least significant byte is always stored in the next (+1) odd-numbered register.
Working register addressing differs from Register addressing as it uses a register pointer to identify a specific
8-byte working register space in the internal register file and a specific 8-bit register within that space.
MSB
Rn
LSB
Rn+1
n = Even address
Figure 2-8. 16-Bit Register Pair
ADDRESS SPACES
S3C830A/P830A
2-12
RP1
RP0
Register
Pointers
00H
All
Addressing
Modes
Page 0
Indirect Register,
Indexed
Addressing
Modes
Page 0
Register Addressing Only
Can be Pointed by Register Pointer
FFH
E0H
BFH
Control
Registers
System
Registers
Special-Purpose Registers
D0H
C0H
Bank 1
Bank 0
NOTE:
In the S3C830A microcontroller,
pages 0-7 are implemented.
Pages 0-7 contain all of the addressable
registers in the internal register file.
Each register pointer (RP) can independently point
to one of the 24 8-byte "slices" of the register file
(other than set 2). After a reset, RP0 points to
locations C0H-C7H and RP1 to locations C8H-CFH
(that is, to the common working register area).
FFH
C0H
Set 2
Prime
Registers
CFH
General-Purpose Register
All
Addressing
Modes
Can be Pointed
by register Pointer
LCD Data
Registers
Figure 2-9. Register File Addressing
S3C830A/P830A
ADDRESS SPACES
2-13
COMMON WORKING REGISTER AREA (C0HCFH)
After a reset, register pointers RP0 and RP1 automatically select two 8-byte register slices in set 1, locations
C0HCFH, as the active 16-byte working register block:
RP0
C0HC7H
RP1
C8HCFH
This 16-byte address range is called common area. That is, locations in this area can be used as working
registers by operations that address any location on any page in the register file. Typically, these working
registers serve as temporary buffers for data operations between different pages.
FFH
Page 7
FFH
Page 6
FFH
Page 5
FFH
C0H
BFH
Page 4
Page 0
Prime
Space
FFH
FCH
E0H
D0H
C0H
Set 1
Following a hardware reset, register
pointers RP0 and RP1 point to the
common working register area,
locations C0H-CFH.
RP0 =
RP1 =
1 1 0 0
0 0 0 0
1 1 0 0
1 0 0 0
LCD Data
Registers
Page 7
00H
13H
FFH
Page 3
Set 2
FFH
Page 2
Set 2
FFH
Page 1
Set 2
FFH
C0H
00H
BFH
Page 0
Set 2
Page 0
Prime
Space
~
~
~
~
~
~
~
~
~
Figure 2-10. Common Working Register Area
ADDRESS SPACES
S3C830A/P830A
2-14
+
+
PROGRAMMING TIP -- Addressing the Common Working Register Area
As the following examples show, you should access working registers in the common area, locations C0HCFH,
using working register addressing mode only.
Examples
1. LD
0C2H,40H
; Invalid addressing mode!
Use working register addressing instead:
SRP
#0C0H
LD
R2,40H
; R2 (C2H)
the value in location 40H
2. ADD
0C3H,#45H
; Invalid addressing mode!
Use working register addressing instead:
SRP
#0C0H
ADD
R3,#45H
; R3 (C3H)
R3 + 45H
4-BIT WORKING REGISTER ADDRESSING
Each register pointer defines a movable 8-byte slice of working register space. The address information stored in
a register pointer serves as an addressing "window" that makes it possible for instructions to access working
registers very efficiently using short 4-bit addresses. When an instruction addresses a location in the selected
working register area, the address bits are concatenated in the following way to form a complete 8-bit address:
-- The high-order bit of the 4-bit address selects one of the register pointers ("0" selects RP0, "1" selects RP1).
-- The five high-order bits in the register pointer select an 8-byte slice of the register space.
-- The three low-order bits of the 4-bit address select one of the eight registers in the slice.
As shown in Figure 2-11, the result of this operation is that the five high-order bits from the register pointer are
concatenated with the three low-order bits from the instruction address to form the complete address. As long as
the address stored in the register pointer remains unchanged, the three bits from the address will always point to
an address in the same 8-byte register slice.
Figure 2-12 shows a typical example of 4-bit working register addressing. The high-order bit of the instruction
"INC R6" is "0", which selects RP0. The five high-order bits stored in RP0 (01110B) are concatenated with the
three low-order bits of the instruction's 4-bit address (110B) to produce the register address 76H (01110110B).
S3C830A/P830A
ADDRESS SPACES
2-15
Together they create an
8-bit register address
Register pointer
provides five
high-order bits
Address
OPCODE
Selects
RP0 or RP1
RP1
RP0
4-bit address
provides three
low-order bits
Figure 2-11. 4-Bit Working Register Addressing
Register
address
(76H)
RP0
0 1 1 1 0
0 0 0
0 1 1 1 0
1 1 0
R6
0 1 1 0
1 1 1 0
Selects RP0
Instruction
'INC R6'
OPCODE
RP1
0 1 1 1 1
0 0 0
Figure 2-12. 4-Bit Working Register Addressing Example
ADDRESS SPACES
S3C830A/P830A
2-16
8-BIT WORKING REGISTER ADDRESSING
You can also use 8-bit working register addressing to access registers in a selected working register area. To
initiate 8-bit working register addressing, the upper four bits of the instruction address must contain the value
"1100B." This 4-bit value (1100B) indicates that the remaining four bits have the same effect as 4-bit working
register addressing.
As shown in Figure 2-13, the lower nibble of the 8-bit address is concatenated in much the same way as for 4-bit
addressing: Bit 3 selects either RP0 or RP1, which then supplies the five high-order bits of the final address; the
three low-order bits of the complete address are provided by the original instruction.
Figure 2-14 shows an example of 8-bit working register addressing. The four high-order bits of the instruction
address (1100B) specify 8-bit working register addressing. Bit 4 ("1") selects RP1 and the five high-order bits in
RP1 (10101B) become the five high-order bits of the register address. The three low-order bits of the register
address (011) are provided by the three low-order bits of the 8-bit instruction address. The five address bits from
RP1 and the three address bits from the instruction are concatenated to form the complete register address,
0ABH (10101011B).
8-bit logical
address
8-bit physical address
Register pointer
provides five
high-order bits
Address
Selects
RP0 or RP1
RP1
RP0
Three low-order bits
These address
bits indicate 8-bit
working register
addressing
1
1
0
0
Figure 2-13. 8-Bit Working Register Addressing
S3C830A/P830A
ADDRESS SPACES
2-17
8-bit address
form instruction
'LD R11, R2'
RP0
0 1 1 0 0
0 0 0
1 1 0 0 1 0 1 1
Selects RP1
R11
Register
address
(0ABH)
RP1
1 0 1 0 1
0 0 0
1 0 1 0 1
0 1 1
Specifies working
register addressing
Figure 2-14. 8-Bit Working Register Addressing Example
ADDRESS SPACES
S3C830A/P830A
2-18
SYSTEM AND USER STACK
The S3C8-series microcontrollers use the system stack for data storage, subroutine calls and returns. The PUSH
and POP instructions are used to control system stack operations. The S3C830A architecture supports stack
operations in the internal register file.
Stack Operations
Return addresses for procedure calls, interrupts, and data are stored on the stack. The contents of the PC are
saved to stack by a CALL instruction and restored by the RET instruction. When an interrupt occurs, the contents
of the PC and the FLAGS register are pushed to the stack. The IRET instruction then pops these values back to
their original locations. The stack address value is always decreased by one before a push operation and
increased by one after a pop operation. The stack pointer (SP) always points to the stack frame stored on the top
of the stack, as shown in Figure 2-15.
Stack contents
after a call
instruction
Stack contents
after an
interrupt
Top of
stack
Flags
PCH
PCL
PCL
PCH
Top of
stack
Low Address
High Address
Figure 2-15. Stack Operations
User-Defined Stacks
You can freely define stacks in the internal register file as data storage locations. The instructions PUSHUI,
PUSHUD, POPUI, and POPUD support user-defined stack operations.
Stack Pointers (SPL, SPH)
Register locations D8H and D9H contain the 16-bit stack pointer (SP) that is used for system stack operations.
The most significant byte of the SP address, SP15SP8, is stored in the SPH register (D8H), and the least
significant byte, SP7SP0, is stored in the SPL register (D9H). After a reset, the SP value is undetermined.
Because only internal memory space is implemented in the S3C830A, the SPL must be initialized to an 8-bit
value in the range 00HFFH. The SPH register is not needed and can be used as a general-purpose register, if
necessary.
When the SPL register contains the only stack pointer value (that is, when it points to a system stack in the
register file), you can use the SPH register as a general-purpose data register. However, if an overflow or
underflow condition occurs as a result of increasing or decreasing the stack address value in the SPL register
during normal stack operations, the value in the SPL register will overflow (or underflow) to the SPH register,
overwriting any other data that is currently stored there. To avoid overwriting data in the SPH register, you can
initialize the SPL value to "FFH" instead of "00H".
S3C830A/P830A
ADDRESS SPACES
2-19
+
+
PROGRAMMING TIP -- Standard Stack Operations Using PUSH and POP
The following example shows you how to perform stack operations in the internal register file using PUSH and
POP instructions:
LD
SPL,#0FFH
; SPL
FFH
; (Normally, the SPL is set to 0FFH by the initialization
; routine)
PUSH
PP
; Stack address 0FEH
PP
PUSH
RP0
; Stack address 0FDH
RP0
PUSH
RP1
; Stack address 0FCH
RP1
PUSH
R3
; Stack address 0FBH
R3
POP
R3
; R3
Stack address 0FBH
POP
RP1
; RP1
Stack address 0FCH
POP
RP0
; RP0
Stack address 0FDH
POP
PP
; PP
Stack address 0FEH
ADDRESS SPACES
S3C830A/P830A
2-20
NOTES
S3C830A/P830A
ADDRESSING MODES
3-1
3
ADDRESSING MODES
OVERVIEW
Instructions that are stored in program memory are fetched for execution using the program counter. Instructions
indicate the operation to be performed and the data to be operated on. Addressing mode is the method used to
determine the location of the data operand. The operands specified in SAM88RC instructions may be condition
codes, immediate data, or a location in the register file, program memory, or data memory.
The S3C8-series instruction set supports seven explicit addressing modes. Not all of these addressing modes are
available for each instruction. The seven addressing modes and their symbols are:
-- Register (R)
-- Indirect Register (IR)
-- Indexed (X)
-- Direct Address (DA)
-- Indirect Address (IA)
-- Relative Address (RA)
-- Immediate (IM)
ADDRESSING MODES
S3C830A/P830A
3-2
REGISTER ADDRESSING MODE (R)
In Register addressing mode (R), the operand value is the content of a specified register or register pair
(see Figure 3-1).
Working register addressing differs from Register addressing in that it uses a register pointer to specify an 8-byte
working register space in the register file and an 8-bit register within that space (see Figure 3-2).
dst
Value used in
Instruction Execution
OPCODE
OPERAND
8-bit Register
File Address
Point to One
Register in Register
File
One-Operand
Instruction
(Example)
Sample Instruction:
DEC
CNTR
; Where CNTR is the label of an 8-bit register address
Program Memory
Register File
Figure 3-1. Register Addressing
dst
OPCODE
4-bit
Working Register
Point to the
Working Register
(1 of 8)
Two-Operand
Instruction
(Example)
Sample Instruction:
ADD
R1, R2
; Where R1 and R2 are registers in the curruntly
selected working register area.
Program Memory
Register File
src
3 LSBs
RP0 or RP1
Selected
RP points
to start
of working
register
block
OPERAND
MSB Point to
RP0 or RP1
Figure 3-2. Working Register Addressing
S3C830A/P830A
ADDRESSING MODES
3-3
INDIRECT REGISTER ADDRESSING MODE (IR)
In Indirect Register (IR) addressing mode, the content of the specified register or register pair is the address of
the operand. Depending on the instruction used, the actual address may point to a register in the register file, to
program memory (ROM), or to an external memory space (see Figures 3-3 through 3-6).
You can use any 8-bit register to indirectly address another register. Any 16-bit register pair can be used to
indirectly address another memory location. Please note, however, that you cannot access locations C0HFFH in
set 1 using the Indirect Register addressing mode.
dst
Address of Operand
used by Instruction
OPCODE
ADDRESS
8-bit Register
File Address
Point to One
Register in Register
File
One-Operand
Instruction
(Example)
Sample Instruction:
RL
@SHIFT
; Where SHIFT is the label of an 8-bit register address
Program Memory
Register File
Value used in
Instruction Execution
OPERAND
Figure 3-3. Indirect Register Addressing to Register File
ADDRESSING MODES
S3C830A/P830A
3-4
INDIRECT REGISTER ADDRESSING MODE (Continued)
dst
OPCODE
PAIR
Points to
Register Pair
Example
Instruction
References
Program
Memory
Sample Instructions:
CALL
@RR2
JP
@RR2
Program Memory
Register File
Value used in
Instruction
OPERAND
REGISTER
Program Memory
16-Bit
Address
Points to
Program
Memory
Figure 3-4. Indirect Register Addressing to Program Memory
S3C830A/P830A
ADDRESSING MODES
3-5
INDIRECT REGISTER ADDRESSING MODE (Continued)
dst
OPCODE
ADDRESS
4-bit
Working
Register
Address
Point to the
Working Register
(1 of 8)
Sample Instruction:
OR
R3, @R6
Program Memory
Register File
src
3 LSBs
Value used in
Instruction
OPERAND
Selected
RP points
to start fo
working register
block
RP0 or RP1
MSB Points to
RP0 or RP1
~
~
~
~
Figure 3-5. Indirect Working Register Addressing to Register File
ADDRESSING MODES
S3C830A/P830A
3-6
INDIRECT REGISTER ADDRESSING MODE (Concluded)
dst
OPCODE
4-bit Working
Register Address
Sample Instructions:
LDC
R5,@RR6
; Program memory access
LDE
R3,@RR14
; External data memory access
LDE
@RR4, R8
; External data memory access
Program Memory
Register File
src
Value used in
Instruction
OPERAND
Example Instruction
References either
Program Memory or
Data Memory
Program Memory
or
Data Memory
Next 2-bit Point
to Working
Register Pair
(1 of 4)
LSB Selects
Register
Pair
16-Bit
address
points to
program
memory
or data
memory
RP0 or RP1
MSB Points to
RP0 or RP1
Selected
RP points
to start of
working
register
block
Figure 3-6. Indirect Working Register Addressing to Program or Data Memory
S3C830A/P830A
ADDRESSING MODES
3-7
INDEXED ADDRESSING MODE (X)
Indexed (X) addressing mode adds an offset value to a base address during instruction execution in order to
calculate the effective operand address (see Figure 3-7). You can use Indexed addressing mode to access
locations in the internal register file or in external memory. Please note, however, that you cannot access
locations C0HFFH in set 1 using Indexed addressing mode.
In short offset Indexed addressing mode, the 8-bit displacement is treated as a signed integer in the range 128
to +127. This applies to external memory accesses only (see Figure 3-8.)
For register file addressing, an 8-bit base address provided by the instruction is added to an 8-bit offset contained
in a working register. For external memory accesses, the base address is stored in the working register pair
designated in the instruction. The 8-bit or 16-bit offset given in the instruction is then added to that base address
(see Figure 3-9).
The only instruction that supports Indexed addressing mode for the internal register file is the Load instruction
(LD). The LDC and LDE instructions support Indexed addressing mode for internal program memory and for
external data memory, when implemented.
dst/src
OPCODE
Two-Operand
Instruction
Example
Point to One of the
Woking Register
(1 of 8)
Sample Instruction:
LD R0, #BASE[R1]
; Where BASE is an 8-bit immediate value
Program Memory
Register File
x
3 LSBs
Value used in
Instruction
OPERAND
INDEX
Base Address
RP0 or RP1
Selected RP
points to
start of
working
register
block
~
~
~
~
+
Figure 3-7. Indexed Addressing to Register File
ADDRESSING MODES
S3C830A/P830A
3-8
INDEXED ADDRESSING MODE (Continued)
Register File
OPERAND
Program Memory
or
Data Memory
Point to Working
Register Pair
(1 of 4)
LSB Selects
16-Bit
address
added to
offset
RP0 or RP1
MSB Points to
RP0 or RP1
Selected
RP points
to start of
working
register
block
dst/src
OPCODE
Program Memory
x
OFFSET
4-bit Working
Register Address
Sample Instructions:
LDC
R4, #04H[RR2]
; The values in the program address (RR2 + 04H)
are loaded into register R4.
LDE
R4,#04H[RR2]
; Identical operation to LDC example, except that
external program memory is accessed.
NEXT 2 Bits
Register
Pair
Value used in
Instruction
8-Bits
16-Bits
16-Bits
+
~
~
Figure 3-8. Indexed Addressing to Program or Data Memory with Short Offset
S3C830A/P830A
ADDRESSING MODES
3-9
INDEXED ADDRESSING MODE (Concluded)
Register File
OPERAND
Program Memory
or
Data Memory
Point to Working
Register Pair
LSB Selects
16-Bit
address
added to
offset
RP0 or RP1
MSB Points to
RP0 or RP1
Selected
RP points
to start of
working
register
block
Sample Instructions:
LDC
R4, #1000H[RR2]
; The values in the program address (RR2 + 1000H)
are loaded into register R4.
LDE
R4,#1000H[RR2]
; Identical operation to LDC example, except that
external program memory is accessed.
NEXT 2 Bits
Register
Pair
Value used in
Instruction
8-Bits
16-Bits
16-Bits
dst/src
OPCODE
Program Memory
src
OFFSET
4-bit Working
Register Address
OFFSET
+
~
~
Figure 3-9. Indexed Addressing to Program or Data Memory
ADDRESSING MODES
S3C830A/P830A
3-10
DIRECT ADDRESS MODE (DA)
In Direct Address (DA) mode, the instruction provides the operand's 16-bit memory address. Jump (JP) and Call
(CALL) instructions use this addressing mode to specify the 16-bit destination address that is loaded into the PC
whenever a JP or CALL instruction is executed.
The LDC and LDE instructions can use Direct Address mode to specify the source or destination address for
Load operations to program memory (LDC) or to external data memory (LDE), if implemented.
Sample Instructions:
LDC
R5,1234H
; The values in the program address (1234H)
are loaded into register R5.
LDE
R5,1234H
; Identical operation to LDC example, except that
external program memory is accessed.
dst/src
OPCODE
Program Memory
"0" or "1"
Lower Address Byte
LSB Selects Program
Memory or Data Memory:
"0" = Program Memory
"1" = Data Memory
Memory
Address
Used
Upper Address Byte
Program or
Data Memory
Figure 3-10. Direct Addressing for Load Instructions
S3C830A/P830A
ADDRESSING MODES
3-11
DIRECT ADDRESS MODE (Continued)
OPCODE
Program Memory
Lower Address Byte
Memory
Address
Used
Upper Address Byte
Sample Instructions:
JP
C,JOB1
; Where JOB1 is a 16-bit immediate address
CALL
DISPLAY
; Where DISPLAY is a 16-bit immediate address
Next OPCODE
Figure 3-11. Direct Addressing for Call and Jump Instructions
ADDRESSING MODES
S3C830A/P830A
3-12
INDIRECT ADDRESS MODE (IA)
In Indirect Address (IA) mode, the instruction specifies an address located in the lowest 256 bytes of the program
memory. The selected pair of memory locations contains the actual address of the next instruction to be
executed. Only the CALL instruction can use the Indirect Address mode.
Because the Indirect Address mode assumes that the operand is located in the lowest 256 bytes of program
memory, only an 8-bit address is supplied in the instruction; the upper bytes of the destination address are
assumed to be all zeros.
Current
Instruction
Program Memory
Locations 0-255
Program Memory
OPCODE
dst
Lower Address Byte
Upper Address Byte
Next Instruction
LSB Must be Zero
Sample Instruction:
CALL
#40H
; The 16-bit value in program memory addresses 40H
and 41H is the subroutine start address.
Figure 3-12. Indirect Addressing
S3C830A/P830A
ADDRESSING MODES
3-13
RELATIVE ADDRESS MODE (RA)
In Relative Address (RA) mode, a twos-complement signed displacement between 128 and + 127 is specified
in the instruction. The displacement value is then added to the current PC value. The result is the address of the
next instruction to be executed. Before this addition occurs, the PC contains the address of the instruction
immediately following the current instruction.
Several program control instructions use the Relative Address mode to perform conditional jumps. The
instructions that support RA addressing are BTJRF, BTJRT, DJNZ, CPIJE, CPIJNE, and JR.
OPCODE
Program Memory
Displacement
Program Memory
Address Used
Sample Instructions:
JR
ULT,$+OFFSET ; Where OFFSET is a value in the range +127 to -128
Next OPCODE
+
Signed
Displacement Value
Current Instruction
Current
PC Value
Figure 3-13. Relative Addressing
ADDRESSING MODES
S3C830A/P830A
3-14
IMMEDIATE MODE (IM)
In Immediate (IM) addressing mode, the operand value used in the instruction is the value supplied in the
operand field itself. The operand may be one byte or one word in length, depending on the instruction used.
Immediate addressing mode is useful for loading constant values into registers.
(The Operand value is in the instruction)
OPCODE
Sample Instruction:
LD R0,#0AAH
Program Memory
OPERAND
Figure 3-14. Immediate Addressing
S3C830A/P830A
ELECTRICAL DATA
20-1
20
ELECTRICAL DATA
OVERVIEW
In this chapter, S3C830A electrical characteristics are presented in tables and graphs.
The information is arranged in the following order:
-- Absolute maximum ratings
-- D.C. electrical characteristics
-- A.C. electrical characteristics
-- Input/output capacitance
-- Data retention supply voltage in stop mode
-- A/D converter electrical characteristics
-- PLL electrical characteristics
-- Low voltage reset electrical characteristics
-- Serial I/O timing characteristics
-- Oscillation characteristics
-- Oscillation stabilization time
ELECTRICAL DATA
S3C830A/P830A
20-2
Table 20-1. Absolute Maximum Ratings
(T
A
= 25
C)
Parameter
Symbol
Conditions
Rating
Unit
Supply voltage
V
DD
0.3 to +6.5
V
Input voltage
V
I
Ports 08
0.3 to V
DD
+ 0.3
Output voltage
V
O
0.3 to V
DD
+ 0.3
Output current high
I
OH
One I/O pin active
15
mA
All I/O pins active
60
Output current low
I
OL
One I/O pin active
+ 30
Total pin current for port
+ 100
Operating temperature
T
A
25 to + 85
C
Storage temperature
T
STG
65 to + 150
Table 20-2. D.C. Electrical Characteristics
(T
A
= 25
C to + 85
C, V
DD
= 3.0 V to 5.5 V)
Parameter
Symbol
Conditions
Min.
Typ.
Max.
Unit
Operating voltage
V
DD
fx = 0.44.5 MHz
(except PLL/IFC)
3.0
5.5
V
fx = 4.5 MHz (PLL/IFC)
4.5
5.5
Input high voltage
V
IH1
Ports 08
0.8 V
DD
V
DD
V
IH2
RESET
, CE
0.8 V
DD
V
DD
V
IH3
X
IN
, X
OUT
V
DD
0.1
V
DD
Input low voltage
V
IL1
Ports 08
0.2 V
DD
V
IL2
RESET
, CE
0.2 V
DD
V
IL3
X
IN
, X
OUT
0.1
Output high voltage
V
OH1
V
DD
= 4.5 V to 5.5 V
EO0, EO1; I
OH
= 1 mA
V
DD
2.0
V
DD
V
OH2
V
DD
= 4.5 V to 5.5 V
Other output ports;
I
OH
= 1 mA
V
DD
1.0
V
DD
Output low voltage
V
OL1
V
DD
= 4.5 V to 5.5 V
EO0, EO1; I
OL
= 1 mA
2.0
V
OL2
V
DD
= 4.5 V to 5.5 V
Other output ports;
I
OL
= 10 mA
2.0
S3C830A/P830A
ELECTRICAL DATA
20-3
Table 20-2. D.C. Electrical Characteristics (Continued)
(T
A
= -25
C to + 85
C, V
DD
= 3.0 V to 5.5 V)
Parameter
Symbol
Conditions
Min.
Typ.
Max.
Unit
Input high leakage
current
I
LIH1
V
IN
= V
DD
All input pins except
X
IN
,
X
OUT
3
uA
I
LIH2
V
IN
= V
DD,
X
IN
,
X
OUT
20
Input low leakage
current
I
LIL1
V
IN
= 0 V
All input pins except
RESET,
X
IN
,
X
OUT
-3
I
LIL2
V
IN
= 0 V, X
IN
,
X
OUT
-20
Output high
leakage current
I
LOH
V
OUT
= V
DD
All output pins
3
Output low leakage
current
I
LOL
V
OUT
= 0 V
All output pins
-3
Pull-up resistor
R
L1
V
IN
= 0 V; V
DD
= 5 V
Port 08
25
50
100
k
R
L2
V
IN
= 0 V; V
DD
= 5 V;
RESET
150
250
400
Pull-down resistor
R
D
V
IN
= V
DD
, V
DD
= 5 V
VCOFM, VCOAM, AMIF
and FMIF
15
35
45
k
Oscillator feed
back resistors
R
OSC
V
DD
= 5 V, T
A
= 25
C
X
IN
= V
DD
, X
OUT
= 0 V
300
750
1500
k
LCD voltage
dividing resistor
R
LCD
T
A
= 25
C
70
110
150
k
|V
LCD
COMi|
voltage drop
(I = 03)
V
DC
15
A per common pin
45
120
mV
|V
LCD
SEGx|
voltage drop
(x = 039)
V
DS
15
A per common pin
45
120
mV
Middle output
voltage
V
LC0
V
DD
= 3.0 V to 5.5 V
0.6V
DD
0.2
0.6V
DD
0.6V
DD
+
0.2
V
V
LC1
0.4V
DD
0.2
0.4V
DD
0.4V
DD
+
0.2
V
LC2
0.2V
DD
0.2
0.2V
DD
0.2V
DD
+
0.2
ELECTRICAL DATA
S3C830A/P830A
20-4
Table 20-2. D.C. Electrical Characteristics (Concluded)
(T
A
= -25
C to + 85
C, V
DD
= 3.0 V to 5.5 V)
Parameter
Symbol
Conditions
Min.
Typ.
Max.
Unit
Supply current
(1)
I
DD1
Run mode:
4.5 MHz crystal oscillator
CE = V
DD
V
DD
= 5 V
10 %
C1 = C2 = 22pF
5.0
15
mA
I
DD2
Run mode:
4.5 MHz crystal oscillator
CE = 0 V
V
DD
= 5 V
10 %
C1 = C2 = 22pF
2.6
5.5
I
DD3
Idle mode:
4.5 MHz crystal oscillator
V
DD
= 5 V
10 %
0.6
2.0
I
DD4
(2)
Stop mode (in LVR disable):
CE = 0 V, T
A
= 25
C
V
DD
= 5 V
10 %
0.5
3
A
NOTES:
1.
Supply current does not include current drawn through internal pull-up resistors, PWM, or external output current loads.
2.
I
DD4
is current when the main clock oscillation stops.
3.
Every values in this table is measured when bits 43 of the system clock control register (CLKCON.4.3) is set to 11B.
S3C830A/P830A
ELECTRICAL DATA
20-5
Table 20-3. A.C. Electrical Characteristics
(T
A
= -25
C to +85
C, V
DD
= 3.0 V to 5.5 V)
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
Interrupt input
high, low width
(P1.0P1.7)
tINTH,
tINTL
P1.0P1.7, V
DD
= 5 V
200
ns
RESET
input low
width
tRSL
V
DD
= 5 V
10
us
t
TIH
t
TIL
0.8 V
DD
0.2 V
DD
0.2 V
DD
Figure 20-1. Input Timing for External Interrupts (Ports 1)
t
RSL
0.2 V
DD
RESET
Figure 20-2. Input Timing for
RESET
RESET
ELECTRICAL DATA
S3C830A/P830A
20-6
Table 20-4. Input/Output Capacitance
(T
A
= -25
C to +85
C, V
DD
=
0 V )
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
Input
capacitance
C
IN
f = 1 MHz; unmeasured pins
are returned to V
SS
10
pF
Output
capacitance
C
OUT
I/O capacitance
C
IO
Table 20-5. Data Retention Supply Voltage in Stop Mode
(T
A
= -25
C to + 85
C)
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
Data retention
supply voltage
V
DDDR
3.0
5.5
V
Data retention
supply current
I
DDDR
V
DDDR
= 2 V (TA = 25
C)
Stop mode (in LVR disable)
1
uA
Execution of
STOP Instrction
RESET
Occurs
~ ~
V
DDDR
~ ~
Stop Mode
Oscillation
Stabilization
Time
Normal
Operating Mode
Data Retention Mode
t
WAIT
RESET
V
DD
NOTE:
t
WAIT
is the same as 4096 x 16 x 1/fxx
0.2 V
DD
Figure 20-3. Stop Mode Release Timing Initiated by
RESET
RESET
S3C830A/P830A
ELECTRICAL DATA
20-7
Execution of
STOP Instruction
~ ~
V
DDDR
~ ~
Stop Mode
Idle Mode
Data Retention Mode
t
WAIT
V
DD
Interrupt
Normal
Operating Mode
Oscillation
Stabilization Time
0.2 V
DD
NOTE:
t
WAIT
is the same as 16 x 1/BT clock
Figure 20-4. Stop Mode Release Timing Initiated by Interrupts
Table 20-6. A/D Converter Electrical Characteristics
(T
A
= -25
C to +85
C, V
DD
= 3.5 V to 5.5 V, V
SS
= 0 V)
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
A/D converting
resolution
8
bits
Absolute accuracy
2
LSB
A/D conversion time
t
CON
Conversion clock = fxx
50/fxx
s
Analog input voltage
V
IAN
V
SS
V
DD
V
Analog input
impedance
R
AN
V
DD
= 5 V
2
1000
M
ELECTRICAL DATA
S3C830A/P830A
20-8
Table 20-7. PLL Electrical Characteristics
(T
A
= 25
C to +85
C, V
DD
= 4.5 V to 5.5 V)
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
VCOFM, VCOAM,
FMIF and AMIF
input voltage (peak
to peak)
V
IN
Sine wave input
0.3
V
DD
V
Frequency
fV
COAM
VCOAM mode, sine wave
input; V
IN
= 0.3V
P-P
0.5
30
MHz
fV
COFM
VCOFM mode, sine wave
input; V
IN
= 0.3V
P-P
30
150
f
AMIF
AMIF mode, sine wave
input; V
IN
= 0.3V
P-P
0.1
1.0
f
FMIF
FMIF mode, sine wave
input; V
IN
= 0.3V
P-P
5
15
Table 20-8. Low Voltage Reset Electrical Characteristics
(T
A
= 25
C to +85
C)
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
Detect voltage range
V
DET
3.0
3.5
4.0
V
LVR operating
current
I
BL
10
25
A
S3C830A/P830A
ELECTRICAL DATA
20-9
Table 20-9. Synchronous SIO Electrical Characteristics
(T
A
= 25
C to +85
C, V
DD
= 3.0 V to 5.5 V)
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
SCK0/SCK1 cycle time
t
CKY
External SCK0/SCK1 source
1000
ns
Internal SCK0/SCK1 source
1000
SCK0/SCK1 high, low
t
KH
, t
KL
External SCK0/SCK1 source
500
width
Internal SCK0/SCK1 source
t
KCY
/2
50
SI setup time to
t
SIK
External SCK0/SCK1 source
250
SCK0/SCK1 high
Internal SCK0/SCK1 source
250
SI hold time to
t
KSI
External SCK0/SCK1 source
400
SCK0/SCK1 high
Internal SCK0/SCK1 source
400
Output delay for
t
KSO
External SCK0/SCK1 source
300
SCK0/SCK1 to SO
Internal SCK0/SCK1 source
250
Output Data
Input Data
SCK0/SCK1
t
KH
t
CKY
t
KL
0.8 V
DD
0.2 V
DD
t
KSO
t
SIK
t
KSI
0.8 V
DD
0.2 V
DD
SI0/SI1
SO0/SO1
Figure 20-5. Serial Data Transfer Timing
ELECTRICAL DATA
S3C830A/P830A
20-10
Table 20-10. Main Oscillator Characteristics (fx)
(T
A
= 25
C to +85
C, V
DD
= 3.0 V to 5.5 V)
Oscillator
Clock Circuit
Test Condition
Min
Typ
Max
Unit
Crystal
X
IN
C1
C2
X
OUT
Crystal oscillation frequency
0.4
4.5
MHz
Ceramic
X
IN
C1
C2
X
OUT
Ceramic oscillation
frequency
0.4
4.5
MHz
External clock
X
IN
X
OUT
X
IN
input frequency
0.4
4.5
MHz
Table 20-11. Main Oscillator Clock Stabilization Time (t
ST1
)
(T
A
= -25
C to +85
C, V
DD
= 3.0 V to 5.5 V)
Oscillator
Test Condition
Min
Typ
Max
Unit
Crystal
V
DD
= 4.5 V to 5.5 V
10
ms
Ceramic
Stabilization occurs when V
DD
is equal to the minimum
oscillator voltage range.
4
ms
External clock
X
IN
input high and low level width (t
XH
, t
XL
)
111
1250
ns
NOTE: Oscillation stabilization time (tST1) is the time required for the CPU clock to return to its normal oscillation
frequency after a power-on occurs, or when Stop mode is ended by a
RESET
signal.
The
RESET
should therefore be held at low level until the tST1 time has elapsed
S3C830A/P830A
ELECTRICAL DATA
20-11
t
XH
t
XL
0.1V
X
IN
VDD-0.1V
1/fx
Figure 20-6. Clock Timing Measurement at X
IN
Instruction Clock
25 kHz
1
2
3
4
5
6
7
Supply Voltage (V)
When PLL/IFC operation, operating voltage range is 4.5 V to 5.5 V.
1.125 MHZ
Main Oscillator Frequency
400 kHz
CPU Clock = 1/4n x oscillator frequency (n = 1,2,8,16)
4.5 MHZ
Figure 20-7. Operating Voltage Range
ELECTRICAL DATA
S3C830A/P830A
20-12
NOTES
S3C830A/P830A
MECHANICAL DATA
21-1
21
MECHANICAL DATA
OVERVIEW
The S3C830A microcontroller is currently available in 100-pin-QFP package.
100-QFP-1420C
#100
20.00
0.20
23.90
0.30
14.00
0.20
17.90
0.30
0.15
+ 0.10
- 0.05
0-8
0.10 MAX
#1
0.65
NOTE: Dimensions are in millimeters.
(0.58)
0.80
0.20
0.05 MIN
2.65
0.10
3.00 MAX
0.80
0.20
0.30
+ 0.10
- 0.05
(0.83)
0.15 MAX
0.10 MAX
Figure 21-1. Package Dimensions (100-QFP-1420C)
MECHANICAL DATA
S3C830A/P830A
21-2
NOTES
S3C830A/P830A
S3P830A OTP
22-1
22
S3P830A OTP
OVERVIEW
The S3P830A single-chip CMOS microcontroller is the OTP (One Time Programmable)
version of the S3C830A
microcontroller. It has an on-chip OTP ROM instead of a masked ROM. The EPROM is accessed by serial data
format.
The S3P830A is fully compatible with the S3C830A, both in function in D.C. electrical characteristics and in pin
configuration. Because of its simple programming requirements, the S3P830A is ideal as an evaluation chip for
the S3C830A.
S3P830A OTP
S3C830A/P830A
22-2
FMIF
VDDPLL0
EO0
EO1
CE
P0.0
P0.1/T0CLK
P0.2/T0CAP
P0.3/T0OUT/T0PWM
P0.4/T1CLK
P0.5/T1OUT
P0.6/T2CLK
P0.7/T2OUT
P1.0/INT0
P1.1/INT1
P1.2/INT2
P1.3/INT3
P1.4/INT4
P1.5/INT5
P1.6/INT6
P1.7/INT7
P2.0/AD0
P2.1/AD1
P2.2/AD2
P2.3/AD3
P2.4
P2.5
P2.6
P2.7
AV
DD
P3.0/BUZ
P3.1/SCK0
SDAT/P3.2/SO0
SCLK/P3.3/SI0
V
DD
/V
DD
V
SS
/V
SS
X
OUT
X
IN
V
PP
/TEST1
TEST2
P3.4/SCK1
RESET
RESET/RESET
P3.5/SO1
P3.6/SI1
P3.7
P4.0/SEG39
P4.1/SEG38
P4.2/SEG37
P4.3/SEG36
P4.4/SEG35
S3P830A
100-QFP-1420C
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
AMIF
VSSPLL
VCOAM
VCOFM
VDDPLL1
LVREN
TEST3
BIAS
VLC0
VLC1
VLC2
COM0
COM1
COM2
COM3
SEG0/P8.7
SEG1/P8.6
SEG2/P8.5
SEG3/P8.4
SEG4/P8.3
SEG5/P8.2
SEG6/P8.1
SEG7/P8.0
SEG8/P7.7
SEG9/P7.6
SEG10/P7.5
SEG11/P7.4
SEG12/P7.3
SEG13/P7.2
SEG14/P7.1
SEG15/P7.0
SEG16/P6.7
SEG17/P6.6
SEG18/P6.5
SEG19/P6.4
SEG20/P6.3
SEG21/P6.2
SEG22/P6.1
SEG23/P6.0
SEG24/P5.7
SEG25/P5.6
SEG26/P5.5
SEG27/P5.4
SEG28/P5.3
SEG29/P5.2
SEG30/P5.1
SEG31/P5.0
SEG32/P4.7
SEG33/P4.6
SEG34/P4.5
Figure 22-1. S3P830A Pin Assignments (100-Pin QFP Package)
S3C830A/P830A
S3P830A OTP
22-3
Table 22-1. Descriptions of Pins Used to Read/Write the EPROM
Main Chip
During Programming
Pin Name
Pin Name
Pin No.
I/O
Function
P3.2/SO0
SDAT
13
I/O
Serial data pin. Output port when reading and
input port when writing. Can be assigned as a
Input/push-pull output port.
P3.3/SI0
SCLK
14
I
Serial clock pin. Input only pin.
TEST1
V
PP
19
I
Power supply pin for EPROM cell writing
(indicates that OTP enters into the writing mode).
When 12.5 V is applied, OTP is in writing mode
and when 5 V is applied, OTP is in reading mode.
(Option)
RESET
RESET
22
I
Chip Initialization
V
DD
/V
SS
V
DD
/V
SS
15/16
Logic power supply pin. VDD should be tied to
+5 V during programming.
Table 22-2. Comparison of S3P830A and S3C830A Features
Characteristic
S3P830A
S3C830A
Program Memory
48-Kbyte EPROM
48-Kbyte mask ROM
Operating Voltage (V
DD
)
3.0 V to 5.5 V
3.0 V to 5.5 V
OTP Programming Mode
V
DD
= 5 V, V
PP
(TEST1) = 12.5 V
Pin Configuration
100 QFP
100 QFP
EPROM Programmability
User Program 1 time
Programmed at the factory
OPERATING MODE CHARACTERISTICS
When 12.5 V is supplied to the V
PP
(TEST1) pin of the S3P830A, the EPROM programming mode is entered.
The operating mode (read, write, or read protection) is selected according to the input signals to the pins listed in
Table 21-3 below.
Table 22-3. Operating Mode Selection Criteria
VDD
VPP (TEST1)
REG/
MEM
MEM
Address(A15A0)
R/W
Mode
5 V
5 V
0
0000H
1
EPROM read
12.5 V
0
0000H
0
EPROM program
12.5 V
0
0000H
1
EPROM verify
12.5 V
1
0E3FH
0
EPROM read protection
NOTE: "0" means Low level; "1" means High level.
S3P830A OTP
S3C830A/P830A
22-4
Instruction Clock
25 kHz
1
2
3
4
5
6
7
Supply Voltage (V)
When PLL/IFC operation, operating voltage range is 4.5 V to 5.5 V.
1.125 MHZ
Main Oscillator Frequency
400 kHz
CPU Clock = 1/4n x oscillator frequency (n = 1,2,8,16)
4.5 MHZ
Figure 22-2. Operating Voltage Range
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