S3C7544/P7544
PRODUCT OVERVIEW
1-1
1
PRODUCT OVERVIEW
OVERVIEW
The S3C7544 single-chip CMOS microcontroller is designed for high-performance using Samsung's newest
4-bit CPU core, SAM47 (Samsung Arrangeable Microcontrollers).
With a versatile 8-bit timer/counter and a D/A converter, the S3C7544 offers an excellent design solution for a
wide variety of telecommunication applications.
Up to 17 pins of the 24-pin SDIP package can be dedicated to I/O. Four vectored interrupts provide fast response
to internal and external events. In addition, the S3C7544's advanced CMOS technology has realized substantially
lower power consumption with a wide operating voltage range -- all at a substantially lower cost.
OTP
The S3C7544 microcontroller is also available in OTP (One Time Programmable) version, S3P7544.
S3P7544 microcontroller has an on-chip 4-Kbyte one-time-programmable EPROM instead of masked ROM. The
S3P7544 is comparable to S3C7544, both in function and in pin configuration.
PRODUCT OVERVIEW
S3C7544/P7544
1-2
FEATURES SUMMARY
Memory
512
4-bit RAM
4096
8-bit ROM
I/O Pins
17 pins I/O
N-channel open-drain I/O: 8 pins
8-Bit Basic Timer
Programmable interval timer
Watchdog timer
Interval 8-Bit Timer/Counter
Programmable interval timer
External event counter function
Timer/counter clock output to TCLO0 pin
Buzzer Output
Four frequency output to BUZ pin
D/A Converter
8-bit D/A converter
Interrupts
Two external interrupt vectors
Two internal interrupt vectors
One quasi-interrupt
Memory-Mapped I/O Structure
Data memory bank 15
Bit Sequential Carrier
Supports 16-bit serial data transfer in arbitrary
format
Power-Down Modes
Idle mode (only CPU clock stops)
Stop mode (system clock stops)
Oscillation Sources
Crystal, or ceramic for system clock
Crystal, ceramic: 0.46.0 MHz
CPU clock divider circuit (by 4, 8, or 64)
Instruction Execution Times
0.95, 1.91, and 15.3
s at 4.19 MHz
0.67, 1.33, 10.7
s at 6.0 MHz
Operating Temperature
40
C to 85
C
Operating Voltage Range
1.8 V to 5.5 V (at 3 MHz)
2.7 V to 5.5 V (at 6 MHz)
Package Types
24-pin SOP-375
24-pin SDIP-300
S3C7544/P7544
PRODUCT OVERVIEW
1-3
BLOCK DIAGRAM
DAO
Arithmetic Logic Unit
Interrupt
Control
Block
Stack
Pointer
Program
Counter
Program
Status
Word
Flags
Instruction Decoder
Clock
X
IN
Internal
Interrupts
P4.0P4.3
P5.0P5.3
8-bit
Timer/
Counter
I/O Port 4
I/O Port 5
D/A
Converter
RESET
512 x 4-bit
Data
Memory
Basic
Timer
X
OUT
INT0, INT1
Buzzer
P0.0/INT0
P0.1/INT1
P0.2/KS0
P0.3/KS1
I/O Port 0
I/O Port 1
P1.0/TCL0
P1.1/TCLO0
P1.2/CLO
P1.3/BUZ
I/O Port 2
P2.0
4 K byte
Program
Memory
Watchdog
Timer
Figure 1-1. S3C7544 Simplified Block Diagram
PRODUCT OVERVIEW
S3C7544/P7544
1-4
PIN ASSIGNMENTS
V
SS
X
OUT
X
IN
TEST
P0.0/INT0
DAO
P0.1/INT1
RESET
P0.2/KS0
P0.3/KS1
P1.0/TCL0
P1.1/TCLO0
V
DD
P5.3
P5.2
P5.1
P5.0
P4.3
P4.2
P4.1
P4.0
P2.0
P1.3/BUZ
P1.2/CLO
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
S3C7544
24 SOP-375
24 SDIP-300
Figure 1-2. S3C7544 Pin Assignment Diagrams
S3C7544/P7544
PRODUCT OVERVIEW
1-5
PIN DESCRIPTIONS
Table 1-1. S3C7544 Pin Descriptions
Pin Name
Pin Type
Description
Share Pin
P0.0
P0.1
P0.2
P0.3
I
4-bit I/O port. 1- or 4-bit read/write and test is possible.
Pull-up resistors are assignable to input pins by software and are
automatically disabled for output pins. Pins are individually
configurable as input or output.
INT0
INT1
KS0
KS1
P1.0
P1.1
P1.2
P1.3
I/O
4-bit I/O port. 1- or 4-bit read/write and test is possible.
Pull-up resistors are assignable to input pins by software and are
automatically disabled for output pins. Pins are individually
configurable as input or output.
TCL0
TCLO0
CLO
BUZ
P2.0
I/O
1-bit I/O port. 1- or 4-bit read/write and test is possible.
Pull-up resistors are assignable to input pins by software and are
automatically disabled for output pins.
P4.0P4.3
P5.0P5.3
I/O
4-bit I/O port. 1- or 4-bit read/write and test is possible.
Pins are individually configurable as input or output.
Pull-up resistors are assignable to input pins by software and are
automatically disabled for output pins.
The N-channel open drain or push-pull output can be selected by
software (1-bit unit).
INT0
I/O
External interrupts with rising/falling edge detection
P0.0
INT1
I/O
External interrupts with rising/falling edge detection
P0.1
KS0
KS1
I/O
Quasi-interrupt input with falling edge detection
P0.2
P0.3
TCL0
I/O
External clock input for timer/counter
P1.0
TCLO0
I/O
Timer/counter clock output
P1.1
CLO
I/O
CPU clock output
P1.2
BUZ
I/O
0.5, 1, 2, or 4 kHz frequency output at 4.19 MHz for buzzer sound
P1.3
DAO
O
8-bit D/A converter output
V
DD
Main power supply
V
SS
Ground
RESET
I
Reset signal
TEST
I
Chip test input pin. Hold GND when the device is operating.
X
IN
, X
OUT
Crystal, ceramic oscillator signal for system clock
PRODUCT OVERVIEW
S3C7544/P7544
1-6
Table 1-2. Overview of S3C7544 Pin Data
SDIP Pin Numbers
Share Pins
I/O Type
Reset Value
Circuit Type
V
SS
X
OUT
, X
IN
TEST
I
P0.0, P0.1
INT0, INT1
I/O
Input
D-4
RESET
I
B
P0.2
P0.3
KS0
KS1
I/O
Input
D-4
P1.0
P1.1
P1.2
P1.3
TCL0
TCLO0
CLO
BUZ
I/O
Input
D-2
P2.0
I/O
Input
D-2
DAO
O
Output
P4.0P4.3
I/O
Input
E-2
P5.0P5.3
I/O
Input
E-2
V
DD
S3C7544/P7544
PRODUCT OVERVIEW
1-7
PIN CIRCUIT DIAGRAMS
V
DD
P
-
Channel
IN
N
-
Channel
Figure 1-3. Pin Circuit Type A
V
DD
Pull-up
Resistor
Schmitt Trigger
IN
Figure 1-4. Pin Circuit Type B
Data
Output
Disable
Out
V
DD
P
-
Channel
N
-
Channel
Figure 1-5. Pin Circuit Type C
P-Channel
Pull-up
Enable
Data
Output
Disable
In/Out
V
DD
Circuit
Type C
Figure 1-6. Pin Circuit Type D-2
PRODUCT OVERVIEW
S3C7544/P7544
1-8
P-Channel
Pull-up
Enable
Data
Output
Disable
In/Out
V
DD
Circuit
Type C
Figure 1-7. Pin Circuit Type D-4
Resistor
Enable
V
DD
Pull-Up
Resistor
V
DD
Data
Output
Disable
In/Out
PNE
Figure 1-8. Pin Circuit Type E-2
S3C7544/P7544
ELECTRICAL DATA
14-1
14
ELECTRICAL DATA
OVERVIEW
In this section, S3C7544 electrical characteristics are presented in tables and graphs. The information is
arranged in the following order:
Standard Electrical Characteristics
-- Absolute maximum ratings
-- D.C. electrical characteristics
-- Main system clock oscillator characteristics
-- Subsystem clock oscillator characteristics
-- I/O capacitance
-- A.C. electrical characteristics
-- Operating voltage range
Miscellaneous Timing Waveforms
-- A.C timing measurement point
-- Clock timing measurement at X
in
-- Clock timing measurement at XT
in
-- TCL timing
-- Input timing for
RESET
-- Input timing for external interrupts
-- Serial data transfer timing
Stop Mode Characteristics and Timing Waveforms
-- RAM data retention supply voltage in stop mode
-- Stop mode release timing when initiated by
RESET
-- Stop mode release timing when initiated by an interrupt request
ELECTRICAL DATA
S3C7544/P7544
14-2
Table 14-1. Absolute Maximum Ratings
(T
A
= 25
C)
Parameter
Symbol
Conditions
Rating
Units
Supply Voltage
V
DD
0.3 to + 6.5
V
Input Voltage
V
I
All I/O ports
0.3 to V
DD
+ 0.3
V
Output Voltage
V
O
0.3 to V
DD
+ 0.3
V
Output Current High
I
OH
One I/O port active
5
mA
All I/O ports active
35
Output Current Low
I
OL
One I/O port active
+ 30 (peak)
mA
+ 15
(note)
All I/O ports active
+ 100 (peak)
+ 60
(note)
Operating Temperature
T
A
40 to + 85
C
Storage Temperature
T
stg
65 to + 150
C
NOTE: The values for output current low (I
OL
) are calculated as peak value
Duty .
Table 14-2. D.C. Electrical Characteristics
(T
A
= 40
C to + 85
C, V
DD
= 1.8 V to 5.5 V)
Parameter
Symbol
Conditions
Min
Typ
Max
Units
Input High
Voltage
V
IH1
All input pins except V
IH2
V
IH3
0.7 V
DD
V
DD
V
V
IH2
P0 and
RESET
0.8 V
DD
V
DD
V
IH3
X
IN
and X
OUT
V
DD
0.1
V
DD
Input Low
Voltage
V
IL1
All input pins except V
IH2
V
IH3
0.3 V
DD
V
V
IL2
P0 and
RESET
0.2 V
DD
V
IL3
X
IN
and X
OUT
0.1
S3C7544/P7544
ELECTRICAL DATA
14-3
Table 14-2. D.C. Electrical Characteristics (Continued)
(T
A
= 40
C to + 85
C, V
DD
= 1.8 V to 5.5 V)
Parameter
Symbol
Conditions
Min
Typ
Max
Units
Output High
Voltage
V
OH
V
DD
= 4.5 V to 5.5 V
I
OH
= 1 mA
V
DD
1.0
V
Output Low
Voltage
V
OL1
V
DD
= 4.5 V to 5.5 V
I
OL
= 15 mA
Ports 4, 5
2
V
V
DD
= 1.8 V to 5.5 V
I
OL
= 1.6 mA
0.4
V
OL2
V
DD
= 4.5V to 5.5 V
I
OL
= 4 mA
All out ports except ports 4, 5
2
V
DD
= 1.8 V to 5.5 V
I
OL
= 1.6 mA
0.6
Input High
Leakage
Current
I
LIH1
V
IN
= V
DD
All input pins except X
IN
and X
OUT
3
A
I
LIH2
V
IN
= V
DD
X
IN
and X
OUT
20
Input Low
Leakage
Current
I
LIL1
V
IN
= 0 V
All input pins except X
IN
, X
OUT
and
RESET
3
A
I
LIL2
V
IN
= 0 V
X
IN
and X
OUT
20
Output High
Leakage
Current
I
LOH
V
O
= V
DD
All output pins
3
A
Output Low
Leakage
Current
I
LOL
V
O
= 0 V
All output pins
3
A
Pull-up
Resistor
R
L1
V
DD
= 5 V; V
I
= 0 V
except
RESET
25
45
100
k
V
DD
= 3 V
50
90
200
R
L2
V
DD
= 5 V; V
I
= 0 V;
RESET
100
220
400
V
DD
= 3 V
200
450
800
ELECTRICAL DATA
S3C7544/P7544
14-4
Table 14-2. D.C. Electrical Characteristics (Concluded)
(T
A
= 40
C to + 85
C, V
DD
= 1.8 V to 5.5 V)
Parameter
Symbol
Conditions
Min
Typ
Max
Units
Supply
I
DD1
Run mode; V
DD
= 5.0 V
10%
6.0MHz
3.4
10.0
mA
Current
(1)
(DAC on)
Crystal oscillator; C1 = C2 = 22pF
4.19MHz
2.7
8.0
I
DD2
Run mode; V
DD
= 5.0 V
10%
6.0MHz
2.3
8.0
mA
(DAC off)
Crystal oscillator; C1 = C2 = 22pF
4.19MHz
1.7
5.5
V
DD
= 3 V
10%
6.0MHz
1.1
4.0
4.19MHz
0.8
3.0
I
DD3
Idle mode; V
DD
= 5.0 V
10%
6.0MHz
0.7
2.5
mA
Crystal oscillator; C1 = C2 = 22pF
4.19MHz
0.5
1.8
V
DD
= 3 V
10%
6.0MHz
0.3
1.5
4.19MHz
0.2
1.0
I
DD4
Stop mode; V
DD
= 5.0 V
10%
0.2
3.0
A
Stop mode; V
DD
= 3.0 V
10%
0.1
2.0
NOTES:
1.
D.C. electrical values for supply current (I
DD1
to I
DD3
) do not include the current drawn through internal pull-up
resistors.
2.
I
DD1
typical values are measured when DADATA register value is 055H.
CPU CLOCK = 1/n x oscillator frequency (n = 4, 8 or 64)
SUPPLY VOLTAGE (V)
0.75 MHz
15.625 kHz
CPU CLOCK
3 MHz
6 MHz
400 kHz
Main Osc. Freq.
1.5 MHz
1
2
2.7
3
4
5
6
7
1.8
Figure 14-1. Standard Operating Voltage Range
S3C7544/P7544
ELECTRICAL DATA
14-5
Table 14-3. Oscillators Characteristics
(T
A
= 40
C + 85
C, V
DD
= 1.8 V to 5.5 V)
Oscillator
Clock
Configuration
Parameter
Test Condition
Min
Typ
Max
Units
Ceramic
Oscillator
Xin
Xout
C1
C2
Oscillation frequency
(1)
V
DD
= 2.7 V to 5.5 V
0.4
6.0
MHz
V
DD
= 1.8 V to 5.5 V
0.4
3
Stabilization time
(2)
V
DD
= 3.0 V
4
ms
Crystal
Oscillator
Xin
Xout
C1
C2
Oscillation frequency
(1)
V
DD
= 2.7 V to 5.5 V
0.4
6.0
MHz
V
DD
= 1.8 V to 5.5 V
0.4
3
Stabilization time
(2)
V
DD
= 3.0 V
10
ms
External
Clock
Xin
Xout
X
IN
input frequency
(1)
V
DD
= 2.7 V to 5.5 V
0.4
6.0
MHz
V
DD
= 1.8 V to 5.5 V
0.4
3
X
IN
input high and low
level width (t
XH
, t
XL
)
83.3
1250
ns
NOTES:
1.
Oscillation frequency and X
IN
input frequency data are for oscillator characteristics only.
2.
Stabilization time is the interval required for oscillating stabilization after a power-on occurs, or when stop mode is
terminated.
ELECTRICAL DATA
S3C7544/P7544
14-6
Table 14-4. Recommended Oscillator Constants
(T
A
= 40
C + 85
C, V
DD
= 1.8 V to 5.5 V)
Manufacturer
Series
Number
(1)
Frequency Range
Load Cap (pF)
Oscillator Voltage
Range (V)
Remarks
C1
C2
MIN
MAX
TDK
FCR
M5
3.58 MHz6.0 MHz
33
33
2.0
5.5
Leaded Type
FCR
MC5
3.58 MHz6.0 MHz
(2)
(2)
2.0
5.5
On-chip C
Leaded Type
CCR
MC3
3.58 MHz6.0 MHz
(3)
(3)
2.0
5.5
On-chip C
SMD Type
NOTES:
1.
Please specify normal oscillator frequency.
2.
On-chip C: 30pF built in.
3.
On-chip C: 38pF built in.
Table 14-5. Input/Output Capacitance
(T
A
= 25
C, V
DD
= 0 V )
Parameter
Symbol
Condition
Min
Typ
Max
Units
Input
Capacitance
C
IN
f = 1 MHz; Unmeasured pins
are returned to V
SS
15
pF
Output
Capacitance
C
OUT
15
pF
I/O Capacitance
C
IO
15
pF
Table 14-6. D/A Converter Electrical Characteristics
(T
A
= 40
C to + 85
C, V
DD
= 3.5 V to 5.5 V, V
SS
= 0 V)
Parameter
Symbol
Condition
Min
Typ
Max
Units
Resolution
8
bits
Absolute Accuracy
3
3
LSB
Differential Linearity Error
DLE
1
1
LSB
Setup Time
t
su
5
s
Output Resistance
R
O
4.5
5
5.5
K
S3C7544/P7544
ELECTRICAL DATA
14-7
Table 14-7. A.C. Electrical Characteristics
(T
A
= 40
C to + 85
C, V
DD
= 1.8 V to 5.5 V)
Parameter
Symbol
Conditions
Min
Typ
Max
Units
Instruction Cycle
Time
t
CY
V
DD
= 2.7 V to 5.5 V
0.67
64
s
V
DD
= 1.8 V to 5.5 V
1.33
TCL0 Input
Frequency
f
TI
V
DD
= 2.7 V to 5.5 V
0
1.5
MHz
V
DD
= 1.8 V to 5.5 V
1
MHz
TCL0 Input High,
Low Width
t
TIH,
t
TIL
V
DD
= 2.7 V to 5.5 V
0.48
s
V
DD
= 1.8 V to 5.5 V
1.8
Interrupt Input
High, Low Width
t
INTH,
t
INTL
INT0, INT1, KS0KS1
10
s
RESET
Input Low
Width
t
RSL
Input
10
s
Table 14-8. RAM Data Retention Supply Voltage in Stop Mode
(T
A
= 40
C to + 85
C)
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
Data retention supply voltage
V
DDDR
1.8
5.5
V
Data retention supply current
I
DDDR
V
DDDR
= 1.8 V
0.1
10
A
Release signal set time
t
SREL
0
s
Oscillator stabilization wait
time
(1)
t
WAIT
Released by
RESET
2
17
/fx
ms
Released by interrupt
(2)
ms
NOTES:
1.
During oscillator stabilization wait time, all CPU operations must be stopped to avoid instability during oscillator
start-up.
2.
Use the basic timer mode register (BMOD) interval timer to delay the execution of CPU instructions during the wait time.
ELECTRICAL DATA
S3C7544/P7544
14-8
TIMING WAVEFORMS
t
SREL
t
WAIT
V
DD
RESET
EXECUTION OF
STOP INSTRUCTION
V
DDDR
DATA RETENTION MODE
STOP MODE
INTERNAL RESET
OPERATION
IDLE MODE
OPERATING
MODE
~ ~
~ ~
Figure 14-2. Stop Mode Release Timing When Initiated by
RESET
RESET
V
DD
EXECUTION OF
STOP INSTRUCTION
V
DDDR
DATA RETENTION
STOP MODE
t
WAIT
t
SREL
IDLE MODE
NORMAL
OPERATING
MODE
POWER-DOWN MODE TERMINATING
(INTERRUPT REQUEST)
~ ~
~ ~
Figure 14-3. Stop Mode Release Timing When Initiated by Interrupt Request
S3C7544/P7544
ELECTRICAL DATA
14-9
0.8 V
DD
0.2 V
DD
0.8 V
DD
0.2 V
DD
MEASUREMENT
POINTS
Figure 14-4. A.C. Timing Measurement Points (Except for X
IN
)
X
IN
t
XL
t
XH
1 / f x
V
DD
0.1 V
0.1 V
Figure 14-5. Clock Timing Measurement at X
IN
ELECTRICAL DATA
S3C7544/P7544
14-10
TCL
t
TIL
t
TIH
0.7 V
DD
0.3 V
DD
1 / f TI
Figure 14-6. TCL Timing
RESET
0.2 V
DD
t
RSL
Figure 14-7. Input Timing for
RESET
RESET
Signal
INT0, 1
KS0 to KS1
t
INTL
tINTH
0.8 V
DD
0.2 V
DD
Figure 14-8. Input Timing for External Interrupts
S3C7544/P7544
MECHANICAL DATA
151
15
MECHANICAL DATA
This section contains the following information about the device package:
-- Package dimensions in millimeters
-- Pad diagram
-- Pad/pin coordinate data table
NOTE: Typical dimensions are in millimeters.
30-SDIP-400
8.94 0.2
0.56 0.1
27.48 0.2
0 ~ 15
0.25
+0.1 0.05
#1
15
30
16
10.16
(1.30)
1.12 0.1
1.778
0.51MIN
3.81 0.2
3.30 0.3
5.08MAX
Figure 15-1. 30-SDIP-400 Package Dimensions
S3C7544/P7544
S3P7544 OTP
16-1
16
S3P7544 OTP
OVERVIEW
The S3P7544 single-chip CMOS microcontroller is the OTP (One Time Programmable)
version of the S3C7544
microcontroller. It has an on-chip OTP ROM instead of masked ROM. The EPROM is accessed by serial data
format.
The S3P7544 is fully compatible with the S3C7544, both in function and in pin configuration. Because of its
simple programming requirements, the S3P7544 is ideal for use as an evaluation chip for the S3C7544.
V
SS
/V
SS
X
OUT
X
IN
V
PP
/TEST
P0.0/INT0
DAO
P0.1/INT1
RESET
RESET /RESET
P0.2/KS0
P0.3/KS1
P1.0/TCL0
P1.1/TCLO0
V
DD
/V
DD
P5.3/ SCLK
P5.2/ SDAT
P5.1
P5.0
P4.3
P4.2
P4.1
P4.0
P2.0
P1.3/BUZ
P1.2/CLO
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
S3P7544
24 SOP-375
24 SDIP-300
Figure 16-1. S3P7544 Pin Assignments (24 SOP-375, 24 SDIP-300 Package)
S3P7544 OTP
S3C7544/P7544
16-2
Table 16-1. Descriptions of Pins Used to Read/Write the EPROM
Main Chip
During Programming
Pin Name
Pin Name
Pin No.
I/O
Function
P5.2
SDAT
22
I/O
Serial data pin. Output port when reading and input
port when writing. Can be assigned as a Input /
push-pull output port.
P5.3
SCLK
23
I/O
Serial clock pin. Input only pin.
TEST
TEST
4
I
Power supply pin for EPROM cell writing (indicates
that OTP enters into the writing mode). When 12.5
V is applied, OTP is in writing mode and when 5 V
is applied, OTP is in reading mode. (Option)
Hold GND when OTP is operating.
RESET
RESET
8
I
Chip initialization
V
DD
/V
SS
V
DD
/V
SS
24/1
Logic power supply pin. V
DD
should be tied to +5 V
during programming.
NOTE: ( ) means the 32-SOP OTP pin number.
Table 16-2. Comparison of S3P7544 and S3C7544 Features
Characteristic
S3P7544
S3C7544
Program Memory
4 K-byte EPROM
4 K-byte mask ROM
Operating Voltage (V
DD
)
1.8 V (3 MHz) to 5.5 V
1.8 V (3 MHz) to 5.5 V
OTP Programming Mode
V
DD
= 5 V, V
PP
(TEST) = 12.5 V
Pin Configuration
24 SOP, 24 SDIP
24 SOP, 24 SDIP
EPROM Programmability
User Program one time
Programmed at the factory
OPERATING MODE CHARACTERISTICS
When 12.5 V is supplied to the V
PP
(TEST) pin of the S3P7544, the EPROM programming mode is entered. The
operating mode (read, write, or read protection) is selected according to the input signals to the pins listed in
Table 16-3 below.
Table 16-3. Operating Mode Selection Criteria
V
DD
V
PP
(TEST)
REG/
MEM
Address
(A15-A0)
R/W
Mode
5 V
5 V
0
0000H
1
EPROM read
12.5 V
0
0000H
0
EPROM program
12.5 V
0
0000H
1
EPROM verify
12.5 V
1
0E3FH
0
EPROM read protection
NOTE: "0" means Low level; "1" means High level.
S3C7544/P7544
S3P7544 OTP
16-3
OTP ELECTRICAL DATA
Table 16-4. Absolute Maximum Ratings
(T
A
= 25
C)
Parameter
Symbol
Conditions
Rating
Units
Supply Voltage
V
DD
0.3 to + 6.5
V
Input Voltage
V
I
All I/O ports
0.3 to V
DD
+ 0.3
V
Output Voltage
V
O
0.3 to V
DD
+ 0.3
V
Output Current High
I
OH
One I/O port active
5
mA
All I/O ports active
35
Output Current Low
I
OL
One I/O port active
+ 30 (peak)
mA
+ 15
(note)
All I/O ports active
+ 100 (peak)
+ 60
(note)
Operating Temperature
T
A
40 to + 85
C
Storage Temperature
T
stg
65 to + 150
C
NOTE: The values for output current low (I
OL
) are calculated as peak value
Duty .
Table 16-5. D.C. Electrical Characteristics
(T
A
= 40
C to + 85
C, V
DD
= 1.8 V to 5.5 V)
Parameter
Symbol
Conditions
Min
Typ
Max
Units
Input High
Voltage
V
IH1
All input pins except V
IH2
V
IH3
0.7 V
DD
V
DD
V
V
IH2
P0 and
RESET
0.8 V
DD
V
DD
V
IH3
X
IN
and X
OUT
V
DD
0.1
V
DD
Input Low
Voltage
V
IL1
All input pins except V
IH2
V
IH3
0.3 V
DD
V
V
IL2
P0 and
RESET
0.2 V
DD
V
IL3
X
IN
and X
OUT
0.1
S3P7544 OTP
S3C7544/P7544
16-4
Table 16-5. D.C. Electrical Characteristics (Continued)
(T
A
= 40
C to + 85
C, V
DD
= 1.8 V to 5.5 V)
Parameter
Symbol
Conditions
Min
Typ
Max
Units
Output High
Voltage
V
OH
V
DD
= 4.5 V to 5.5 V
I
OH
= 1 mA
V
DD
1.0
V
Output Low
Voltage
V
OL1
V
DD
= 4.5 V to 5.5 V
I
OL
= 15 mA
Ports 4, 5
2
V
V
DD
= 1.8 V to 5.5 V
I
OL
= 1.6 mA
0.4
V
OL2
V
DD
= 4.5V to 5.5 V
I
OL
= 4 mA
All out ports except ports 4, 5
2
V
DD
= 1.8 V to 5.5 V
I
OL
= 1.6 mA
0.6
Input High
Leakage
Current
I
LIH1
V
IN
= V
DD
All input pins except X
IN
and X
OUT
3
A
I
LIH2
V
IN
= V
DD
X
IN
and X
OUT
20
Input Low
Leakage
Current
I
LIL1
V
IN
= 0 V
All input pins except X
IN
, X
OUT
and
RESET
3
A
I
LIL2
V
IN
= 0 V
X
IN
and X
OUT
20
Output High
Leakage
Current
I
LOH
V
O
= V
DD
All output pins
3
A
Output Low
Leakage
Current
I
LOL
V
O
= 0 V
All output pins
3
A
Pull-up
Resistor
R
L1
V
DD
= 5 V; V
I
= 0 V
except
RESET
25
50
100
k
V
DD
= 3 V
50
100
200
R
L2
V
DD
= 5 V; V
I
= 0 V;
RESET
100
250
400
V
DD
= 3 V
200
500
800
S3C7544/P7544
S3P7544 OTP
16-5
Table 16-5. D.C. Electrical Characteristics (Concluded)
(T
A
= 40
C to + 85
C, V
DD
= 1.8 V to 5.5 V)
Parameter
Symbol
Conditions
Min
Typ
Max
Units
Supply
I
DD1
Run mode; V
DD
= 5.0 V
10%
6.0MHz
3.4
10.0
mA
Current
(1)
(DAC on)
Crystal oscillator; C1 = C2 = 22pF
4.19MHz
2.7
8.0
I
DD2
Run mode; V
DD
= 5.0 V
10%
6.0MHz
2.3
8.0
mA
(DAC off)
Crystal oscillator; C1 = C2 = 22pF
4.19MHz
1.7
5.5
V
DD
= 3 V
10%
6.0MHz
1.1
4.0
4.19MHz
0.8
3.0
I
DD3
Idle mode; V
DD
= 5.0 V
10%
6.0MHz
0.7
2.5
mA
Crystal oscillator; C1 = C2 = 22pF
4.19MHz
0.5
1.8
V
DD
= 3 V
10%
6.0MHz
0.3
1.5
4.19MHz
0.2
1.0
I
DD4
Stop mode; V
DD
= 5.0 V
10%
0.2
3.0
A
Stop mode; V
DD
= 3.0 V
10%
0.1
2.0
NOTES:
1.
D.C. electrical values for supply current (I
DD1
to I
DD3
) do not include the current drawn through internal pull-up
resistors.
2.
I
DD1
typical values are measured when DADATA register value is 055H .
CPU CLOCK = 1/n x oscillator frequency (n = 4, 8 or 64)
SUPPLY VOLTAGE (V)
0.75 MHz
15.625 kHz
CPU CLOCK
3 MHz
6 MHz
400 kHz
Main Osc. Freq.
1.5 MHz
1
2
2.7
3
4
5
6
7
1.8
Figure 16-2. Standard Operating Voltage Range
S3P7544 OTP
S3C7544/P7544
16-6
Table 16-6. Oscillators Characteristics
(T
A
= 40
C + 85
C, V
DD
= 1.8 V to 5.5 V)
Oscillator
Clock
Configuration
Parameter
Test Condition
Min
Typ
Max
Units
Ceramic
Oscillator
Xin
Xout
C1
C2
Oscillation frequency
(1)
V
DD
= 2.7 V to 5.5 V
0.4
6.0
MHz
V
DD
= 1.8 V to 5.5 V
0.4
3
Stabilization time
(2)
V
DD
= 3.0 V
4
ms
Crystal
Oscillator
Xin
Xout
C1
C2
Oscillation frequency
(1)
V
DD
= 2.7 V to 5.5 V
0.4
6.0
MHz
V
DD
= 1.8 V to 5.5 V
0.4
3
Stabilization time
(2)
V
DD
= 3.0 V
10
ms
External
Clock
Xin
Xout
X
IN
input frequency
(1)
V
DD
= 2.7 V to 5.5 V
0.4
6.0
MHz
V
DD
= 1.8 V to 5.5 V
0.4
3
X
IN
input high and low
level width (t
XH
, t
XL
)
83.3
1250
ns
NOTES:
1.
Oscillation frequency and X
IN
input frequency data are for oscillator characteristics only.
2.
Stabilization time is the interval required for oscillating stabilization after a power-on occurs, or when stop mode is
terminated.
S3C7544/P7544
S3P7544 OTP
16-7
Table 16-7. Input/Output Capacitance
(T
A
= 25
C, V
DD
= 0 V )
Parameter
Symbol
Condition
Min
Typ
Max
Units
Input
Capacitance
C
IN
f = 1 MHz; Unmeasured pins
are returned to V
SS
15
pF
Output
Capacitance
C
OUT
15
pF
I/O Capacitance
C
IO
15
pF
Table 16-8. Comparator Electrical Characteristics
(T
A
= 40
C to + 85
C, V
DD
= 3.5 V to 5.5 V, V
SS
= 0 V)
Parameter
Symbol
Condition
Min
Typ
Max
Units
Resolution
8
bits
Absolute Accuracy
3
3
LSB
Differential Linearity Error
DLE
1
1
LSB
Setup Time
t
su
5
s
Output Resistance
R
O
4.5
5
5.5
K
Table 16-9. A.C. Electrical Characteristics
(T
A
= 40
C to + 85
C, V
DD
= 1.8 V to 5.5 V)
Parameter
Symbol
Conditions
Min
Typ
Max
Units
Instruction Cycle
Time
t
CY
V
DD
= 2.7 V to 5.5 V
0.67
64
s
V
DD
= 1.8 V to 5.5 V
1.33
TCL0 Input
Frequency
f
TI
V
DD
= 2.7 V to 5.5 V
0
1.5
MHz
V
DD
= 1.8 V to 5.5 V
1
MHz
TCL0 Input High,
Low Width
t
TIH,
t
TIL
V
DD
= 2.7 V to 5.5 V
0.48
s
V
DD
= 1.8 V to 5.5 V
1.8
Interrupt Input
High, Low Width
t
INTH,
t
INTL
INT0, INT1, KS0KS1
10
s
RESET
Input Low
Width
t
RSL
Input
10
s
S3P7544 OTP
S3C7544/P7544
16-8
Table 16-10. RAM Data Retention Supply Voltage in Stop Mode
(T
A
= 40
C to + 85
C)
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
Data retention supply voltage
V
DDDR
1.8
5.5
V
Data retention supply current
I
DDDR
V
DDDR
= 1.8 V
0.1
10
A
Release signal set time
t
SREL
0
s
Oscillator stabilization wait
time
(1)
t
WAIT
Released by
RESET
2
17
/fx
ms
Released by interrupt
(2)
ms
NOTES:
1.
During oscillator stabilization wait time, all CPU operations must be stopped to avoid instability during oscillator
start-up.
2.
Use the basic timer mode register (BMOD) interval timer to delay the execution of CPU instructions during the wait time.
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