S3CB519/FB519
PRODUCT OVERVIEW
1-1
1
PRODUCT OVERVIEW
OVERVIEW
The S3CB519/FB519 single-chip CMOS microcontroller is designed for high performance using Samsung's new
8-bit CPU core, CalmRISC.
CalmRISC is an 8-bit low power RISC microcontroller. Its basic architecture follows Harvard style, that is, it has
separate program memory and data memory. Both instruction and data can be fetched simultaneously without
causing a stall, using separate paths for memory access. Represented below is the top block diagram of the
CalmRISC microcontroller.
PRODUCT OVERVIEW
S3CB519/FB519
1-2
BBUS[7:0]
20
Program Memory Address
Generation Unit
PC[19:0]
Hardware
Stack
HS[0]
HS[15]
8
8
R0
R3
R1
R2
ALU
ABUS[7:0]
ALUL
ALUR
PA[19:0]
PD[15:0]
IDL0
IDL1
SR0
SR1
ILH
ILX
ILL
SPR
IDH
DO[7:0]
DI[7:0]
GPR
Data Memory
Address
Generation Unit
DA[15:0]
20
Flag
RBUS
TBH TBL
Figure 1-1. Top Block Diagram
S3CB519/FB519
PRODUCT OVERVIEW
1-3
The CalmRISC building blocks consist of:
-- An 8-bit ALU
-- 16 general purpose registers (GPR)
-- 11 special purpose registers (SPR)
-- 16-level hardware stack
-- Program memory address generation unit
-- Data memory address generation unit
Sixteen GPRs are grouped into four banks (Bank0 to Bank3), and each bank has four 8-bit registers (R0, R1, R2,
and R3). SPRs, designed for special purposes, include status registers, link registers for branch-link instructions,
and data memory index registers. The data memory address generation unit provides the data memory address
(denoted as DA[15:0] in the top block diagram) for a data memory access instruction. Data memory contents are
accessed through DI[7:0] for read operations and DO[7:0] for write operations. The program memory address
generation unit contains a program counter, PC[19:0], and supplies the program memory address through
PA[19:0] and fetches the corresponding instruction through PD[15:0] as the result of the program memory
access. CalmRISC has a 16-level hardware stack for low power stack operations as well as a temporary storage
area.
Instruction Fetch
(IF)
Instruction Decode/
Data Memory Access
(ID/MEM)
Execution/Writeback
(EXE/WB)
Figure 1-2. CalmRISC Pipeline Diagram
CalmRISC has a 3-stage pipeline as described below:
As can be seen in the pipeline scheme, CalmRISC adopts a register-memory instruction set. In other words, data
memory where R is a GPR can be one operand of an ALU instruction as shown below:
The first stage (or cycle) is the Instruction fetch stage (IF for short), where the instruction pointed by the program
counter, PC[19:0] , is read into the Instruction Register (IR for short). The second stage is the Instruction Decode
and Data Memory Access stage (ID/MEM for short), where the fetched instruction (stored in IR) is decoded and
data memory access is performed, if necessary. The final stage is the Execute and Write-back stage (EXE/WB),
where the required ALU operation is executed and the result is written back into the destination registers.
Since CalmRISC instructions are pipelined, the next instruction fetch is not postponed until the current instruction
is completely finished but is performed immediately after completing the current instruction fetch. The pipeline
stream of instructions is illustrated in the following diagram.
PRODUCT OVERVIEW
S3CB519/FB519
1-4
EXE/WB
IF
IF
IF
IF
IF
IF
IF
ID/MEM
ID/MEM
ID/MEM
ID/MEM
ID/MEM
ID/MEM
EXE/WB
EXE/WB
EXE/WB
EXE/WB
EXE/WB
/ 1
/ 2
/ 3
/ 4
/ 6
/ 5
Figure 1-3. CalmRISC Pipeline Stream Diagram
Most CalmRISC instructions are 1-word instructions, while same branch instructions such as long "call" and "jp"
instructions are 2-word instructions. In Figure 1-3, the instruction, I4, is a long branch instruction, and it takes two
clock cycles to fetch the instruction. As indicated in the pipeline stream, the number of clocks per instruction
(CPI) is 1 except for long branches, which take 2 clock cycles per instruction.
S3CB519/FB519
PRODUCT OVERVIEW
1-5
FEATURES
CPU
8-bit CalmRISC
Coprocessor
MAC 816
8
16, 16
16 multiply and accumulation
Arithmetic operation
Memory
ROM: 16K-word
RAM: 3K-byte
2048 (X-memory)
1024 (Y-memory)
I/O Pins
11 I/O: not include COM/SEG
35 I/O: include COM/SEG
Power-Down
Idle mode: only CPU clock stops
Stop mode: main system oscillator stops
Sub-system clock stop mode
ROM Option
Basic timer counter clock source selection reset
value
Watchdog timer enable/disable selection
8-Bit Basic Timer
Programmable interval timer
8 kinds of clock source
Watchdog Timer
System reset
Watch Timer
Real time clock or interval time measurement
Buzzer function (0.5/1/2/4 kHz at 4.19 MHz
OSC)
Timer/Counters
One 8-bit timer with PWM/Capture
One 16-bit general-purpose timer/counter
LCD Controller/Driver
56 SEG
16 COM terminals
8, 12 and 16 COM selectable
16-level contrast control
Key strobe output function
Battery Level Detector
2.4, 2.7, 3.0, 3.3, 4.0, 4.5 V detectable
Internal level and/or external level selectable
8-Bit Serial I/O Interface
8-bit transmit/receive mode
8-bit receive mode
LSB-first or MSB-first transmission selectable
A/D Converter
Sigma delta ADC
Linear 14-bit data (16-bit format)
256X over sampling
Operation voltage: V
DD
= 3.0 V5.5 V
D/A Converter
8-bit resolution
Regulated output voltage
Operation voltage: V
DD
= 2.4 V5.5 V
Oscillation Sources
Crystal, ceramic, RC for main system clock
Crystal or external oscillator for subsystem clock
Main system clock frequency: Max 8.2 MHz
Subsystem clock frequency: 32.768 kHz
Operating Voltage
2.2 V to 5.5 V
Operating Temperature Range
40
C to 85
C
Package Type
100 QFP-1420C
PRODUCT OVERVIEW
S3CB519/FB519
1-6
P5.0-P5.15
CalmRISC
CPU
Main OSC
MAC
816
X-Memory
2048 Bytes
Y-Memory
1024 Bytes
SIO
Timer 0
Watch
Timer
BLD
Timer A
Timer B
Timer 1
SI
S0
SCK
T0/T0CAP/
T0PWM
T0CK
BUZ
BLD
CODEC
AV
DD
AV
SS
ADINP
ADINN
ADGAIN
DAOUT
AVREFOUT
REFH
REFL
Port 4
Port 3
Port 2
Port 1
Port 0
Port 5
Basic
Timer
SUB OSC
WDT
X
IN
X
OUT
XT
IN
XT
OUT
TACK
TB
LCD Driver/Controller
Control
Register
128 Bytes
COM0-COM15
SEG0-SEG55
P4.0-P4.7
P3.0-P3.7
P2.0-P2.7
P1.0-P1.3
P0.0-P0.6
Figure 1-4. S3CB519/FB519 Block Diagram
S3CB519/FB519
PRODUCT OVERVIEW
1-7
PIN ASSIGNMENT
COM8/P4.0
COM7
COM6
COM5
COM4
COM3
COM2
COM1
COM0
SEG0
SEG1
SEG2
SEG3
SEG4
SEG5
SEG6
SEG7
SEG8
SEG9
SEG10
REFL
P1.0/KS0
P1.1/KS1
P1.2/KS2
P1.3/KS3
P2.0/SEG55
P2.1/SEG54
P2.2/SEG53
P2.3/SEG52
P2.4/SEG51
P2.5/SEG50
P2.6/SEG49
P2.7/SEG48
P3.0/SEG47
P3.1/SEG46
P3.2/SEG45
P3.3/SEG44
P3.4/SEG43
P3.5/SEG42
P3.6/SEG41
SEG11
SEG12
SEG13
SEG14
SEG15
SEG16
SEG17
SEG18
SEG19
SEG20
SEG21
SEG22
SEG23
SEG24/P5.15
SEG25/P5.14
SEG26/P5.13
SEG27/P5.12
SEG28/P5.11
SEG29/P5.10
SEG30/P5.9
SEG31/P5.8
SEG32/P5.7
SEG33/P5.6
SEG34/P5.5
SEG35/P5.4
SEG36/P5.3
SEG37/P5.2
SEG38/P5.1
SEG39/P5.0
SEG40/P3.7
COM9/P4.1
COM10/P4.2
COM11/P4.3
COM12/P4.4
COM13/P4.5
COM14/P4.6
COM15/P4.7
P0.0/INT0/TB
P0.1/INT1/T0/T0CAP/T0PWM
P0.2/INT2/T0CK/BUZ
P0.3/INT3/TACK/BLD
P0.4/INT4/
SCK
P0.5/INT5/SO
P0.6/INT6/SI
V
DD
V
SS
X
OUT
X
IN
TEST
XT
IN
XT
OUT
RESET
DAOUT
AV
DD
AV
SS
ADINP
ADINN
ADGAIN
AVREFOUT
REFH
S3CB519
(100-QFP-1420C)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
Figure 1-5. S3CB519 Pin Assignment Diagram (100-QFP)
S3CB519/FB519
ELECTRICAL DATA
22-1
22
ELECTRICAL DATA
OVERVIEW
Table 22-1. Absolute Maximum Ratings
(T
A
= 25
C)
Parameter
Symbol
Conditions
Rating
Unit
Supply voltage
V
DD
-0.3 to + 6.5
V
Input voltage
V
I
-0.3 to V
DD
+ 0.3
V
Output voltage
V
O
-0.3 to V
DD
+ 0.3
V
Output current high
I
OH
One I/O pin active
-18
mA
All I/O pins active
-60
Output current low
I
OL
One I/O pin active
+ 30
mA
Total pin current for port
+ 100
Operating temperature
T
A
-40 to + 85
C
Storage temperature
T
STG
-65 to + 150
C
Table 22-2. D.C. Electrical Characteristics
(T
A
= -40
C to + 85
C, V
DD
= 2.2 V to 5.5 V)
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
Operating voltage
V
DD
fxx = 8.2 MHz
3.0
5.5
V
fxx = 4.1 MHz
2.2
5.5
Input high voltage
V
IH1
All input pins except V
IH2
0.8 V
DD
V
DD
V
V
IH2
X
IN
, XT
IN
V
DD
-0.1
Input low voltage
V
IL1
All input pins except V
IL2
0.2 V
DD
V
V
IL2
X
IN
, XT
IN
0.1
ELECTRICAL DATA
S3CB519/FB519
22-2
Table 22-2. D.C. Electrical Characteristics (Continued)
(T
A
= -40
C to + 85
C, V
DD
= 2.2 V to 5.5 V)
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
Output high voltage
V
OH1
V
DD
= 5 V; I
OH
= -1 mA
All output pins except V
OH2
V
DD
-1.0
V
V
OH2
V
DD
= 5 V; I
OH
= -15 mA
Port 5
V
DD
-1.0
Output low voltage
V
OL1
V
DD
= 4.5-5.5 V; I
OL
= 15 mA
0.4
2
V
Input high leakage
current
I
LIH1
V
IN
= V
DD
All input pins except I
LIH2
3
uA
I
LIH2
V
IN
= V
DD
X
IN
, XT
IN
, X
OUT
, XT
OUT
20
Input low leakage
current
I
LIL1
V
IN
= 0 V
All input pins except I
LIL2
-3
I
LIL2
V
IN
= 0 V
X
IN
, XT
IN
, X
OUT
, XT
OUT
,
RESET
-20
Output high
leakage current
I
LOH
V
OUT
= V
DD
All I/O pins and Output pins
3
Output low
leakage current
I
LOL
V
OUT
= 0 V
All I/O pins and Output pins
-3
Pull-up resistor
R
L1
V
IN
= 0 V; V
DD
= 5 V
10%
All port, T
A
= 25
C
30
50
70
k
R
L2
V
IN
= 0 V; V
DD
= 5 V
10%
T
A
= 25
C,
RESET
only
110
210
310
S3CB519/FB519
ELECTRICAL DATA
22-3
Table 22-2. D.C. Electrical Characteristics (Concluded)
(T
A
= -40
C to + 85
C, V
DD
= 2.2 V to 5.5 V)
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
|V
DD
COMi|
voltage drop (I=0-16)
V
DC
V
DD
= 2.7 to 5.5 V
-15 uA per common pin
LCNST = 00000000b
120
mV
|V
DD
SEGi|
voltage drop (I=0-55)
V
DS
V
DD
= 2.7 to 5.5 V
-15 uA per segment pin
LCNST =
00000000b
120
mV
LCD voltage
dividing resistor
R
LCD1
V
LCD
= 2.7 to 5.5 V; LCON.3 = 0
40
55
70
K
R
LCD2
V
LCD
= 2.7 to 5.5 V; LCON.3 = 1
20
28
35
Total contrast
resistor
R
CNST
V
LCD
= 2.7 to 5.5 V;
LCNST = 10000000b
140
VLC Output voltage
V
LC1
V
LCD
= 2.7 to 5.5 V
VDD-0.2
VDD
VDD+0.2
V
V
LC2
LCD clock = 0 Hz
0.8VDD-0.2
0.8 VDD
0.8VDD+0.2
V
LC3
LCNST = 00000000b
0.6VDD-0.2
0.6 VDD
0.6VDD+0.2
V
LC4
0.4VDD-0.2
0.4 VDD
0.4VDD+0.2
V
LC5
0.2VDD-0.2
0.2 VDD
0.2VDD+0.2
Supply current
(1)
I
DD1
Run mode; V
DD
= 5 V
10%
6 MHz crystal oscillator
4
8
mA
4 MHz crystal oscillator
2.7
5.4
V
DD
= 3 V
10%
6 MHz crystal oscillator
2
4
mA
4 MHz crystal oscillator
1.3
2.6
I
DD2
Idle mode: V
DD
= 5 V
10 %
6 MHz crystal oscillator
1.2
2.5
mA
4 MHz crystal oscillator
1.0
2.0
Idle mode: V
DD
= 3 V
10 %
6 MHz crystal oscillator
0.5
1.5
mA
4 MHz crystal oscillator
0.4
1.0
I
DD3
Sub-run mode; V
DD
= 3 V
10 %
Main stop, 32 kHz sub-osc.
17
34
uA
I
DD4
Sub-idle mode; V
DD
= 3 V
10 %
Main stop, 32 kHz
4.8
10
uA
I
DD5
Stop mode ; V
DD
= 5 V
10 %
0.2
3
uA
V
DD
= 3 V
10 %
0.1
2
NOTE: Supply current does not include current drawn through internal pull-up resistors or external output current loads and
ADC, DAC, BLD, LCD voltage dividing resistor.
ELECTRICAL DATA
S3CB519/FB519
22-4
Table 22-3. A.C. Electrical Characteristics
(T
A
= -40
C to + 85
C, V
DD
= 2.2 V to 5.5 V)
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
Interrupt input high,
low width
t
INTH
,
t
INTL
P0, P1
V
DD
= 5 V
200
ns
RESET
input
low width
t
RSL
V
DD
= 5 V
10 %
5
us
NOTE: User must keep a larger value than the min value.
t
INTH
t
INTL
0.8 V
DD
0.2 V
DD
Figure 22-1. Input Timing for External Interrupts (Port 0, Port 1)
RESET
t
RSL
0.2 V
DD
Figure 22-2. Input Timing for
RESET
RESET
S3CB519/FB519
ELECTRICAL DATA
22-5
Table 22-4. Data Retention Supply Voltage in Stop Mode
(T
A
= -40
C to + 85
C)
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
Data retention
supply voltage
V
DDDR
2.2
5.5
V
Data retention
supply current
I
DDDR
V
DDDR
= 2.2 V
2
uA
Execution of
STOP Instruction
RESET
Occur
~ ~
V
DDDR
~ ~
Stop Mode
Normal
Operating Mode
Data Retention Mode
t
WAIT
RESET
V
DD
NOTE: t
WAIT
is same as 2048 x 32 x 1/fxx
Oscillation
Stabilization Time
0.2V
DD
Figure 22-3. Stop Mode Release Timing When Initiated by a
RESET
RESET
ELECTRICAL DATA
S3CB519/FB519
22-6
Execution of
STOP Instruction
V
DDDR
~ ~
Data Retention
V
DD
Normal
Operating
Mode
~ ~
Stop Mode
OSC Start
up time
t
WAIT
NOTE:
t
WAIT
is same as 2048 x 32 x 1/fxx. The value of 2048 which is selected for the clock
source of the basic timer can be changed. And then the value of t
WAIT
will be changed.
Oscillation
Stabilization Time
0.2 V
DD
INT
Figure 22-4. Stop Mode (Main) Release Timing Initiated by Interrupts
Execution of
STOP Instruction
V
DDDR
~ ~
Data Retention
V
DD
Normal
Operating
Mode
~ ~
Stop Mode
OSC Start
up time
t
WAIT
NOTE:
t
WAIT
is same as 256 x 32 x 1/fxx. The oscillator strat up time is less than
100 ms. The value of 256 which is selected for the clock source of basic timer
must be kept within this value.
Oscillation
Stabilization Time
0.2 V
DD
INT
Figure 22-5. Stop Mode (Sub) Release Timing Initiated by Interrupts
S3CB519/FB519
ELECTRICAL DATA
22-7
Table 22-5. Synchronous SIO Electrical Characteristics
(T
A
= -40
C to + 85
C V
DD
= 4.5 V to 5.5 V, V
SS
= 0 V, fxx = 10 MHz oscillator )
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
SCK Cycle time
t
CYC
200
ns
Serial Clock High Width
t
SCKH
60
Serial Clock Low Width
t
SCKL
60
Serial Output data delay
time
t
OD
50
Serial Input data setup
time
t
ID
40
Serial Input data Hold
time
t
IH
100
Output Data
Input Data
SCK
t
SCKH
t
CYC
t
SCKL
0.8 V
DD
0.2 V
DD
t
OD
t
ID
t
IH
0.8 V
DD
0.2 V
DD
SI
SO
Figure 22-6. Serial Data Transfer Timing
ELECTRICAL DATA
S3CB519/FB519
22-8
Table 22-6. BLD Electrical Characteristics
(T
A
= 25
C, V
DD
= 2.2 V to 5.5 V, V
SS
= 0 V)
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
BLD Voltage
VB0
Internal V
DD
mode
Typ-0.15
2.4
Typ+0.15
V
VB1
2.7
VB2
3.0
VB3
3.3
VB4
Typ-0.3
4.0
Typ+0.3
VB5
4.5
VB6
External Input mode,
V
DD
= 2.2 V3.0 V
Typ-0.15
1.2
Typ+0.15
VB7
External Input mode,
V
DD
= 3.0 V5.5 V
Typ-0.3
1.2
Typ+0.3
BLD Current
IBLD
V
DD
= 5.5 V
50
100
uA
BLD Response
TB
V
DD
= 5.5 V
1/fw
(note)
us
NOTE: The fw must be greater than 10
sec.
Table 22-7. ADC Electrical Characteristics
(T
A
= -40
C to + 85
C, V
DD
= 3.0 V to 5.5 V, V
SS
= 0 V)
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
ADC Current
IADC
V
DD
= 3.3 V
1.5
3
mA
Sampling Frequency
8
11
kHz
Resolution
Measurement Bandwidth: 20 Hz4 kHz,
Full scale input sine wave: 1 kHz,
Sampling frequency: 8 kHz
14
bits
Signal to Distortion
ratio
70
75
dB
Offset Error
20
mV
Input Voltage Range
V
DD
= 3.3 V
2
V
PP
NOTE: All the data in this ADC characteristics is measured in the condition of V
DD
= 3.3 V
S3CB519/FB519
ELECTRICAL DATA
22-9
Table 22-8. DAC Electrical Characteristics
(T
A
= -40
C to + 85
C, V
DD
= 2.4 V to 5.5 V, V
SS
= 0 V)
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
DAC Current
IDAC
V
DD
= 5.5 V
1.5
3.0
mA
Resolution
8
bits
Absolute Accuracy
-3
3
LSB
Differential Linearity Error
DLE
-1.5
1.5
LSB
Output Delay
250
us
Output Load Resistance
Ro
10
k
Output Level
(peak to peak)
T
A
= -30
C to + 60
C
1.2
1.5
1.88
V
PP
Regulator Bias voltage
V
DD
= 3.3 V
V
DD
/2
V
Output Interval
OSC = 4.096 MHz;
AD/DA clock input = 8 kHz
31
us
ELECTRICAL DATA
S3CB519/FB519
22-10
Table 22-9. Main Oscillator Frequency (f
OSC
1)
(T
A
= -40
C to + 85
C V
DD
= 2.2 V to 5.5 V)
Oscillator
Clock Circuit
Test Condition
Min
Typ
Max
Unit
Crystal/Ceramic
X
IN
C1
C2
X
OUT
V
DD
= 2.2 V5.5 V
0.4
4.1
MHz
V
DD
= 2.4 V5.5 V
6.2
V
DD
= 3.0 V5.5 V
8.2
External clock
X
IN
X
OUT
V
DD
= 2.2 V5.5 V
0.4
4.1
MHz
V
DD
= 2.4 V5.5 V
6.2
V
DD
= 3.0 V5.5 V
8.2
RC
X
IN
X
OUT
R = 20 Kohm, V
DD
= 5 V
2
MHz
NOTE: Oscillation frequency and Xin input frequency data are for oscillator characteristics only.
Table 22-10. Main Oscillator Clock Stabilization Time (T
ST1
)
(T
A
= -40
C + 85
C, V
DD
= 4.5 V to 5.5 V)
Oscillator
Test Condition
Min
Typ
Max
Unit
Crystal
V
DD
= 4.5 V to 5.5 V
10
ms
Ceramic
Stabilization occurs when V
DD
is equal to the minimum
oscillator voltage range.
V
DD
= 4.5 V to 5.5 V
4
ms
External clock
X
IN
input high and low level width (t
XH
, t
XL
)
50
ns
NOTE: Oscillation stabilization time (T
ST1
) is the time required for the CPU clock to return to its normal oscillation
frequency after a power-on occurs, or when Stop mode is ended by a
RESET
signal.
S3CB519/FB519
ELECTRICAL DATA
22-11
X
IN
t
XH
t
XL
1/fosc1
V
DD
- 0.1 V
0.1 V
Figure 22-7. Clock Timing Measurement at X
IN
Table 22-11. Sub Oscillator Frequency (f
OSC2
)
(T
A
= -40
C + 85
C, V
DD
= 2.2 V to 5.5 V)
Oscillator
Clock Circuit
Test Condition
Min
Typ
Max
Unit
Crystal
C1
C2
XT
IN
XT
OUT
R
Crystal oscillation frequency
C1 = 22 pF, C2 = 33 pF
R = 39 K
XT
IN
and XT
OUT
are connected
with R and C by soldering.
32
32.768
35
kHz
NOTE: Oscillation frequency and XTin input frequency data are for oscillator characteristics only.
Table 22-12. Sub Oscillator (Crystal) Start up Time (t
ST2
)
(T
A
= -40
C + 85
C, V
DD
= 2.2 V to 5.5 V)
Oscillator
Test Condition
Min
Typ
Max
Unit
Normal mode
V
DD
= 4.5 V to 5.5 V
1
2
sec
V
DD
= 2.2 V to 4.5 V
10
Strong mode
V
DD
= 3.0 V to 5.5 V
6
V
DD
= 2.2 V to 3.0 V
2
NOTE: Oscillation stabilization time (t
ST2
) is the time required for the oscillator to it's normal oscillation when stop mode is
released by interrupts.
ELECTRICAL DATA
S3CB519/FB519
22-12
20 MHz
fxx
4 MHz
0.4 MHz
1
2
3
4
5
6
7
Supply Voltage (V)
Minimum instruction clock = 1/(1 x oscillator frequency)
A = 2.4 V: 6.2 MHz
B = 3.0 V: 8.2 MHz
C = 4.0 V: 10.24 MHz
6 MHz
8 MHz
12 MHz
A
B
C
10 MHz
Figure 22-8. Operating Voltage Range
S3CB519/FB519
MECHANICAL DATA
23-1
23
MECHANICAL DATA
OVERVIEW
The S3CB519/FB519 microcontroller is currently available in a 100-pin QFP package.
MECHANICAL DATA
S3CB519/FB519
23-2
100-QFP-1420C
#100
20.00
0.20
23.90
0.30
14.00
0.20
17.90
0.30
0.15
+ 0.10
- 0.05
0-8
0.10 MAX
#1
0.65
NOTE: Dimensions are in millimeters.
(0.58)
0.80
0.20
0.05 MIN
2.65
0.10
3.00 MAX
0.80
0.20
0.30
+ 0.10
- 0.05
(0.83)
0.15 MAX
0.10 MAX
Figure 23-1. 100-QFP-1420C Package Dimensions
S3CB519/FB519
S3FB519
24-1
24
S3FB519
OVERVIEW
The S3FB519 single-chip CMOS microcontroller is the FLASH version of the S3CB519 microcontroller.
It has an on-chip FLASH ROM instead of masked ROM. The FLASH ROM is accessed by serial data format.
The S3FB519 is fully compatible with the S3CB519, both in function and in pin configuration. Because of its
simple programming requirements, the S3FB519 is ideal for use as an evaluation chip for the S3CB519.
S3CB519/FB519
S3FB519
24-2
COM8/P4.0
COM7
COM6
COM5
COM4
COM3
COM2
COM1
COM0
SEG0
SEG1
SEG2
SEG3
SEG4
SEG5
SEG6
SEG7
SEG8
SEG9
SEG10
REFL
P1.0/KS0
P1.1/KS1
P1.2/KS2
P1.3/KS3
P2.0/SEG55
P2.1/SEG54
P2.2/SEG53
P2.3/SEG52
P2.4/SEG51
P2.5/SEG50
P2.6/SEG49
P2.7/SEG48
P3.0/SEG47
P3.1/SEG46
P3.2/SEG45
P3.3/SEG44
P3.4/SEG43
P3.5/SEG42
P3.6/SEG41
SEG11
SEG12
SEG13
SEG14
SEG15
SEG16
SEG17
SEG18
SEG19
SEG20
SEG21
SEG22
SEG23
SEG24/P5.15
SEG25/P5.14
SEG26/P5.13
SEG27/P5.12
SEG28/P5.11
SEG29/P5.10
SEG30/P5.9
SEG31/P5.8
SEG32/P5.7
SEG33/P5.6
SEG34/P5.5
SEG35/P5.4
SEG36/P5.3
SEG37/P5.2
SEG38/P5.1
SEG39/P5.0
SEG40/P3.7
COM9/P4.1
COM10/P4.2
COM11/P4.3
COM12/P4.4
COM13/P4.5
COM14/P4.6
COM15/P4.7
P0.0/INT0/TB
P0.1/INT1/T0/T0CAP/T0PWM
P0.2/INT2/T0CK/BUZ
P0.3/INT3/TACK/BLD
P0.4/INT4/
SCK
SDAT/P0.5/INT5/SO
SCLK/P0.6/INT6/SI
V
DD
/V
DD
V
SS
/V
SS
X
OUT
X
IN
V
PP
/TEST
XT
IN
XT
OUT
RESET
DAOUT
AV
DD
AV
SS
ADINP
ADINN
ADGAIN
AVREFOUT
REFH
S3FB519
(100-QFP-1420C)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
Figure 24-1. S3FB519 Pin Assignments (100-QFP)
S3CB519/FB519
S3FB519
24-3
Table 24-1. Descriptions of Pins Used to Read/Write the FLASH ROM
Main Chip
During Programming
Pin Name
Pin Name
Pin No.
I/O
Function
P0.5
SDAT
13
I/O
Serial data pin. Output port when reading and input
port when writing. Can be assigned as a Input/push-
pull output port.
P0.6
SCLK
14
I/O
Serial clock pin. Input only pin.
TEST
V
PP
(TEST)
19
I
Power supply pin for FLASH ROM cell writing
(indicates that FLASH enters into the writing mode).
When 12.5 V is applied, FLASH is in writing mode
and when 5 V is applied, FLASH is in reading
mode. When FLASH is operating, hold GND.
RESET
RESET
22
I
Chip initialization
V
DD
/V
SS
V
DD
/V
SS
15/16
I
Logic power supply pin. V
DD
should be tied to
+5 V during programming.
NOTE: Pin No. is for 100-QFP type package.
Table 24-2. Comparison of S3FB519 and S3CB519 Features
Characteristic
S3FB519
S3CB519
Program Memory
32-Kbyte FLASH ROM
32-Kbyte mask ROM
Operating Voltage (V
DD
)
2.2 V to 5.5 V
2.2 V to 5.5 V
FLASH Programming Mode
V
DD
= 5 V, V
PP
(TEST) = 12.5V
Pin Configuration
100-QFP
100-QFP
FLASH ROM Programmability User program
Programmed at the factory
S3CB519/FB519
S3FB519
24-4
NOTES
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