DRAM MODULE

KMM5368105CK/CKG

KMM5368005CK/CKG

KMM5368005CK/CKG & KMM5368105CK/CKG Fast Page Mode with EDO Mode
8M x 36 DRAM SIMM using 4Mx4 and 16M Quad CAS, 4K/2K Refresh, 5V

The Samsung KMM53680(1)05CK is a 8Mx36bits Dynamic
RAM high density memory module. The Samsung
KMM53680(1)05CK consists of sixteen CMOS 4Mx4bits
DRAMs in 24-pin SOJ package and two CMOS 4Mx4 bit Quad
CAS with EDO DRAM in 28-pin SOJ package mounted on a
72-pin glass-epoxy substrate. A 0.1 or 0.22uF decoupling
capacitor is mounted on the printed circuit board for each
DRAM. The KMM53680(1)05CK is a Single In-line Memory
Module with edge connections and is intended for mounting
into 72 pin edge connector sockets.

· Part Identification
- KMM5368005CK(4096 cycles/64ms Ref, SOJ, Solder)
- KMM5368005CKG(4096 cycles/64ms Ref, SOJ, Gold)
- KMM5368105CK(2048 cycles/32ms Ref, SOJ, Solder)
- KMM5368105CKG(2048 cycles/32ms Ref, SOJ, Gold)
· Fast Page Mode with Extended Data Out
· CAS-before-RAS refresh capability
· RAS-only and Hidden refresh capability
· TTL compatible inputs and outputs
· Single +5V

10% power supply

· JEDEC standard PDPin & pinout
· PCB : Height(1000mil), double sided component

GENERAL DESCRIPTION

FEATURES

PERFORMANCE RANGE

Speed

RAC

CAC

HPC

-5

50ns

13ns

90ns

25ns

-6

60ns

15ns

110ns

30ns

PIN NAMES

Pin Name

Function

A0 - A11

Address Inputs(4K Ref)

A0 - A10

Address Inputs(2K Ref)

DQ0 - DQ35

Data In/Out

Read/Write Enable

RAS0, RAS1

Row Address Strobe

CAS0 - CAS3

Column Address Strobe

PD1 -PD4

Presence Detect

Vcc

Power(+5V)

Vss

Ground

No Connection

PRESENCE DETECT PINS (Optional)

* Pin connection changing available

Pin

50NS

60NS

PD1
PD2
PD3
PD4

Vss
Vss
Vss

Vss
Vss

NC
NC

PIN CONFIGURATIONS

Pin

Symbol

DQ0

DQ18

DQ1

DQ19

DQ2

DQ20

DQ3

DQ21

Vcc

A10

DQ4

DQ22

DQ5

DQ23

DQ6

DQ24

DQ7

DQ25

A11

Vcc

RAS1

RAS0

DQ26

DQ8

Pin

Symbol

DQ17

DQ35

Vss

CAS0

CAS2

CAS3

CAS1

RAS0

RAS1

DQ9

DQ27

DQ10

DQ28

DQ11

DQ29

DQ12

DQ30

DQ13

DQ31

Vcc

DQ32

DQ14

DQ33

DQ15

DQ34

DQ16

PD1

PD2

PD3

PD4

Vss

* NOTE : A11 is used for only KMM5368005CK/CKG (4K ref.)

SAMSUNG ELECTRONICS CO., LTD. reserves the right to
change products and specifications without notice.

DRAM MODULE

KMM5368105CK/CKG

KMM5368005CK/CKG

FUNCTIONAL BLOCK DIAGRAM

DQ0
DQ1
DQ2
DQ3

CAS
RAS
OE

A0-

Vcc

Vss

.1 or .22uF Capacitor

for each DRAM

To all DRAMs

A11(A10)

DQ0
DQ1
DQ2
DQ3

CAS
RAS

A0-

A11(A10)

DQ0
DQ1
DQ2
DQ3

CAS
RAS
OE

A0-

A11(A10)

DQ0
DQ1
DQ2
DQ3

CAS
RAS

A0-

A11(A10)

DQ0
DQ1
DQ2
DQ3

CAS
RAS
OE

A0-

A11(A10)

DQ0
DQ1
DQ2
DQ3

CAS
RAS

A0-

A11(A10)

DQ0
DQ1
DQ2
DQ3

CAS
RAS
OE

A0-

A11(A10)

DQ0
DQ1
DQ2
DQ3

CAS
RAS

A0-

A11(A10)

DQ0
DQ1
DQ2
DQ3

CAS
RAS
OE

A0-

A11(A10)

DQ0
DQ1
DQ2
DQ3

CAS
RAS

A0-

A11(A10)

DQ0
DQ1
DQ2
DQ3

CAS
RAS
OE

A0-

A11(A10)

DQ0
DQ1
DQ2
DQ3

CAS
RAS

A0-

A11(A10)

DQ0
DQ1
DQ2
DQ3

CAS
RAS
OE

A0-

A11(A10)

DQ0
DQ1
DQ2
DQ3

CAS
RAS

A0-

A11(A10)

DQ0
DQ1
DQ2
DQ3

CAS
RAS
OE

A0-

A11(A10)

DQ0
DQ1
DQ2
DQ3

CAS
RAS

A0-

A11(A10)

CAS0
CAS1
CAS2
CAS3
RAS
OE W

A0-

A11(A10)

A0-

A11(A10)

CAS0
CAS1
CAS2
CAS3

RAS

A0-A11(A10)

DQ0
DQ1
DQ2
DQ3

DQ8

DQ17
DQ26
DQ35

CAS0
RAS1

CAS1

CAS2

CAS3

CAS1

CAS2

CAS3

CAS0
RAS0

U10

U11

U12

U13

U14

U15

U16

U17

DQ0-DQ3

DQ4-DQ7

DQ9-DQ12

DQ13-DQ16

DQ18-DQ21

DQ22-DQ25

DQ27-DQ30

DQ31-DQ34

DRAM MODULE

KMM5368105CK/CKG

KMM5368005CK/CKG

CC1

, I

CC3

, I

CC4

and I

CC6

are dependent on output loading and cycle rates. Specified values are obtained with the output open.

is specified as an average current. In I

CC1

and I

CC3

, address can be changed maximum once while RAS=V

. In I

CC4

address can be changed maximum once within one EDO mode cycle,

HPC

* NOTE :

ABSOLUTE MAXIMUM RATINGS *

* Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to

the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for intended
periods may affect device reliability.

Item

Symbol

Rating

Unit

Voltage on any pin relative to V

Voltage on V

supply relative to V

Storage Temperature
Power Dissipation
Short Circuit Output Current

, V

OUT

stg

-1 to +7.0
-1 to +7.0

-55 to +150

18
50

V
V

RECOMMENDED OPERATING CONDITIONS

(Voltage referenced to V

, T

= 0 to 70

*1 : V

+2.0V/20ns, Pulse width is measured at V

*2 : -2.0V/20ns, Pulse width is measured at V

Item

Symbol

Min

Typ

Max

Unit

Supply Voltage
Ground
Input High Voltage
Input Low Voltage

4.5

2.4

-1.0

5.0

-
-

5.5

0.8

V
V
V
V

DC AND OPERATING CHARACTERISTICS

(Recommended operating conditions unless otherwise noted)

CC1

CC2

CC3

CC4

CC5

CC6

I(L)

O(L)

Symbol

Speed

KMM5368005CK/CKG

KMM5368105CK/CKG

Unit

Min

Max

Min

Max

CC1

-5
-6

-
-

828
738

-
-

1008

918

mA
mA

CC2

Don

t care

CC3

-5
-6

-
-

828
738

-
-

1008

918

mA
mA

CC4

-5
-6

-
-

738
648

-
-

828
738

mA
mA

CC5

Don

t care

CC6

-5
-6

-
-

828
738

-
-

1008

918

mA
mA

I(L)

O(L)

Don

t care

-90
-10

90
10

-90
-10

90
10

uA
uA

Don

t care

2.4

0.4

2.4

0.4

V
V

: Operating Current * (RAS, CAS, Address cycling @

=min)

: Standby Current (RAS=CAS=W=V

)

: RAS Only Refresh Current * (CAS=V

, RAS cycling @

=min)

: EDO Mode Current * (RAS=V

, CAS Address cycling :

HPC

=min)

: Standby Current (RAS=CAS=W=Vcc-0.2V)
: CAS-Before-RAS Refresh Current * (RAS and CAS cycling @

=min)

: Input Leakage Current (Any input 0

Vcc+0.5V, all other pins not under test=0 V)

: Output Leakage Current(Data Out is disabled, 0V

OUT

Vcc)

: Output High Voltage Level (I

= -5mA)

: Output Low Voltage Level (I

= 4.2mA)

DRAM MODULE

KMM5368105CK/CKG

KMM5368005CK/CKG

CAPACITANCE

= 25

C, V

=5V, f = 1MHz)

Item

Symbol

Min

Max

Unit

Input capacitance[A0-A11(A10)]
Input capacitance[W]
Input capacitance[RAS0, RAS1]
Input capacitance[CAS0 - CAS3]
Input/Output capacitance[DQ0-35]

IN1

IN2

IN3

IN4

DQ1

-
-
-
-
-

110
130

80
40
25

pF
pF
pF
pF
pF

Test condition : V

=2.4/0.8V, V

=2.0/0.8V, Output loading CL=100pF

Parameter

Symbol

-5

-6

Unit

Note

Min

Max

Min

Max

Random read or write cycle time

110

Access time from RAS

RAC

3,4,10

Access time from CAS

CAC

3,4,5

Access time from column address

3,10

CAS to output in Low-Z

CLZ

Output buffer turn-off delay from CAS

CEZ

6,11,12

Transition time(rise and fall)

RAS precharge time

RAS pulse width

RAS

10K

RAS hold time

RSH

CAS hold time

CSH

CAS pulse width

CAS

10K

RAS to CAS delay time

RCD

RAS to column address delay time

RAD

CAS to RAS precharge time

CRP

Row address set-up time

ASR

Row address hold time

RAH

Column address set-up time

ASC

Column address hold time

CAH

Column address to RAS lead time

RAL

Read command set-up time

RCS

Read command hold time referenced to CAS

RCH

Read command hold time referenced to RAS

RRH

Write command hold time

WCH

Write command pulse width

Write command to RAS lead time

RWL

Write command to CAS lead time

CWL

Data-in set-up time

Data-in hold time

Refresh period (4K Ref)

REF

Refresh period (2K Ref)

REF

Write command set-up time

WCS

CAS setup time(CAS-before-RAS refresh)

CSR

CAS hold time(CAS-before-RAS refresh)

CHR

RAS to CAS precharge time

RPC

AC CHARACTERISTICS

C, V

=5.0V

10%. See notes 1,2.)

DRAM MODULE

KMM5368105CK/CKG

KMM5368005CK/CKG

NOTES

An initial pause of 200us is required after power-up followed
by any 8 RAS-only or CAS-before-RAS refresh cycles before
proper device operation is achieved.

(min) and V

(max) are reference levels for measuring

timing of input signals. Transition times are measured
between V

(min) and V

(max) and are assumed to be 5ns

for all inputs.

Measured with a load equivalent to 2 TTL loads and 100pF.

Operation within the

RCD

(max) limit insures that

RAC

(max)

can be met.

RCD

(max) is specified as a reference point only.

RCD

is greater than the specified

RCD

(max) limit, then

access time is controlled exclusively by

CAC

Assumes that

RCD

(max).

This parameter defines the time at which the output achieves
the open circuit condition and is not referenced to V

WCS

is non-restrictive operating parameter. It is included in

the data sheet as electrical characteristics only. If

WCS

(min), the cycle is an early write cycle and the data

out pin will remain high impedance for the duration of the
cycle.

Either

RCH

RRH

must be satisfied for a read cycle.

These parameter are referenced to the CAS leading edge in
early write cycles and to the W leading edge in read-write
cycles.

Operation within the

RAD

(max) limit insures that

RAC

(max)

can be met.

RAD

(max) is specified as reference point only. If

RAD

is greater than the specified

RAD

(max) limit, then

access time is controlled by

CEZ

(max),

REZ

(max),

WEZ

(max) and

OEZ

(max) define the

time at which the output achieves the open circuit condition
and are not referenced to output voltage level.

If RAS goes to high before CAS high going, the open circuit
condtion of the output is achieved by CAS high going. If CAS
goes to high before RAS high going, the open circuit condtion
of the output is achieved by RAS high going.

ASC

min

In order to hold the address latched by the first CAS going
low, the parameter

CLCH

must be met.

10.

Test condition : V

=2.4/0.8V, V

=2.0/0.8V, Output loading CL=100pF

Parameter

Symbol

-5

-6

Unit

Note

Min

Max

Min

Max

CAS precharge time (C-B-R counter test cycle)

CPT

Access time from CAS precharge

CPA

Hyper page mode cycle time

HPC

CAS precharge time(Hyper page cycle)

RAS pulse width(Hyper page cycle)

RASP

200K

RAS hold time from CAS precharge

RHCP

W to RAS precharge time(C-B-R refresh)

WRP

W to RAS hold time(C-B-R refresh)

WRH

Output data hold time

DOH

Output buffer turn off delay from RAS

REZ

6,11,12

Output buffer turn off delay from W

WEZ

6,11

W to data delay

WED

W pulse width (Hyper Page Cycle)

WPE

Hold time CAS low to CAS high

CLCH

AC CHARACTERISTICS

C, V

=5.0V

10%. See notes 1,2.)

11.

12.

13.

14.

DRAM MODULE

KMM5368105CK/CKG

KMM5368005CK/CKG

DOH

HYPER PAGE READ CYCLE

RAS

CAS

COLUMN

ADDRESS

ROW

ADDR

RASP

RCD

ASR

CRP

Don

t care

Undefined

COLUMN

ADDRESS

CAS

HPC

RHCP

CSH

RAD

RAH

ASC

CAH

ASC

CAH

RCS

RCH

ASC

COLUMN

ADDRESS

COLUMN

ADDR

VALID

DATA-OUT

CAC

CPA

VALID

DATA-OUT

VALID

DATA-OUT

CLZ

RAC

CAC

RRH

REZ

CAC

CPA

CAC

¡ó

ASC

DOH

VALID

DATA-OUT

DOH

DRAM MODULE

KMM5368105CK/CKG

KMM5368005CK/CKG

RAS

CAS

COLUMN

ADDRESS

ROW

ADDR.

RASP

RCD

ASR

CRP

Don

t care

HYPER PAGE WRITE CYCLE ( EARLY WRITE )

Undefined

RHCP

RAD

RAH

CAH

ASC

CAH

ASC

VALID

DATA-IN

¡ó

COLUMN

ADDRESS

COLUMN

ADDRESS

CAS

RSH

¡ó

CSH

ASC

¡ó

WCS

WCH

WCS

WCH

WCS

WCH

¡ó

VALID

DATA-IN

VALID

DATA-IN

¡ó

CWL

RWL

NOTE : D

OUT

= OPEN

HPC

DRAM MODULE

KMM5368105CK/CKG

KMM5368005CK/CKG

Don

t care

RAS - ONLY REFRESH CYCLE*

NOTE : W, OE, D

= Don't care

Undefined

OUT

= OPEN

RAS

CAS

ROW

ADDR

ASR

CRP

RAS

RAH

RPC

CRP

OPEN

CAS - BEFORE - RAS REFRESH CYCLE

NOTE : OE , A = Don't care

RAS

CAS

RAS

RPC

CSR

CHR

CEZ

WRP

WRH

* In RAS-only refresh cycle of 64Mb A-dile & B-die, when CAS signal transits from Low to High, the valid data may be cut off.

DRAM MODULE

KMM5368105CK/CKG

KMM5368005CK/CKG

CAS-BEFORE-RAS REFRESH COUNTER TEST CYCLE

RAS

CAS

COLUMN

ADDRESS

RAS

RSH

CHR

RAL

CSR

CPT

CAS

ASC

CAH

READ CYCLE

DATA-OUT

REZ

CLZ

WRITE CYCLE

DATA-IN

Don

t care

Undefined

WRP

WRH

RRH

RCH

RCS

CAC

WRP

WRH

WCS

WCH

CWL

RWL

NOTE : This timing diagram is applied to all devices besides 64M DRAM based modules.

CEZ

WEZ

DRAM MODULE

KMM5368105CK/CKG

KMM5368005CK/CKG

PACKAGE DIMENSIONS

.133(3.38)

4.250(107.95)

3.984(101.19)

.125(3.17)

R.062

.004(R1.57

.10)

.250(6.35)

3.750(95.25)

.250(6.35)

Units : Inches (millimeters)

Gold & Solder Plating Lead

.010(.25)MAX

.050(1.27)

.041

.004(1.04

.10)

.100(2.54)

MIN

.350(8.89)

MAX

.054(1.37)

Tolerances :

.005(.13) unless otherwise specified

NOTE : The used device are 4Mx4 EDO DRAM (SOJ & 300mil) & 4Mx4 Quad CAS with EDO DRAM (SOJ & 300mil)
DRAM Part No. : KMM5368005CK/CKG -- KM44C4004CK (300 mil) & KM44C4005CK (300mil)

1.00(25.40)

MIN

.400(10.16)

.125 DIA

.002(3.18

.051)

R.062(1.57)

.250(6.35)

.080(2.03)

.047(1.19)

( Back view )

( Front view )

KMM5368105CK/CKG -- KM44C4104CK (300 mil) & KM44C4105CK (300mil)

Revision History
Rev 0.0 : Aug. 1997

.225(5.71)

MIN

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