DRAM MODULE
KMM5321200C2W/C2WG
Rev. 0.0 (Nov. 1997)
- 3 -
KMM5321200C2W/C2WG with Fast Page Mode
1M x 32 DRAM SIMM using 1Mx16, 1K Refresh, 5V
The Samsung KMM5321200C2W is a 1Mx32bits Dynamic
RAM high density memory module. The Samsung
KMM5321200C2W consists of two CMOS 1Mx16bits DRAMs
in 42-pin SOJ packages mounted on a 72-pin glass-epoxy
substrate. A 0.1 or 0.22uF decoupling capacitor is mounted
on the printed circuit board for each DRAM. The
KMM5321200C2W is a Single In-line Memory Module with
edge connections and is intended for mounting into 72 pin
edge connector sockets.
Part Identification
- KMM5321200C2W(1024 cycles/16ms Ref, SOJ, Solder)
- KMM5321200C2WG(1024 cycles/16ms Ref, SOJ, Gold)
Fast Page Mode Operation
CAS-before-RAS refresh capability
RAS-only refresh capability
TTL compatible inputs and outputs
Single +5V
10% power supply
JEDEC standard PDPin & pinout
PCB : Height(750mil), single sided component
GENERAL DESCRIPTION
FEATURES
PERFORMANCE RANGE
Speed
t
RAC
t
CAC
t
RC
-5
50ns
15ns
90ns
-6
60ns
15ns
110ns
PIN NAMES
Pin Name
Function
A0 - A9
Address Inputs
DQ0 - DQ31
Data In/Out
W
Read/Write Enable
RAS0
Row Address Strobe
CAS0 - CAS3
Column Address Strobe
PD1 -PD4
Presence Detect
Vcc
Power(+5V)
Vss
Ground
NC
No Connection
Res
Reserved Pin
PRESENCE DETECT PINS (Optional)
* Pin connection changing available
Pin
50NS
60NS
PD1
PD2
PD3
PD4
Vss
Vss
Vss
Vss
Vss
Vss
NC
NC
PIN CONFIGURATIONS
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
Symbol
V
SS
DQ0
DQ16
DQ1
DQ17
DQ2
DQ18
DQ3
DQ19
Vcc
NC
A0
A1
A2
A3
A4
A5
A6
Res(A10)
DQ4
DQ20
DQ5
DQ21
DQ6
DQ22
DQ7
DQ23
A7
Res(A11)
Vcc
A8
A9
Res(RAS1)
RAS0
NC
NC
Pin
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
Symbol
NC
NC
Vss
CAS0
CAS2
CAS3
CAS1
RAS0
Res(RAS1)
NC
W
NC
DQ8
DQ24
DQ9
DQ25
DQ10
DQ26
DQ11
DQ27
DQ12
DQ28
Vcc
DQ29
DQ13
DQ30
DQ14
DQ31
DQ15
NC
PD1
PD2
PD3
PD4
NC
Vss
SAMSUNG ELECTRONICS CO., LTD. reserves the right to
change products and specifications without notice.
DRAM MODULE
KMM5321200C2W/C2WG
Rev. 0.0 (Nov. 1997)
- 4 -
FUNCTIONAL BLOCK DIAGRAM
RAS0
W
A0-A9
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
RAS
LCAS
UCAS
OE
W
A0-A9
CAS0
CAS1
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
RAS
LCAS
UCAS
OE
CAS2
CAS3
Vcc
Vss
.1 or .22uF Capacitor
for each DRAM
To all DRAMs
U0
U1
W
A0-A9
DRAM MODULE
KMM5321200C2W/C2WG
Rev. 0.0 (Nov. 1997)
- 5 -
I
CC1
, I
CC3
, I
CC4
and I
CC6
are dependent on output loading and cycle rates. Specified values are obtained with the output open.
I
CC
is specified as an average current. In I
CC1
and I
CC3
, address can be changed maximum once while RAS=V
IL
. In I
CC4
,
address can be changed maximum once within one page mode cycle,
t
PC.
* NOTE :
ABSOLUTE MAXIMUM RATINGS *
* Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to
the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for in tended
periods may affect device reliability.
Item
Symbol
Rating
Unit
Voltage on any pin relative to V
SS
Voltage on V
CC
supply relative to V
SS
Storage Temperature
Power Dissipation
Short Circuit Output Current
V
IN
, V
OUT
V
CC
T
stg
P
d
I
OS
-1 to +7.0
-1 to +7.0
-55 to +150
2
50
V
V
C
W
mA
RECOMMENDED OPERATING CONDITIONS
(Voltage referenced to V
SS
, T
A
= 0 to 70
C)
*1 : V
CC
+2.0V/20ns, Pulse width is measured at V
CC
.
*2 : -2.0V/20ns, Pulse width is measured at V
SS
.
Item
Symbol
Min
Typ
Max
Unit
Supply Voltage
Ground
Input High Voltage
Input Low Voltage
V
CC
V
SS
V
IH
V
IL
4.5
0
2.4
-1.0
*2
5.0
0
-
-
5.5
0
V
CC
+1
*1
0.8
V
V
V
V
DC AND OPERATING CHARACTERISTICS
(Recommended operating conditions unless otherwise noted)
I
CC1
I
CC2
I
CC3
I
CC4
I
CC5
I
CC6
I
I(L)
I
O(L)
V
OH
V
OL
Symbol
Speed
KMM5321200C2W/C2WG
Unit
Min
Max
I
CC1
-5
-6
-
-
300
280
mA
mA
I
CC2
Don
t care
-
4
mA
I
CC3
-5
-6
-
-
300
280
mA
mA
I
CC4
-5
-6
-
-
180
160
mA
mA
I
CC5
Don
t care
-
2
mA
I
CC6
-5
-6
-
-
300
280
mA
mA
I
I(L)
I
O(L)
Don
t care
-10
-5
10
5
uA
uA
V
OH
V
OL
Don
t care
2.4
-
-
0.4
V
V
: Operating Current * ( RAS, LCAS or UCAS, Address cycling @
t
RC
=min)
: Standby Current ( RAS=LCAS=UCAS=W=V
IH
)
: RAS Only Refresh Current * ( LCAS=UCAS=V
IH
, RAS cycling @
t
RC
=min)
: Fast Page Mode Current * ( RAS=V
IL
, LCAS or UCAS cycling :
t
PC
=min)
: Standby Current ( RAS=LCAS=UCAS=W=Vcc-0.2V)
: CAS-Before-RAS Refresh Current * ( RAS and CAS cycling @
t
RC
=min)
: Input Leakage Current (Any input 0
V
IN
Vcc+0.5V, all other pins not under test=0 V)
: Output Leakage Current(Data Out is disabled, 0V
V
OUT
Vcc)
: Output High Voltage Level (I
OH
= -5mA)
: Output Low Voltage Level (I
OL
= 4.2mA)
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