KC73129MP 1/3 INCH CCD IMAGE SENSOR FOR CCIR CAMERA
1
INTRODUCTION
The KC73129MP is an interline transfer CCD area
image sensor developed for CCIR 1/3 inch video
cameras. It can be used for door phones, surveillance
cameras, object detection and pattern recognition
FEATURES
High Sensitivity
Optical Size: 1/3 inch Format
Veriable Speed Electronic Shutter
(1/60, 1/100 ~ 1/10, 000sec)
Horizontal Register: 5V Drive
16pin Plastic DIP Package
Field Integration Read Out System
No DC Bias on Reset Gate
STRUCTURE
Number of Total Pixels:
537(H)
597(V)
Number of Effective Pixels:
500(H)
582(V)
Chip Size:
6.00mm(H)
5.10mm(V)
Unit Pixel Size:
9.80
m(H)
6.30
m(V)
Optical Blacks & Dummies:
Refer to Figure Below
Vertical 1 Line (Even Field Only)
16Pin PLASTIC-DIP
ORDERING INFORMATION
Device
Package
Operating
KC73129MP
16Pin PLASTIC-DIP
-10
C ~ +55
C
16 7
500
30
1
5
8
2
1
4
V
-
C
C
D
OUTPUT
Dummy Pixels
Optical Black Pixels
Effective Pixels
Effective
Imaging
Area
H-CCD
1/3 INCH CCD IMAGE SENSOR FOR CCIR CAMERA
KC73129MP
2
BLOCK DIAGRAM
PIN DESCRIPTION
Figure 1. Block Diagram
Table 1. Pin Description
Pin
Symbol
Description
Pin
Symbol
Description
1
V4
Vertical CCD transfer clock 4
9
V
OUT
Signal output
2
V3
Vertical CCD transfer clock 3
10
V
GG
Output AMP gate valtage
3
V2
Vertical CCD transfer clock 2
11
V
SS
Output AMP source valtage
4
SUB
Substrate voltage
12
GND
Ground
5
V1
Vertical CCD transfer clock 1
13
VRD
Reset drain voltage
6
V
L
Protection bias voltage
14
RG
Charge reset clock
7
GND
Ground
15
H1
Horizontal CCD transfer clock 1
8
V
DD
Output AMP drain voltage
16
H2
Horizontal CCD transfer clock 2
8
V
DD
7
6
5
4
3
2
1
9
10
11
12
13
14
15
16
GND
V
L
V1
V2
V3
V4
V
OUT
GND
V
GG
H1
H2
SUB
V
e
r
t
i
c
a
l
S
h
i
f
t
R
e
g
i
s
t
e
r
C
C
D
V
e
r
t
i
c
a
l
S
h
i
f
t
R
e
g
i
s
t
e
r
C
C
D
V
e
r
t
i
c
a
l
S
h
i
f
t
R
e
g
i
s
t
e
r
C
C
D
V
e
r
t
i
c
a
l
S
h
i
f
t
R
e
g
i
s
t
e
r
C
C
D
Horizontal Shift Register CCD
RG
VRD
V
SS
(Top View)
KC73129MP 1/3 INCH CCD IMAGE SENSOR FOR CCIR CAMERA
3
ABSOLUTE MAXIMUM RATINGS
(NOTE)
NOTE: The device can be destroyed, if the applied voltage or temperature is higher than the absolute maximum rating voltage
or temperature.
Table 2. Absolute Maximum Ratings
Characteristics
Symbols
Min.
Max.
Unit
Substrate voltage
SUB - GND
-0.3
55
V
Supply voltage
V
DD
, V
OUT,
V
OUT
- GND
-0.3
17
V
Vertical clock input voltage
V1
,
V2
,
V3
,
V4
- GND
-10
20
V
V1
,
V2
,
V3
,
V4
- V
L
-0.3
30
V
Horizontal clock input voltage
H1
,
H2
- GND
-0.3
17
V
Voltage difference between vertical and
horizontal clock input pins
V1
,
V2
,
V3
,
V4
-0.3
15
V
H1
,
H2
-0.3
17
V
H1
,
H2
-
V4
-17
17
V
Output clock input voltage
RG,
GG
- GND
-0.3
15
V
Protection circuit bias voltage
V
L
- SUB
-65
0.3
V
Operating temperature
T
OPR
-10
55
C
Storage temperature
T
STG
-30
80
C
1/3 INCH CCD IMAGE SENSOR FOR CCIR CAMERA
KC73129MP
4
DC CHARACTERISTICS
CLOCK VOLTAGE CONDITIONS
Table 3. DC Characteristics
Item
Symbol
Min.
Typ.
Max.
Unit
Remark
Output amp drain voltage
V
DD
14.55
15.0
15.45
V
Output amp gate voltage
V
GG
1.75
2.0
2.25
V
Output amp source voltage
V
SS
Ground through 680
V
5%
Substrate voltage adjustment range
SUB
7.0
14.5
V
Fluctuation range after substrate
voltage adjusted
V
SUB
-3
3
%
Protection circuit bias voltage
V
L
V
VL
voltage of the vertical clock waveform
Output stage drain current
I
DD
2.5
mA
Table 4. Clock Voltage Conditions
Item
Symbol
Min.
Typ.
Max.
Unit
Remark
Read-out clock voltage
V
VT
14.55
15.0
15.45
V
High level
Vertical transfer clock voltage
V
VH1
~ V
VH4
-0.05
0.0
0.05
V
V
VH
= (V
VH1
+ V
VH2
)/2
V
VL1
~ V
VL4
-9.5
-9.0
-8.5
V
V
VL
= (V
VL3
+ V
VL4
)/2
Horizontal transfer clock voltage
V
H
4.75
5.0
5.25
V
High
V
HL
-0.05
0.0
0.05
V
Low
Charge reset clock voltage
V
RG
4.75
5.0
5.25
V
High
V
RGLH -
V
RGLL
0.8
V
Low
Substrate clock voltage
V
SUB
20.0
23.0
25.0
V
Shutter
KC73129MP 1/3 INCH CCD IMAGE SENSOR FOR CCIR CAMERA
5
DRIVE CLOCK WAVEFORM CONDITIONS
Read Out Clock Waveform
Vertical Transfer Clock Waveform
0V
100%
90%
10%
0%
V
VH 1,
V
VH3
tr
twh
tf
V
V H 1
V
VH
V
V H H
V
VL L
V
VL
V
VL 1
V
VL H
V
V H L
V
V H L
V
V H H
V 1
V
VH
V
VHL
V
VH H
V
V HH
V
VHL
V
VH 4
V
VL
V
VL H
V
VL L
V
V L 4
V 4
V
VH H
V
VHH
V
VH
V
VHL
V
VHL
V
VH2
V
VL
V
VL L
V
VL H
V
VL 2
V 2
V
VL 3
V
VHH
V
VL
V
V HL
V
VH L
V
VH3
V
VH H
V
VH
V
VL H
V
VL L
V 3
V
V H
= ( V
V H 1
+ V
V H 2
)/ 2
V
V L
= (V
V L 3
+ V
V L 4
)/ 2
V
V
= V
V H n
- V
V L n
(n =1~4)
V
V H H
= V
V H
+ 0 . 3 V
V
V H L
= V
V H
- 0 . 3 V
V
V L H
= V
V L
+ 0 . 3 V
V
V L L
= V
V L
- 0 . 3 V
PDF 
ZIP