K4S643233E-SE/N
CMOS SDRAM
- 1 -
Rev. 1.5 April 2002
Revision 1.5
April 2002
Samsung Electronics reserves the right to change products or specification without notice.
2M x 32 SDRAM
512K x 32bit x 4 Banks
Synchronous DRAM
LVTTL(3.0V & 3.3V)
Extended Temperature
90-Ball FBGA
K4S643233E-SE/N
CMOS SDRAM
- 2 -
Rev. 1.5 April 2002
Revision 1.5 (April 19, 2002) -
Final
Erased TSOP specification.
Revision 1.4 (November 15, 2001) -
Final
Final specification for 2Mx32 SDRAM.
Revision 1.3 (October 10, 2001) -
Preliminary
Integrated 3.0V part numbr(K4S643234E-S(T)E(N)) and 3.3V part number(K4S643232E-S(T)E(N)) to 3.0V & 3.3V part-
number(K4S643233E-S(T)E(N)).
Deleted tCC 5ns part and 6ns part.
Unification of tCH 3ns for -70 part and tCH 3ns for -80 part, tCH 3ns for -10 part.
Unification of tCL 3ns for -70 part and tCL 3ns for -80 part, tCL 3ns for -10 part.
Unification of tSS 1.75ns for -70 part and tSS 2ns for -80 part, tSS 2.5ns for -10 part.
Changed tCDL form 2clk to 1clk and tRDL for CL1 from 1clk to 2clk.
Revision 1.2 (August 7, 2001) -
Target
Added CAS Latency 1
Revision 1.1 (July 6, 2001)
Added K4S643232E-T/S(E/N)50
Revision 1.0 (April 6, 2001)
Revision 0.0 (March 21, 2001)
Initial draft
Extended temperature (-25
c ~ 85
c )
3.3V Power supply (VDD &VDDQ)
Supported 90-ball FBGA as well as 86 - TSOP
Revision History
K4S643233E-SE/N
CMOS SDRAM
- 3 -
Rev. 1.5 April 2002
The K4S643233E is 67,108,864 bits synchronous high data
rate Dynamic RAM organized as 4 x 524,288 words by 32 bits,
fabricated with SAMSUNG
s high performance CMOS technol-
ogy. Synchronous design allows precise cycle control with the
use of system clock and I/O transactions are possible on every
clock cycle. Range of operating frequencies, programmable
burst length and programmable latencies allow the same device
to be useful for a variety of high bandwidth, high performance
memory system applications.
3.0V & 3.3V power supply
LVTTL compatible with multiplexed address
Four banks operation
MRS cycle with address key programs
-. CAS latency (1 & 2 & 3)
-. Burst length (1, 2, 4, 8 & Full page)
-. Burst type (Sequential & Interleave)
All inputs are sampled at the positive going edge of the system
clock
Burst read single-bit write operation
DQM for masking
Auto & self refresh
64ms refresh period (4K cycle).
Extended Temperature range : -25
o
C to +85
o
C.
GENERAL DESCRIPTION
FEATURES
512K x 32Bit x 4 Banks Synchronous DRAM
ORDERING INFORMATION
- SE/N : Extended temperature (-25
o
C - 85
o
C)
Part NO.
Max Freq.
Interface Package
K4S643233E-SE/N70
143MHz
LVTTL
90-Ball
FBGA
K4S643233E-SE/N80
125MHz
K4S643233E-SE/N10
100MHz
FUNCTIONAL BLOCK DIAGRAM
Samsung Electronics reserves the right to
change products or specification without
notice.
*
Bank Select
Data Input Register
512K x 32
512K x 32
S
e
n
s
e
A
M
P
O
u
t
p
u
t
B
u
f
f
e
r
I
/
O
C
o
n
t
r
o
l
Column Decoder
Latency & Burst Length
Programming Register
A
d
d
r
e
s
s
R
e
g
i
s
t
e
r
R
o
w
B
u
f
f
e
r
R
e
f
r
e
s
h
C
o
u
n
t
e
r
R
o
w
D
e
c
o
d
e
r
C
o
l
.
B
u
f
f
e
r
L
R
A
S
L
C
B
R
LCKE
LRAS
LCBR
LWE
LDQM
CLK
CKE
CS
RAS
CAS
WE
DQM
LWE
LDQM
DQi
CLK
ADD
LCAS
LWCBR
512K x 32
512K x 32
Timing Register
K4S643233E-SE/N
CMOS SDRAM
- 4 -
Rev. 1.5 April 2002
90Ball(6x15) CSP
1
2
3
7
8
9
A
DQ26
DQ24
V
SS
V
D D
DQ23
DQ21
B
DQ28
V
DDQ
V
SSQ
V
DDQ
V
SSQ
DQ19
C
V
SSQ
DQ27
DQ25
DQ22
DQ20
V
DDQ
D
V
SSQ
DQ29
DQ30
DQ17
DQ18
V
DDQ
E
V
DDQ
DQ31
NC
NC
DQ16
V
SSQ
F
V
SS
DQM3
A3
A2
DQM2
V
D D
G
A4
A5
A6
A10
A0
A1
H
A7
A8
NC
NC
BA1
NC
J
CLK
CKE
A9
BA0
CS
RAS
K
DQM1
NC
NC
CAS
WE
DQM0
L
V
DDQ
DQ8
V
SS
V
D D
DQ7
V
SSQ
M
V
SSQ
DQ10
DQ9
DQ6
DQ5
V
DDQ
N
V
SSQ
DQ12
DQ14
DQ1
DQ3
V
DDQ
P
DQ11
V
DDQ
V
SSQ
V
DDQ
V
SSQ
DQ4
R
DQ13
DQ15
V
SS
V
D D
DQ0
DQ2
Pin Name
Pin Function
CLK
System Clock
CS
Chip Select
CKE
Clock Enable
A
0
~ A
10
Address
BA
0
~ BA
1
Bank Select Address
RAS
Row Address Strobe
CAS
Column Address Strobe
WE
Write Enable
DQM
0
~
DQM
3
Data Input/Output Mask
DQ
0
~
31
Data Input/Output
V
DD
/V
SS
Power Supply/Ground
V
DDQ
/V
SSQ
Data Output Power/Ground
90-Ball FBGA Package Dimension and Pin Configuration
< Bottom View
*1
>
< Top View
*2
>
< Top View
*2
>
*2: Top View
Symbol
Min
Typ
Max
A
-
1.40
1.45
A
1
0.30
0.35
0.40
E
-
11.00
-
E
1
-
6.40
-
D
-
13.00
-
D
1
-
11.20
-
e
-
0.80
-
b
0.40
0.45
0.50
-
-
0.10
[Unit:mm]
5
2
1
6
3
4
8
9
7
F
E
D
C
B
J
H
G
A
e
D
D
/
2
D
1
E
1
E
E/2
A
A1
b
Substrate(2 Layer)
#A1 Ball Origin Indicator
*1: Bottom View
M
L
K
R
P
N
K
4
S
6
4
3
2
3
3
E
S
E
C
W
e
e
k
S
X
X
X
K4S643233E-SE/N
CMOS SDRAM
- 5 -
Rev. 1.5 April 2002
DC OPERATING CONDITIONS
Recommended operating conditions (Voltage referenced to V
SS
= 0V, T
A
= -25
o
C to +85
o
C)
Parameter
Symbol
Min
Typ
Max
Unit
Note
Supply voltage
V
DD
, V
DDQ
2.7
3.0
3.6
V
Input logic high voltage
V
IH
2.0
3.0
V
DDQ
+0.3
V
1
Input logic low voltage
V
IL
-0.3
0
0.8
V
2
Output logic high voltage
V
OH
2.4
-
-
V
I
OH
= -2mA
Output logic low voltage
V
OL
-
-
0.4
V
I
OL
= 2mA
Input leakage current
I
LI
-10
-
10
uA
3
1. V
IH
(max) = 5.6V AC.The overshoot voltage duration is
3ns.
2. V
IL
(min) = -2.0V AC. The undershoot voltage duration is
3ns.
3. Any input 0V
V
IN
V
DDQ
,
Input leakage currents include Hi-Z output leakage for all bi-directional buffers with Tri-State outputs.
Notes :
ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
Value
Unit
Voltage on any pin relative to Vss
V
IN
, V
O U T
-1.0 ~ 4.6
V
Voltage on V
D D
supply relative to Vss
V
DD
, V
DDQ
-1.0 ~ 4.6
V
Storage temperature
T
STG
-55 ~ +150
C
Power dissipation
P
D
1
W
Short circuit current
I
OS
50
mA
Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
Note :
CAPACITANCE
(V
D D
= 3.0 & 3.3V, T
A
= 23
C, f = 1MHz, V
REF
= 1.4V
200
mV)
Pin
Symbol
Min
Max
Unit
Clock
C
CLK
-
4
pF
RAS, CAS, WE, CS, CKE, DQM
C
IN
-
4.5
pF
Address
C
A D D
-
4.5
pF
DQ
0
~ DQ
31
C
O U T
-
6.5
pF
K4S643233E-SE/N
CMOS SDRAM
- 6 -
Rev. 1.5 April 2002
(Recommended operating condition unless otherwise noted, T
A
= -25
o
C to +85
o
C)
Parameter
Symbol
Test Condition
Speed
Unit
Note
-70
-80
-10
Operating Current
(One Bank Active)
I
CC1
Burst Length =1
t
RC
t
RC
(min), t
C C
t
C C
(min), Io = 0mA
155
150
140
mA
2
Precharge Standby Current
in power-down mode
I
CC2
P CKE
V
IL
(max), t
CC
= 15ns
3
mA
I
CC2
PS CKE & CLK
V
IL
(max), t
CC
=
2
Precharge Standby Current
in non power-down mode
I
CC2
N CKE
V
IH(min)
, CS
V
IH(min)
, t
C C
= 15ns
Input signals are changed one time during 30ns
20
mA
I
CC2
NS CKE
V
IH(min)
, CLK
V
IL(max)
, tCC =
Input signals are stable
10
Active Standby Current
in power-down mode
I
CC3
P CKE
V
IL(max),
t
CC
= 15ns
7
mA
I
CC3
PS CKE
V
IL(max)
, t
CC
=
5
Active Standby Current
in non power-down mode
(One Bank Active)
I
CC3
N CKE
V
IH(min)
, CS
V
IH(min)
, t
C C
= 15ns
Input signals are changed one time during 30ns
55
mA
I
CC3
NS CKE
V
IH(min)
, CLK
V
IL(max)
, t
CC
=
Input signals are stable
40
Operating Current
(Burst Mode)
I
CC4
Io = 0 mA, Page Burst
All bank Activated, t
CCD
= t
CCD(min)
170
160
150
mA
2
Refresh Current
I
CC5
t
RC
t
RC(min)
165
155
145
mA
3
Self Refresh Current
I
CC6
CKE
0.2V
-SE
3
mA
4
-SN
450
uA
5
DC CHARACTERISTICS
1. Unless otherwise notes, Input level is CMOS(V
IH
/V
IL
=V
DDQ
/V
SSQ
).
2. Measured with outputs open.
3. Refresh period is 64ms.
4. K4S643233E-SE**
5. K4S643233E-SN**
Notes :
K4S643233E-SE/N
CMOS SDRAM
- 7 -
Rev. 1.5 April 2002
AC OPERATING TEST CONDITIONS
(V
DD
= 2.7V ~ 3.6V, T
A
= -25
o
C to +85
o
C)
Parameter
Value
Unit
AC input levels (Vih/Vil)
2.4/0.4
V
Input timing measurement reference level
1.4
V
Input rise and fall time
tr/tf = 1/1
ns
Output timing measurement reference level
1.4
V
Output load condition
See Fig. 2
VDDQ
1200
870
Output
30pF
V
OH
(DC) = 2.4V, I
OH
= -2mA
V
OL
(DC) = 0.4V, I
OL
= 2mA
Vtt = 1.4V
50
Output
30pF
Z0 = 50
(Fig. 2) AC output load circuit
(Fig. 1) DC output load circuit
OPERATING AC PARAMETER
(AC operating conditions unless otherwise noted)
Parameter
Symbol
Version
Unit
Note
-70
-80
-10
CAS Latency
CL
3
2
1
3
2
1
3
2
1
CLK
CLK cycle time
t
CC(min)
7
10
20
8
12
20
10
12
20
ns
Row active to row active delay
t
RRD(min)
2
2
1
2
2
1
2
2
1
CLK
1
RAS to CAS delay
t
RCD(min)
3
2
1
3
2
1
2
2
1
CLK
1
Row precharge time
t
RP(min)
3
2
1
3
2
1
2
2
1
CLK
1
Row active time
t
RAS(min)
7
5
2
6
4
2
5
4
2
CLK
1
t
RAS(max)
100
us
Row cycle time
t
RC
(
min
)
10
7
3
10
7
3
10
7
3
CLK
1
Last data in to row precharge
t
RDL(min)
2
CLK
2
Last data in to new col.address delay t
CDL(min)
1
CLK
2
Last data in to burst stop
t
BDL(min)
1
CLK
2
Col. address to col. address delay
t
CCD(min)
1
CLK
3
Mode Register Set cycle time
t
MRS(min)
2
CLK
Number of valid
output data
CAS Latency=3
2
ea
4
CAS Latency=2
1
CAS Latency=1
0
1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time
and then rounding off to the next higher integer.
2. Minimum delay is required to complete write.
3. All parts allow every cycle column address change.
4. In case of row precharge interrupt, auto precharge and read burst stop.
Notes :
K4S643233E-SE/N
CMOS SDRAM
- 8 -
Rev. 1.5 April 2002
1. Parameters depend on programmed CAS latency.
2. If clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter.
3. Assumed input rise and fall time (tr & tf)=1ns.
If tr & tf is longer than 1ns, transient time compensation should be considered,
i.e., [(tr + tf)/2-1]ns should be added to the parameter.
Note :
AC CHARACTERISTICS
(AC operating conditions unless otherwise noted)
Parameter
Symbol
-70
-80
-10
Unit
Note
Min
Max
Min
Max
Min
Max
CLK cycle time
CAS Latency=3
t
C C
7
1000
8
1000
10
1000
ns
1
CAS Latency=2
10
12
12
CAS Latency=1
20
20
20
CLK to valid
output delay
CAS Latency=3
t
SAC
-
5.5
-
6
-
6
ns
1, 2
CAS Latency=2
-
6
-
8
-
8
CAS Latency=1
-
18
-
18
-
18
Output data hold time
CAS Latency=2,3
t
OH
2
-
2
-
2
-
ns
2
CAS Latency=1
3
-
3
-
3
-
CLK high pulse width
t
C H
3
-
3
-
3.5
-
ns
3
CLK low
t
CL
3
-
3
-
3.5
-
ns
3
Input setup time
t
SS
1.75
-
2
-
2.5
-
ns
3
Input hold time
t
SH
1
-
1
-
1
-
ns
3
CLK to output in Low-Z
t
SLZ
1
-
1
-
1
-
ns
2
CLK to output
in Hi-Z
CAS Latency=3
t
SHZ
-
5.5
-
6
-
6
ns
-
CAS Latency=2
-
6
-
8
-
8
CAS Latency=1
-
18
-
18
-
18
K4S643233E-SE/N
CMOS SDRAM
- 9 -
Rev. 1.5 April 2002
SIMPLIFIED TRUTH TABLE
(V=Valid, X=Don
t care, H=Logic high, L=Logic low)
Command
CKEn-1
CKEn
CS
RAS
CAS
WE
DQM
BA
0,1
A
1 0
/AP
,
A
9
~ A
0
Note
Register
Mode register set
H
X
L
L
L
L
X
OP code
1,2
Refresh
Auto refresh
H
H
L
L
L
H
X
X
3
Self
refresh
Entry
L
3
Exit
L
H
L
H
H
H
X
X
3
H
X
X
X
3
Bank active & row addr.
H
X
L
L
H
H
X
V
Row address
Read &
column address
Auto precharge disable
H
X
L
H
L
H
X
V
L
Column
address
(A
0
~ A
7
)
4
Auto precharge enable
H
4,5
Write &
column address
Auto precharge disable
H
X
L
H
L
L
X
V
L
Column
address
(A
0
~ A
7
)
4
Auto precharge enable
H
4,5
Burst Stop
H
X
L
H
H
L
X
X
6
Precharge
Bank selection
H
X
L
L
H
L
X
V
L
X
All banks
X
H
Clock suspend or
active power down
Entry
H
L
H
X
X
X
X
X
L
V
V
V
Exit
L
H
X
X
X
X
X
Precharge power down mode
Entry
H
L
H
X
X
X
X
X
L
H
H
H
Exit
L
H
H
X
X
X
X
L
V
V
V
DQM
H
V
X
7
No operation command
H
X
H
X
X
X
X
X
L
H
H
H
1. OP Code : Operand code
A
0
~ A
10
& BA
0
~ BA
1
: Program keys. (@ MRS)
2. MRS can be issued only at all banks precharge state.
A new command can be issued after 2 CLK cycles of MRS.
3. Auto refresh functions are as same as CBR refresh of DRAM.
The automatical precharge without row precharge command is meant by "Auto".
Auto/self refresh can be issued only at all banks precharge state.
4. BA
0
~ BA
1
: Bank select addresses.
If both BA
0
and BA
1
are "Low" at read, write, row active and precharge, bank A is selected.
If BA
0
is "Low" and BA
1
is "High" at read, write, row active and precharge, bank B is selected.
If BA
0
is "High" and BA
1
is "Low" at read, write, row active and precharge, bank C is selected.
If both BA
0
and BA
1
are "High" at read, write, row active and precharge, bank D is selected.
If A
10
/AP is "High" at row precharge, BA
0
and BA
1
is ignored and all banks are selected.
5. During burst read or write with auto precharge, new read/write command can not be issued.
Another bank read/write command can be issued after the end of burst.
New row active of the associated bank can be issued at t
RP
after the end of burst.
6. Burst stop command is valid at every burst length.
7. DQM sampled at the positive going edge of CLK masks the data-in at that same CLK in write operation (Write DQM latency
is 0), but in read operation makes the data-out Hi-Z state after 2 CLK cycles. (Read DQM latency is 2).
Notes :
X
K4S643233E-SE/N
CMOS SDRAM
- 10
Rev. 1.5 April 2002
MODE REGISTER FIELD TABLE TO PROGRAM MODES
Register Programmed with MRS
Address
Function
A
10
/AP
RFU
A
9
W.B.L
A
8
A
7
TM
A
6
A
5
A
4
A
3
A
2
A
1
A
0
CAS Latency
BT
Burst Length
A
8
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
BT = 0
Test Mode
Type
Mode Register Set
Reserved
Reserved
Reserved
0
0
1
1
0
1
0
1
Write Burst Length
A
9
0
1
Length
Burst
Single Bit
Latency
Reserved
1
2
3
Reserved
Reserved
Reserved
Reserved
CAS Latency
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Burst Type
0
1
BT = 1
Burst Length
Type
Sequential
Interleave
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1
2
4
8
Reserved
Reserved
Reserved
Full Page
1
2
4
8
Reserved
Reserved
Reserved
Reserved
POWER UP SEQUENCE
SDRAMs must be powered up and initialized in a predefined manner to prevent undefined operations.
1. Apply power and start clock. Must maintain CKE= "H", DQM= "H" and the other pins are NOP condition at the inputs.
2. Power is applied to VDD and VDDQ (simultaneously).
3. Maintain stable power, stable clock and NOP input condition for a minimum of 200us.
4. Issue precharge commands for all banks of the devices.
5. Issue 2 or more auto-refresh commands.
6. Issue a mode register set command to initialize the mode register.
cf.) Sequence of 4 & 5 is regardless of the order.
The device is now ready for normal operation.
Note
: 1. If A
9
is high during MRS cycle, "Burst Read Single Bit Write" function will be enabled.
2. RFU (Reserved for future use) should stay "0" during MRS cycle.
Full Page Length : x32 (256)
BA
0
~ BA
1
RFU
K4S643233E-SE/N
CMOS SDRAM
- 11
Rev. 1.5 April 2002
BURST SEQUENCE (BURST LENGTH = 4)
Initial Address
Sequential
Interleave
A
1
A
0
0
0
1
1
0
1
0
1
0
1
2
3
1
2
3
0
2
3
0
1
3
0
1
2
0
1
2
3
1
0
3
2
2
3
0
1
3
2
1
0
BURST SEQUENCE (BURST LENGTH = 8)
Initial Address
Sequential
Interleave
0
0
0
0
1
1
1
1
0
1
0
1
0
1
0
1
0
1
2
3
4
5
6
7
2
3
4
5
6
7
0
1
4
5
6
7
0
1
2
3
6
7
0
1
2
3
4
5
A
1
A
0
A
2
0
0
1
1
0
0
1
1
1
2
3
4
5
6
7
0
3
4
5
6
7
0
1
2
5
6
7
0
1
2
3
4
7
0
1
2
3
4
5
6
0
1
2
3
4
5
6
7
2
3
0
1
6
7
4
5
4
5
6
7
0
1
2
3
6
7
4
5
2
3
0
1
1
0
3
2
5
4
7
6
3
2
1
0
7
6
5
4
5
4
7
6
1
0
3
2
7
6
5
4
3
2
1
0
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