K4S280832B
CMOS SDRAM
Rev. 0.0 Aug. 1999
V
DD
DQ0
V
DDQ
N.C
DQ1
V
SSQ
N.C
DQ2
V
DDQ
N.C
DQ3
V
SSQ
N.C
V
DD
N.C
WE
CAS
RAS
CS
BA0
BA1
A10/AP
A0
A1
A2
A3
V
DD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
PIN CONFIGURATION (Top view)
V
SS
DQ7
V
SSQ
N.C
DQ6
V
DDQ
N.C
DQ5
V
SSQ
N.C
DQ4
V
DDQ
N.C
V
SS
N.C/RFU
DQM
CLK
CKE
N.C
A11
A9
A8
A7
A6
A5
A4
V
SS
54Pin TSOP (II)
(400mil x 875mil)
(0.8 mm Pin pitch)
PIN FUNCTION DESCRIPTION
Pin
Name
Input Function
CLK
System clock
Active on the positive going edge to sample all inputs.
CS
Chip select
Disables or enables device operation by masking or enabling all inputs except
CLK, CKE and DQM
CKE
Clock enable
Masks system clock to freeze operation from the next clock cycle.
CKE should be enabled at least one cycle prior to new command.
Disable input buffers for power down in standby.
A
0
~ A
11
Address
Row/column addresses are multiplexed on the same pins.
Row address : RA
0
~ RA
11
, Column address : CA
0
~ CA
9
BA
0
~ BA
1
Bank select address
Selects bank to be activated during row address latch time.
Selects bank for read/write during column address latch time.
RAS
Row address strobe
Latches row addresses on the positive going edge of the CLK with RAS low.
Enables row access & precharge.
CAS
Column address strobe
Latches column addresses on the positive going edge of the CLK with CAS low.
Enables column access.
WE
Write enable
Enables write operation and row precharge.
Latches data in starting from CAS, WE active.
DQM
Data input/output mask
Makes data output Hi-Z, t
SHZ
after the clock and masks the output.
Blocks data input when DQM active.
DQ
0
~
7
Data input/output
Data inputs/outputs are multiplexed on the same pins.
V
DD
/V
SS
Power supply/ground
Power and ground for the input buffers and the core logic.
V
DDQ
/V
SSQ
Data output power/ground
Isolated power supply and ground for the output buffers to provide improved noise
immunity.
N.C/RFU
No connection
/reserved for future use
This pin is recommended to be left No Connection on the device.
K4S280832B
CMOS SDRAM
Rev. 0.0 Aug. 1999
ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
Value
Unit
Voltage on any pin relative to Vss
V
IN
, V
OUT
-1.0 ~ 4.6
V
Voltage on V
DD
supply relative to Vss
V
DD
, V
DDQ
-1.0 ~ 4.6
V
Storage temperature
T
STG
-55 ~ +150
C
Power dissipation
P
D
1
W
Short circuit current
I
OS
50
mA
Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
Note :
DC OPERATING CONDITIONS
Recommended operating conditions (Voltage referenced to V
SS
= 0V, T
A
= 0 to 70
C)
Parameter
Symbol
Min
Typ
Max
Unit
Note
Supply voltage
V
DD
, V
DDQ
3.0
3.3
3.6
V
Input logic high voltage
V
IH
2.0
3.0
V
DD
+0.3
V
1
Input logic low voltage
V
IL
-0.3
0
0.8
V
2
Output logic high voltage
V
OH
2.4
-
-
V
I
OH
= -2mA
Output logic low voltage
V
OL
-
-
0.4
V
I
OL
= 2mA
Input leakage current
I
LI
-10
-
10
uA
3
1. V
IH
(max) = 5.6V AC.The overshoot voltage duration is
3ns.
2. V
IL
(min) = -2.0V AC. The undershoot voltage duration is
3ns.
3. Any input 0V
V
IN
V
DDQ
,
Input leakage currents include Hi-Z output leakage for all bi-directional buffers with Tri-State outputs.
Notes :
CAPACITANCE
(V
DD
= 3.3V, T
A
= 23
C, f = 1MHz, V
REF
=1.4V
200
mV)
Pin
Symbol
Min
Max
Unit
Note
Clock
C
CLK
2.5
4.0
pF
1
RAS, CAS, WE, CS, CKE, DQM
C
IN
2.5
5.0
pF
2
Address
C
ADD
2.5
5.0
pF
2
DQ
0
~ DQ
7
C
OUT
4.0
6.5
pF
3
1. -75 only specify a maximum value of 3.5pF
2. -75 only specify a maximum value of 3.8pF
3. -75 only specify a maximum value of 6.0pF
Notes :
K4S280832B
CMOS SDRAM
Rev. 0.0 Aug. 1999
DC CHARACTERISTICS
(Recommended operating condition unless otherwise noted, T
A
= 0 to 70
C)
Parameter
Sym-
bol
Test Condition
Version
Unit
Not
e
-75
-80
-1H
-1L
-10
Operating current
(One bank active)
I
CC1
Burst length = 1
t
RC
t
RC
(min)
I
O
= 0 mA
120
120
110
110
110
mA
1
Precharge standby current in
power-down mode
I
CC2
P
CKE
V
IL
(max), t
CC
= 10ns
1
mA
I
CC2
PS
CKE & CLK
V
IL
(max), t
CC
=
1
Precharge standby current in
non power-down mode
I
CC2
N
CKE
V
IH
(min), CS
V
IH
(min), t
CC
= 10ns
Input signals are changed one time during 20ns
20
mA
I
CC2
NS
CKE
V
IH
(min), CLK
V
IL
(max), t
CC
=
Input signals are stable
7
Active standby current in
power-down mode
I
CC3
P
CKE
V
IL
(max), t
CC
= 10ns
5
mA
I
CC3
PS
CKE & CLK
V
IL
(max), t
CC
=
5
Active standby current in
non power-down mode
(One bank active)
I
CC3
N
CKE
V
IH
(min), CS
V
IH
(min), t
CC
= 10ns
Input signals are changed one time during 20ns
30
mA
I
CC3
NS
CKE
V
IH
(min), CLK
V
IL
(max), t
CC
=
Input signals are stable
20
mA
Operating current
(Burst mode)
I
CC4
I
O
= 0 mA
Page burst
4Banks Activated
t
CCD
= 2CLKs
150
145
125
125
125
mA
1
Refresh current
I
CC5
t
RC
t
RC
(min)
220
220
210
210
210
mA
2
Self refresh current
I
CC6
CKE
0.2V
C
1.5
mA
3
L
800
uA
4
1. Measured with outputs open.
2. Refresh period is 64ms.
3. K4S280832B-TC**
4. K4S280832B-TL**
5. Unless otherwise noted, input swing IeveI is CMOS(V
IH
/V
IL
=V
DDQ
/V
SSQ)
Notes :
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