CMOS SDRAM
Rev. 1.1 February 2004
SDRAM stacked 1Gb B-die (x8)
stacked 1Gb B-die SDRAM Specification
Revision 1.1
February 2004
* Samsung Electronics reserves the right to change products or specification without notice.
CMOS SDRAM
Rev. 1.1 February 2004
SDRAM stacked 1Gb B-die (x8)
Revision History
Revision 1.0 (August, 2003)
- First release.
Revision 1.1 (February, 2004)
-Corrected typo.
CMOS SDRAM
Rev. 1.1 February 2004
SDRAM stacked 1Gb B-die (x8)
JEDEC standard 3.3V power supply
LVTTL compatible with multiplexed address
Four banks operation
MRS cycle with address key programs
-. CAS latency (2 & 3)
-. Burst length (1, 2, 4, 8)
-. Burst type (Sequential & Interleave)
All inputs are sampled at the positive going edge of the system clock.
Burst read single-bit write operation
DQM for masking
Auto & self refresh
64ms refresh period (8K Cycle)
FEATURES
32M x 8Bit x 4 Banks Synchronous DRAM
The K4S1G0732B is 1,073,741,824bits synchronous high data rate Dynamic RAM organized as 4 x 33,554,432 words by 8 bits, fabri-
cated with SAMSUNG's high performance CMOS technology. Synchronous design allows precise cycle control with the use of system
clock I/O transactions are possible on every clock cycle. Range of operating frequencies, programmable burst length and programmable
latencies allow the same device to be useful for a variety of high bandwidth, high performance memory system applications.
GENERAL DESCRIPTION
Part No.
Orgainization
Max Freq.
Interface
Package
K4S1G0732B-TC75
st.128Mb x8
133MHz
LVTTL
54pin TSOP(II)
Ordering Information
Organization
Row Address
Column Address
st.128Mx8
A0~A12
A0-A9, A11
Row & Column address configuration
CMOS SDRAM
Rev. 1.1 February 2004
SDRAM stacked 1Gb B-die (x8)
11
.
7
6
0.2
0
0.05 MIN
0.
5
0
0.125
-0.035
+0.075
10.1
6
0.4
0
~0.6
0
0.25 TYP
0~8
C
#54
#28
#1
#27
0.10 MAX
0.71
0.25~0.40
0.80
2.54 MAX
22.53 MAX
22.22
0.10
Unit : Millimeters
Package Physical Dimension
54Pin TSOP2 Stack Package Dimension
FUNCTIONAL BLOCK DIAGRAM
64Mx8
64Mx8
A0~A12,BA0,BA1
DQ0 ~ DQ7
CLK,CAS,RAS
/WE,DQM
/CS1,CKE1
/CS0,CKE0
CMOS SDRAM
Rev. 1.1 February 2004
SDRAM stacked 1Gb B-die (x8)
PIN CONFIGURATION (Top view)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
54Pin TSOP
(400mil x 875mil)
(0.8 mm Pin pitch)
V
DD
DQ0
V
DDQ
N.C
DQ1
V
SSQ
N.C
DQ2
V
DDQ
N.C
DQ3
V
SSQ
N.C
V
DD
CS1
WE
CAS
RAS
CS0
BA0
BA1
A10/AP
A0
A1
A2
A3
V
DD
V
SS
DQ7
V
SSQ
N.C
DQ6
V
DDQ
N.C
DQ5
V
SSQ
N.C
DQ4
V
DDQ
N.C
V
SS
CKE1
DQM
CLK
CKE0
A12
A11
A9
A8
A7
A6
A5
A4
V
SS
PIN FUNCTION DESCRIPTION
Pin
Name
Input Function
CLK
System clock
Active on the positive going edge to sample all inputs.
CS0~1
Chip select
Disables or enables device operation by masking or enabling all inputs except
CLK, CKE and DQM
CKE0~1
Clock enable
Masks system clock to freeze operation from the next clock cycle.
CKE should be enabled at least one cycle prior to new command.
Disable input buffers for power down in standby.
A
0
~ A
12
Address
Row/column addresses are multiplexed on the same pins.
Row address : RA
0
~ RA
12
, Column address : CA
0
~ CA
9,
CA
11
BA
0
~ BA
1
Bank select address
Selects bank to be activated during row address latch time.
Selects bank for read/write during column address latch time.
RAS
Row address strobe
Latches row addresses on the positive going edge of the CLK with RAS low.
Enables row access & precharge.
CAS
Column address strobe
Latches column addresses on the positive going edge of the CLK with CAS low.
Enables column access.
WE
Write enable
Enables write operation and row precharge.
Latches data in starting from CAS, WE active.
DQM
Data input/output mask
Makes data output Hi-Z, t
SHZ
after the clock and masks the output.
Blocks data input when DQM active.
DQ
0
~
7
Data input/output
Data inputs/outputs are multiplexed on the same pins.
V
DD
/V
SS
Power supply/ground
Power and ground for the input buffers and the core logic.
V
DDQ
/V
SSQ
Data output power/ground
Isolated power supply and ground for the output buffers to provide improved noise
immunity.
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