SDRAM 16Mb H-die(x16)
CMOS SDRAM
Rev. 1.5 August 2004
Revision History
Revision 0.0 (May, 2003)
- Target spec release.
Revision 0.1 (October, 2003)
- Modified tRDL from 1CLK to 2CLK.
Revision 0.2 (October, 2003)
- Deleted AC parameter notes 5.
Revision 0.3 (October, 2003)
- Modified tRDL & deleted speed 200MHz.
Revision 1.0 (November, 2003)
- Revision 1.0 spec. release.
Revision 1.1 (December, 2003)
- Corrected PKG dimension.
Revision 1.2 (January, 2004)
- Deleted -10(10ns) speed.
- Modified load cap 50pF -> 30pF.
- Modified DC current .
Revision 1.3 (January, 2004)
- Corrected typo
Revision 1.4 (May, 2004)
- Added Note 8. sentense of tRDL parameter.
Revision 1.5 (August, 2004)
- Modified CLK cycle time(tcc) parameter in AC Characteristics.
( If you want use of CL=2 not CL=3, the maximum operating frequency is 100MHz regardless of its speed bin.)
SDRAM 16Mb H-die(x16)
CMOS SDRAM
Rev. 1.5 August 2004
The K4S161622H is 16,777,216 bits synchronous high data rate Dynamic RAM organized as 2 x 524,288 words by 16 bits, fabricated
with SAMSUNG
s high performance CMOS technology. Synchronous design allows precise cycle control with the use of system clock I/
O transactions are possible on every clock cycle. Range of operating frequencies, programmable burst length and programmable laten-
cies allow the same device to be useful for a variety of high bandwidth, high performance memory system applications.
3.3V power supply
LVTTL compatible with multiplexed address
two banks operation
MRS cycle with address key programs
-. CAS Latency ( 2 & 3)
-. Burst Length (1, 2, 4, 8 & full page)
-. Burst Type (Sequential & Interleave)
All inputs are sampled at the positive going edge of the system clock
Burst Read Single-bit Write operation
DQM for masking
Auto & self refresh
32ms refresh period (2K cycle)
GENERAL DESCRIPTION
FEATURES
512K x 16Bit x 2 Banks SDRAM
ORDERING INFORMATION
Part NO.
MAX Freq.
Interface
Package
K4S161622H-TC55
183MHz
LVTTL
50pin
TSOP(II)
K4S161622H-TC60
166MHz
K4S161622H-TC70
143MHz
K4S161622H-TC80
125MHz
Row & Column address configuration
Organization
Row Address
Column Address
1Mx16
A0~A10
A0-A7
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