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256M GDDR3 SDRAM

K4J55323QG

Rev. 1.1 November 2005

1 of 53

256Mbit GDDR3 SDRAM

* Samsung Electronics reserves the right to change products or specification without notice.

Notice

INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS,
AND IS SUBJECT TO CHANGE WITHOUT NOTICE.

NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE,
EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE,

TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY. ALL
INFORMATION IN THIS DOCUMENT IS PROVIDED

ON AS "AS IS" BASIS WITHOUT GUARANTEE OR WARRANTY OF ANY KIND.

1. For updates or additional information about Samsung products, contact your nearest Samsung office.

2. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar

applications where Product failure could result in loss of life or personal or physical harm, or any military or
defense application, or any governmental procurement to which special terms or provisions may apply.

Revision 1.1

November 2005

256M GDDR3 SDRAM

K4J55323QG

Rev. 1.1 November 2005

2 of 53

Revision History

Revision

Month

Year

History

0.0

February

2005

- Target Spec

0.1

March

2005

- Changed EMRS table for Driver Impedance control.

0.2

March

2005

- Typo corrected.
- Added clock frequency change sequence on page 18 and IBIS spec on page 19~21
- Reduced Cin min. value on page 54.
- Added note for RFM pin on page 4.
- Modified input functional description for CK/CK and Vref on page 5.

- Removed -BC10/11 from the spec. Accordingly, CL12~15 become "reserved" in MRS table.

0.3

April

2005

- Modified note description for RMF on page 4.

- Modified input functional description for Mirror function on page 5.
- Modified note description for the Write Latency on page 55.

0.4

May

2005

- Clarify RMF description on page 4,5 to avoid confusion in case of using same board for both

512Mb and 256Mb GDDR3.

- Added note description for Boundary scan function on page 22,23.

(one RFM ball in the scan oder will be read as a logic "0")

1.0

June

2005

- Typo corrected.

- Finalized DC characteristics and IBIS specification

1.1

November

2005

- Changed tRFC of -BC16 from 33tCK to 31tCK effective date code with WW0543

256M GDDR3 SDRAM

K4J55323QG

Rev. 1.1 November 2005

3 of 53

· 1.8V + 0.1V power supply for device operation
· 1.8V + 0.1V power supply for I/O interface
· On-Die Termination (ODT)
· Output Driver Strength adjustment by EMRS
· Calibrated output drive
· 1.8V Pseudo Open drain compatible inputs/outputs
· 4 internal banks for concurrent operation
· Differential clock inputs (CK and CK)
· Commands entered on each positive CK edge
· CAS latency : 4, 5, 6, 7, 8, 9, 10, 11 (clock)
· Additive latency (AL): 0 and 1 (clock)
· Programmable Burst length : 4 and 8
· Programmable Write latency : 1, 2, 3, 4, 5, 6 and 7 (clock)
· Single ended READ strobe (RDQS) per byte

· Single ended WRITE strobe (WDQS) per byte
· RDQS edge-aligned with data for READs
· WDQS center-aligned with data for WRITEs
· Data Mask(DM) for masking WRITE data
· Auto & Self refresh modes
· Auto Precharge option
· 32ms, auto refresh (4K cycle)
· 136 Ball FBGA
· Maximum clock frequency up to 800MHz
· Maximum data rate up to 1.6Gbps/pin
· DLL for outputs
· Boundary scan function with SEN pin
· Mirror function with MF pin

2M x 32Bit x 4 Banks Graphic Double Data Rate 3 Synchronous DRAM
with Uni-directional Data Strobe

K4J55323QC-AC** is leaded package part number

Part Number

Max Freq.

Max Data Rate

Interface

Package

K4J55323QG-BC12

800MHz

1.6Gbps/pin

Pseudo

Open Drain_18

136 Ball FBGA

K4J55323QG-BC14

700MHz

1.4Gbps/pin

K4J55323QG-BC16

600MHz

1.2Gbps/pin

K4J55323QG-BC20

500MHz

1.0Gbps/pin

The K4J55323QG is 268,435,456 bits of hyper synchronous data rate Dynamic RAM organized as 4 x 2,097,152 words by 32 bits, fab-
ricated with SAMSUNG

high performance CMOS technology. Synchronous features with Data Strobe allow extremely high perfor-

mance up to 6.4GB/s/chip. I/O transactions are possible on both edges of the clock cycle. Range of operating frequencies, and
programmable latencies allow the device to be useful for a variety of high performance memory system applications.

FOR 2M x 32Bit x 4 Bank GDDR3 SDRAM

2.0 ORDERING INFORMATION

1.0 FEATURES

3.0 GENERAL DESCRIPTION

256M GDDR3 SDRAM

K4J55323QG

Rev. 1.1 November 2005

4 of 53

Normal Package (Top View)

VDDQ

VDD

VSS

VSSQ

DQ0

DQ1

VSSQ

VDDQ

DQ2

DQ3

VDDQ

VSSQ

WDQS0 RDQS0

VSSQ

VDDQ

DQ4

DM0

VDDQ

VDD

DQ6

DQ5

CAS

VSS

VSSQ

DQ7

BA0

VREF

RAS

CKE

VSSA

RFU1

RFU2

VDDQ

VDDA

A10

VSS

VSSQ

DQ25

A11

VDD

DQ24

DQ27

VDDQ

DQ26

DM3

VDDQ

VSSQ

WDQS3 RDQS3

VSSQ

VDDQ

DQ28

DQ29

VDDQ

VSSQ

DQ30

DQ31

VSSQ

VDDQ

VDD

VSS

SEN

VSS

VDD

VDDQ

VSSQ

DQ9

DQ8

VSSQ

VDDQ

DQ11

DQ10

VDDQ

VSSQ

RDQS1 WDQS1

VSSQ

VDDQ

DM1

DQ12

VDDQ

DQ13

DQ14

VDD

BA1

DQ15

VSSQ

VSS

VREF

VDDQ

VSSA

A8/AP

VDDA

DQ17

VSSQ

VSS

DQ19

DQ16

VDD

VDDQ

DM2

DQ18

VDDQ

VSSQ

RDQS2 WDQS2

VSSQ

VDDQ

DQ21

DQ20

VDDQ

VSSQ

DQ23

DQ22

VSSQ

RESET

VSS

VDD

VDDQ

RFM

Note :
1. RFU1 is reserved for future use
2. RFU2 is reserved for future use
3. RFM : When the MF ball is tied LOW, RFM(H10) receiver is disabled and it recommended to be driven to a static LOW state, however,

either static HIGH or floating state on this pin will not cause any problem for the DRAM. When the MF ball is tied HIGH, RAS(H3)
becomes RFM due to mirror function and the receiver is disabled. It recommended to be driven to a static LOW state, however, either
static HIGH or floating state on this pin will not cause any problem for the DRAM

Please refer to Mirror Function Signal Mapping table at page 6.

4.0 PIN CONFIGURATION

256M GDDR3 SDRAM

K4J55323QG

Rev. 1.1 November 2005

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Symbol

Type

Function

CK, CK

Input

Clock: CK and CK are differential clock inputs. CMD, ADD inputs are sampled on the crossing of the positive
edge of CK and negative edge of CK. Output (read) data is referenced to the crossings of CK and CK (both
directions of crossing). CK, CK should be maintained stable, except self-refresh mode

CKE

Input

Clock Enable: CKE HIGH activates, and CKE Low deactivates, internal clock signals and device input buffers
and output drivers. Taking CKE Low provides Precharge Power-Down and Self Refresh operation (all banks
idle), or Active Power-Down (row Active in any bank). CKE is synchronous for power down entry and exit, and
for self refresh entry. CKE is asynchronous for self refresh exit. CKE must be maintained high throughout read
and write accesses. Input buffers, excluding CK, CK and CKE are disabled during power-down. Input buffers,
excluding CKE, are disabled during self refresh.

Input

Chip Select: All commands are masked when CS is registered HIGH. CS provides for external bank selection
on systems with multiple banks. CS is considered part of the command code.

RAS, CAS,

Input

Command Inputs: RAS, CAS and WE (along with CS) define the command being entered.

DM0

~DM3

Input

Input Data Mask: DM is an input mask signal for write data. Input data is masked when DM is sampled HIGH
coincident with that input data during a Write access. DM is sampled on both edges of clock. Although DM
pins are input only, the DM loading matches the DQ and WDQS loading.

BA0,BA1

Input

Bank Address Inputs: BA0 and BA1 define to which bank an Active, Read, Write or Precharge command is
being applied.

A0 ~ A11

Input

Address Inputs: Provided the row address for Active commands and the column address and Auto Pre-
charge bit for Read/Write commands to select one location out of the memory array in the respective bank. A8
is sampled during a Precharge command to determine whether the Precharge applies to one bank (A8 LOW)
or all banks (A8 HIGH). If only one bank is to be precharged, the bank is selected by BA0, BA1,BA2. The
address inputs also provide the op-code during Mode Register Set commands.
Row addresses : RA0 ~ RA11, Column addresses : CA0 ~ CA7, CA9 . Column address CA8 is used for auto
precharge.

DQ0

~ DQ31

Input/

Output

Data Input/ Output: Bi-directional data bus.

RDQS0

~ RDQS3

Output

READ Data Strobe: Output with read data. RDQS is edge-aligned with read data.

WDQS0

~ WDQS3

Input

WRITE Data Strobe: Input with write data. WDQS is center-aligned to the inout data.

NC/RFU

No Connect: No internal electrical connection is present.

DDQ

Supply

DQ Power Supply

SSQ

Supply

DQ Ground

Supply

Power Supply

Supply

Ground

DDA

Supply

DLL Power Supply

SSA

Supply

DLL Ground

REF

Supply

Reference voltage: 0.7*VDDQ ,
2 Pins : (H12) for Data input , (H1) for CMD and ADDRESS

Input

Mirror Function for clamshell mounting of DRAMs. VDDQ CMOS input.

Reference Resistor connection pin for On-die termination.

RES

Input

Reset pin: RESET pin is a VDDQ CMOS input

SEN

Input

Scan enable : Must tie to the ground in case not in use. VDDQ CMOS input.

RFM

Input

Reserved for Mirror Function :
When the MF ball is tied low, RFM(H10) is recommended to be driven to logic low state.
When the MF ball is tied high, RAS(H3) switch to RFM and is recommended to be driven to logic low state

5.0 INPUT/OUTPUT FUNCTIONAL DESCRIPTION

256M GDDR3 SDRAM

K4J55323QG

Rev. 1.1 November 2005

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GDDR3 SDRAMs must be powered up and initialized in a predefined manner. Operational procedures other than

those

specified may result in undefined operation.

1. Apply power and keep CKE/RESET at low state ( All other inputs may be undefined)
- Apply VDD and VDDQ simultaneously
- Apply VDDQ before Vref. ( Inputs are not recognized as valid until after V

REF

is applied )

2. Required minimum 100us for the stable power before RESET pin transition to HIGH
- Upon power-up the address/command active termination value will automatically be set based off the state of RESET and CKE.
- On the rising edge of RESET the CKE pin is latched to determine the address and command bus termination value.
If CKE is sampled at a zero the address termination is set to 1/2 of ZQ.
If CKE is sampled at a one the address termination is set to ZQ.
- RESET must be maintained at a logic LOW level and CS at a logic high value during power-up to ensure that the DQ outputs will
be in a High-Z state, all active terminators off, and all DLLs off.
3. Minimum 200us delay required prior to applying any executable command after stable power and clock.
4. Once the 200us delay has been satisfied, a DESELECT or NOP command should be applied, then RESET and CKE should be
brought to HIGH,
5. Issue a PRECHARGE ALL command following after NOP command.
6. Issue a EMRS command (BA1BA0="01") to enable the DLL.
7. Issue MRS command (BA0BA1 = "00") to reset the DLL and to program the operating parameters.
20K clock cycles are required between the DLL to lock.
8. Issue a PRECHARGE ALL command
9 . Issue at least two AUTO refresh command to update the driver impedance and calibrate the output drivers.

Following these requirements, the GDDR3 SDRAM is ready for normal operation.

CODE

DDQ

REF

RES

CKE

COMMAND

A0-A7, A9-A11

BA0, BA1

RDQS

WDQS

CODE

BAO=H,

NOP

PRE

LMR

PRE

ACT

High

BA1 =L

BAO=L,

BA1 =L

T=10ns

Power-up:

and

CK stable

T = 200us

tRP

tMRD

tRFC

tRP

tRFC

Load Extended
Mode Register

tMRD

20K

Load Mode

CODE

Ta0

Tb0

Tc0

Td0

Te0

Tf0

ATS

ATH

Precharge
All Banks

1st

Auto Refresh

2nd

Auto Refresh

DLL Reset

ALL BANKS

7.2 INITIALIZATION

256M GDDR3 SDRAM

K4J55323QG

Rev. 1.1 November 2005

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The mode register stores the data for controlling the various operating modes of GDDR3 SDRAM. It programs CAS latency, address-

ing mode, test mode and various vendor specific options to make GDDR3 SDRAM useful for variety of different applications. The
default value of the mode register is not defined, therefore the mode register must be written after EMRS setting for the proper opera-
tion. The mode register is written by asserting low on CS, RAS, CAS and WE (The GDDR3 SDRAM should be in active mode with CKE
already high prior to writing into the mode register). The state of address pins A

~ A

and BA

, BA

in the same cycle as CS, RAS,

CAS and WE going low is written in the mode register. Minimum clock cycles specified as tMRD are required to complete the write oper-
ation in the mode register. The mode register contents can be changed using the same command and clock cycle requirements during
operation as long as all banks are in the idle state. The mode register is divided into various fields depending on functionality. The Burst
length uses A

~ A

. CAS latency (read latency from column address) uses A

, A

~ A

. A

is used for test mode. A

is used for DLL

reset. A

~ A

are used for Write latency. Refer to the table for specific codes for various addressing modes and CAS latencies.

CAS Latency

Reserved(12)

Reserved(13)

Reserved(14)

Reserved(15)

Reserved

Test Mode

mode

Normal

Test

Burst Type

Sequential

Reserved

DLL

DLL Reset

Yes

DLL

CAS Latency

Burst Length

Burst Length

Reserved

~ A

MRS

EMRS

Write Latency

Reserved

Note : DLL reset is self-clearing

RFU(Reserved for future use) should
stay "0" during MRS cycle

7.3 MODE REGISTER SET(MRS)

256M GDDR3 SDRAM

K4J55323QG

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BURST LENGTH

Read and write accesses to the GDDR3 SDRAM are burst oriented, with the burst length being programmable, as shown in MRS

table. The burst length determines the maximum number of column locations that can be accessed for a given READ or WRITE com-
mand. Reserved states should not be used, as unknown operation or incompatibility with future versions may result. When a READ or
WRITE command is issued, a block of columns equal to the burst length is effectively selected. All accesses for that burst take place
within the block, meaning that the burst will wrap within the block if a boundary is reached. The block is uniquely selected by A2-Ai when
the burst length is set to four (Where Ai is the most significant column address bit for a given configuration). The remaining (least signif-
icant) address bit(s) is (are) used to select the starting location within the block. The programmable burst length applies to both READ
and WRITE bursts.

BURST TYPE

Accesses within a given burst must be programmed to be sequential; this is referred to as the burst type and is selected via bit M3.

This device does not support the interleaved burst mode found in GDDR SDRAM devices. The ordering of accesses within a burst is
determined by the burst length, the burst type, and the starting column address, as shown in below table: Burst Definition

Note : 1. For a burst length of four, A2-A7 select the block of four burst; A0-A1 select the starting column within the block and must be set to zero
2. For a burst length of eight, A3-A7 select the block of eight burst; A0-A2 select the starting column within the block.

PROGRAMMABLE IMPEDANCE OUTPUT BUFFER AND ACTIVE TERMINATOR

The GDDR3 SDRAM is equipped with programmable impedance output buffers and Active Terminators. This allows a user to match

the driver impedance to the system. To adjust the impedance, an external precision resistor(RQ) is connected between the ZQ pin and
Vss. The value of the resistor must be six times of the desired output impedance.
For example, a 240

resistor is required for an output impedance of 40

. To ensure that output impedance is one sixth the value of RQ

(within 10 %), the range of RQ is

120

to 360

(20

to 60

)

output impedance.

MF,SEN, RES, CK and /CK are not internally terminated. CK and /CK will be terminated on the system module using external 1%
resisters. The output impedance is updated during all AUTO REFRESH commands and NOP commands when a READ is not in
progress to compensate for variations in voltage supply and temperature. The output impedance updates are transparent to the system.
Impedance updates do not affect device operation, and all data sheet timing and current specifications are met during update. To guar-
antee optimum output driver impedance after power-up, the GDDR3(x32) needs at least 20us after the clock is applied and stable to cal-
ibrate the impedance upon power-up. The user may operate the part with less than 20us, but the optimal output impedance is not
guaranteed. The value of ZQ is also used to calibrated the internal address/command termination resisters. The two termination values
that are selectable during power up are 1/2 of ZQ and ZQ. The value of ZQ is used to calibrate the internal DQ termination resisters. The
two termination values that are selectable are 1/4 of ZQ and 1/2 of ZQ.

Burst Definition

Burst
Length

Starting Column Address

Order of Accesses

Within a Burst

Type= Sequential

0 - 1 - 2 - 3

0 - 1 - 2 - 3 - 4 - 5 - 6 - 7

4 - 5 - 6 - 7 - 0 - 1 - 2 - 3

256M GDDR3 SDRAM

K4J55323QG

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CAS LATENCY (READ LATENCY)

The CAS latency is the delay, in clock cycles, between the registration of a READ command and the availability of the first bit of output

data. The latency can be set to 4~15 clocks. If a READ command is registered at clock edge n, and the latency is m clocks, the data will
be available nominally coincident with clock edge n+m. Below table indicates the operating frequencies at which each CAS latency set-
ting can be used. Reserved states should not be used as unknown operation or incompatibility with future versions may result.

CAS Latency

SPEED

Allowable operating frequency (MHz)

CL=15

CL=14

CL=13

CL=12

CL=11

CL=10

CL=9

CL=8

CL=7

-10

TBD

-11

TBD

-12

800

-14

700

-16

600

-20

500

NOP

READ

T7n

/CK
CK

COMMAND

RDQS

CL = 7

NOP

READ

T8n

/CK
CK

COMMAND

RDQS

CL = 8

Burst Length = 4 in the cases shown
Shown with nominal t

and nominal t

DSDQ

DON'T CARE

TRANSITIONING DATA

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K4J55323QG

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TEST MODE

The normal operating mode is selected by issuing a MODE REGISTER SET command with bits A7 set to zero, and bits A0-A6 and A8-

A11 set to the desired values. Test mode is entered by issuing a MODE REGISTER SET command with bit A7 set to one, and bits A0-
A6 and A8-A11 set to the desired values. Test mode functions are specific to each Dram Manufacturer and its exact functions are hidden
from the user.

DLL RESET

The normal operating mode is selected by issuing a MODE REGISTER SET command with bit A7 set to zero, and bits A0-A6 and A8-
A11 set to the desired values. A DLL reset is initiated by issuing a MODE REGISTER SET command with bit A8 set to one, and bits A0-
A7 and A9-A11 set to the desired values. When a DLL Reset is complete the GDDR3 SDRAM reset bit 8 of the mode register to a zero.
After DLL Reset MRS, Power down can not be issued within 10 clock.

In case the clock frequency need to be changed after the power-up, 256Mb GDDR3 doesn't require DLL reset. Instead, DLL should

be disabled first before the frequency changed and then change the clock frequency as needed. After the clock frequency changed,
there needed some time till clock become stable and then enable the DLL and then 20K cycle required to lock the DLL

Clock frequency change sequence after the power-up(example)

Command

Wait until

CK,CK

700Mbps

1000Mbps

EMRS

DLL Disable

clock stable

EMRS
DLL Enable

20K cycle for

DLL locking time

Any

Command

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The extended mode register stores the data output driver strength and on-die termination options. The extended mode register is writ-

ten by asserting low on CS, RAS, CAS, WE and high on BA0(The GDDR3 SDRAM should be in all bank precharge with CKE already
high prior to writing into the extended mode register). The state of address pins A0 ~ A11 and BA0,BA1 in the same cycle as CS, RAS,
CAS and WE going low are written in the extended mode register. The minimum clock cycles specified as tMRD are required to com-
plete the write operation in the extended mode register. 4 kinds of the output driver strength are supported by EMRS (A1, A0) code. The
mode register contents can be changed using the same command and clock cycle requirements during operation as long as all banks
are in the idle state. "High" on BA0 is used for EMRS. Refer to the table for specific codes.

DLL

Enable

Disable

Additive Latency

Term

RON

tWR

DLL

tWR

Termination

Drive Strength

~ A

MRS

EMRS

ADDR/CMD Termination

Termination

Default

Half of default

Vendor ID

Off

tWR

Drive Strength

Autocal

Data

Termination

ODT Disabled

Reserved

ZQ/4

ZQ/2

* ZQ : Resistor connection pin for On-die termination

RFU(Reserved for future use) should stay "0" during EMRS cycle

* 1 : ALL ODT will be disabled

Default value is determined by CKE status at
the rising edge of RESET during power-up

Ron of Pull-up

RON

7.4 EXTENDED MODE REGISTER SET(EMRS)

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DLL ENABLE/DISABLE

The DLL must be enabled for normal operation. DLL enable is required during power-up initialization and upon returning to normal oper-
ation after disabling the DLL for debugging or evaluation. (When the device exits self refresh mode, the DLL is enabled automatically.)
Any time the DLL is enabled, 20K clock cycles must occur before an any command can be issued.

DATA TERMINATION

The Data Termination, DT, is used to determine the value of the internal data termination resisters. The GDDR3 SDRAM supports 60

and 120

termination. The termination may also be disabled for testing and other purposes.

DATA DRIVER IMPEDANCE

The Data Driver impedance (DZ) is used to determine the value of the data drivers impedance. When auto calibration is used the data
driver impedance is set to RQ/6 and it's tolerance is determined by the calibration accuracy of the device. When any other value is
selected the target impedance is set nominally to the desired impedance. However, the accuracy is now determined by the device's spe-
cific process corner, applied voltage and operating temperature.

ADDITIVE LATENCY

The Additive Latency function (AL) is used to optimize the command bus efficiency. The AL value is used to determine the number of
clock cycles that is to be added to CL after CAS is captured by the rising edge of CK. Thus the total CAS latency is determined by add-
ing CL and AL.

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DON'T CARE

TRANSITIONING DATA

Tb3

Tc4

Td5

Te6

Ta2

Tf7

RES

CKE

COMMAND

DQ[3:0]

High

Vendor Code

>20ns

200 cycle

MRD

Precharge

All Banks

Dummy_MRS

w/ specified value

EMRS

Vendor_ID

MRS

1st

Auto Refresh

Precharge

All Banks

EMRS

Vendor_ID

Off

~ ~

~ ~
~ ~

~ ~

~ ~
~ ~

~ ~

~ ~
~ ~

~ ~

~ ~
~ ~

~ ~

~ ~
~ ~

~ ~

~ ~
~ ~

~ ~

The Manufacturers Vendor Code, V, is selected by issuing a EXTENDED MODE REGISTER SET command with bits A10 set to one,
and bits A0-A9 and A11 set to the desired values. When the V function is enabled the GDDR3 SDRAM will provide its manufacturers
vendor code on DQ[3:0] and revision identification on DQ[7:4]

Manufacturer

DQ[3:0]

Reserved

Samsung

Infineon

Elpida

Etron

Nanya

Manufacturer

DQ[3:0]

Hynix

Mosel

Winbond

ESMT

Reserved

Manufacturer

DQ[3:0]

Reserved

Micron

7.5 MANUFACTURERS VENDOR CODE AND REVISION IDENTIFICATION

Vendor ID Read

256M GDDR3 SDRAM

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NOP

PRE

MRS

PRE

NOP

tFCHG

tRP

Frequency

Change

All Banks

Precharge

DLL

Reset

tMRD

All Banks

Precharge

20tCK (DLL locking time)

CMD

Both existing tCK and desired tCK are in DLL-On mode
- Change frequency from existing frequency to desired frequency
- Issue Precharge All Banks command
- Issue MRS command to reset the DLL while other fields are valid and required 20K tCK to lock the DLL
- Issue Precharge All Banks command. Issue at least Auto-Refresh command

Existing tCK is in DLL-on mode while desired tCK is in DLL-off mode
- Issue Precharge All Banks command
- Issue EMRS command to disable the DLL
- Issue Precharge All Banks command
- Change the frequency from existing to desired.
- Issue Auto-Refresh command at least two. Issue MRS command

EMRS

PRE

NOP

MRS

NOP

tFCHG

Frequency

Change

CMD

tRP

All Banks

Precharge

DLL

OFF

tMRD

All Banks

Precharge

Clock frequency change in case existing tCK is in DLL-off mode while desired tCK is in DLL-on mode
- Issue Precharge All Banks command and issue EMRS command to disable the DLL.
- Issue Precharge All Banks command.
- Change the clock frequency from existing to desired
- Issue Precharge All Banks command.
- Issue EMRS command to enable the DLL
- Issue MRS command to reset the DLL and required 20K tCK to lock the DLL.
- Issue Precharge All Banks command.
- Issue Auto-Refresh command at least two

EMRS

PRE

NOP

PRE

EMRS

MRS

PRE

NOP

tFCHG

tRP

Frequency

Change

All Banks

Precharge

DLL

tMRD

All Banks

Precharge

20tCK (DLL locking time)

CMD

DLL

Reset

tMRD

tRP

All Banks

Precharge

DLL

OFF

tMRD

All Banks

Precharge

7.6 Clock frequency change sequence during the device operation

256M GDDR3 SDRAM

K4J55323QG

Rev. 1.1 November 2005

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Figure 1. Internal Block Diagram (Reference Only)

Pins under test

DM0

Tie to Iogic 0

DQS

DQ4

RDQS0

RES (SSH,Scan Shift)

CS# (SCK, Scan Clock)

MF (SOE#, Output Enable)

RFU at V-4 (SEN, Scan Enable)

WDQS0 (SOUT,Scan Out)

Puts device into scan mode and re-maps pins to scan functionality

Dedicated Scan Flops

(1per signal under test)

The following lists the rest of the signals on the scan chain:
DQ[3:0], DQ[31:6], RDQS[3:1], WDQS[3:1], DM[3:1], RFU,
CAS#, WE#, CKE, BA[1:0], A[11:0], CK, CK# and ZQ

Two RFU's(J-2 and J-3 on 136-ball package) and one
RFM(H-10 on 136-ball package) will be on the scan chain
and will be read as a logic "0"

The following lists signals not on the scan chain:
NC, VDD, VSS, VDDQ, VSSQ, VREF

In case ZQ pin is connected to the external resistor, it will
be read as logic "0". However, if the ZQ pin is open, it will
be read as floating. Accordingly, ZQ pin should be driven
by any signal.

GENERAL INFORMATION

The 256Mb GDDR3 incorporates a modified boundary scan test mode as an optional feature. This mode doesn't operate in accor-
dance with IEEE Standard 1149.1 - 1990. To save the current GDDR3 ball-out, this mode will scan parallel data input and output and
the scanned data through WDQS0 pin controlled by an add-on pin, SEN which is located at V4 of 136 ball package.
For the normal device operation other than boundary scan, there required device re-initialization by device power-off and then power-on.

DISABLING THE SCAN FEATURE

It is possible to operate the 256Mb GDDR3 without using the boundary scan feature. SEN(at V-4 of 136 ball package) should be tied
LOW(VSS) to prevent the device from entering the boundary scan mode. The other pins which are used for scan mode, RES, MF,
WDQS0 and CS# will be operating at normal GDDR3 function when SEN is de-asserted.

7.7 BOUNDARY SCAN FUNCTION

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BOUNDARY SCAN EXIT ORDER

*Note :
1. When the device is in scan mode, the mirror function will be disabled and none of the pins are remapped.
2. Since the other input of the MUX for DM0 tied to GND, the device will output the continuous zeros after scanning a bit #67, if the chip stays in scan shift mode.
3. Two RFU balls(#56and #57) and one RFM ball(#20) in the scan order will be read as a logic"0".

SCAN PIN DESCRIPTION

*Note :
1. When SEN is asserted, no commands are to be executed by the GDDR3 SDRAM. This applies to both user commands and manufacturing commands which may exist

while RES is de-asserted.

2. All scan functionalities are valid only after the appropriate power-up and initialization sequence. (RES and CKE, to set the ODT of the C/A)
3. In scan mode, the ODT for the address and control lines set to a nominal termination value of ZQ. The ODT for DQ's will be disabled. It is not necessary for the termination

to be calibrated.

4. In a double-load clam-shell configuration, SEN will be asserted to both devices. Separate two SOE's should be provided to top and bottom devices to access the scanned

output. When either of the devices is in scan mode, SOE for the other device which not in a scan will be disabled.

BIT#

BALL

BIT#

BALL

BIT#

BALL

BIT#

BALL

BIT#

BALL

BIT#

BALL

D-3

E-10

K-11

R-10

L-3

G-4

C-2

F-10

K-10

T-11

M-2

F-4

C-3

E-11

K-9

T-10

M-4

F-2

B-2

G-10

M-9

T-3

K-4

G-3

B-3

F-11

M-11

T-2

K-3

E-2

A-4

G-9

L-10

R-3

K-2

F-3

B-10

H-9

N-11

R-2

L-4

E-3

B-11

H-10

M-10

P-3

J-3

C-10

H-11

N-10

P-2

J-2

C-11

J-11

P-11

N-3

H-2

D-10

J-10

P-10

M-3

H-3

D-11

L-9

R-11

N-2

H-4

Package Ball

Symbol

Normal

Function

Type

Description

V-9

SSH

RES

Input

Scan shift.
Capture the data input from the pad at logic LOW and shift the data on the
chain at logic HIGH.

F-9

SCK

Input

Scan Clock. Not a true clock, could be a single pulse or series of pulses.
All scan inputs will be referenced to rising edge of the scan clock.

D-2

SOUT

WDQS0

Output

Scan Output.

V-4

SEN

RFU

Input

Scan Enable.
Logic HIGH would enable the device into scan mode and will be disabled at
logic LOW. Must be tied to GND when not in use.

A-9

SOE

Input

Scan Output Enable.
Enables (registered LOW) and disables (registered HIGH) SOUT data.
This pin will be tied to VDD or GND through a resistor (typically 1K

) for

normal operation. Tester needs to overdrive this pin guarantee the required
input logic level in scan mode.

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SCAN AC ELECTRICAL CHARACTERISTICS

*Note : 1. The parameter applies only when SEN is asserted.
2. Scan Enable should be issued earlier than other Scan Commands by 3ns.

PARAMETER/CONDITON

SYMBOL

MIN

MAX

UNITS

NOTES

Clock
Clock cycle time

tSCK

Scan Command Time
Scan enable setup time

tSES

1,2

Scan enable hold time

tSEH

Scan command setup time for SSH, SOE# and SOUT

tSCS

Scan command hold time for SSH, SOE# and SOUT

tSCH

Scan Capture Time
Scan capture setup Time

tSDS

Scan capture hold Time

tSCH

Scan Shift Time
Scan clock to valid scan output

tSAC

Scan clock to scan output hold

tSOH

1.5

tATS

tSCS

tSCH

tSCS

tSCH

tSDS tSDH

VALID

tSDS tSDH

VALID

tSES

tSDS tSDH

VALID

tSCS

T = 200us

RESET at power - up

Boundary Scan Mode

Scan Out

Bit0

tSCS

VDD

VDDQ

VREF

RES

(SSH in Scan Mode)

CKE

(Dual-load C/A)

CKE

(Quad-load C/A)

SEN

SCK

SOE#

SOUT

Pins Under Test

Note : To set the pre-defined ODT for C/A, a boundary scan mode should be issued after an appropriate ODT initialization sequence with RES and CKE signals

Figure 4. Scan Initialization Sequence

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The GDDR3 SDRAM provides a mirror function (MF) ball to change the physical location of the control lines and all address lines
which helps to route devices back to back. The MF ball will affect RAS, CAS, WE, CS and CKE on balls H3, F4, H9, F9 and H4
respectively and A0, A1, A2, A3, A4, A5, A6, A7, A8, A9, A10, A11, BA0 and BA1 on balls K4, H2, K3, M4, K9, H11, K10, L9, K11, M9,
K2, L4, G4 and G9 respectively and only detects a DC input. The MF ball should be tied directly to VSS or VDD depending on the control
line orientation desired. When the MF ball is tied low the ball orientation is as follows, RAS - H3, CAS - F4, WE - H9, CS - F9, CKE -
H4, A0 - K4, A1 - H2, A2 - K3, A3 - M4, A4 - K9, A5 - H11, A6 - K10, A7 - L9, A8 - K11, A9 - M9, A10 - K2, A11 - L4, BA0 - G4 and
BA1 - G9. The high condition on the MF ball will change the location of the control balls as follows; CS - F4, CAS - F9, RAS - H10, WE
- H4, CKE - H9, A0 - K9, A1 - H11, A2 - K10, A3 - M9, A4 - K4, A5 - H2, A6 - K3, A7 - L4, A8 - K2, A9 - M4, A10 - K11,
A11 - L9, BA0 - G9 and BA1 - G4.

Mirror Function Signal Mapping

PIN

MF LOGIC STATE

HIGH

LOW

RAS

H10

CAS

CKE

H11

K10

H11

K10

K11

A10

K11

A11

BA0

BA1

7.8 Mirror Function

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Before any READ or WRITE commands can be issued to a banks within the GDDR3 SDRAM, a
row in that bank must be "opened." This is accomplished via the ACTIVE command, which selects
both the bank and the row to be activated.
After a row is opened with an ACTIVE command, a READ or WRITE command may be issued to
that row, subject to the t

RCD

specification. t

RCD(min)

should be divided by the clock period and

rounded up to the next whole number to determine the earliest clock edge after the ACTIVE com-
mand in which a READ or WRITE command can be entered. For example, a t

RCD

specification of

16ns with a 800MHz clock (1.25ns period) results in 12.8 clocks rounded to 13. This is reflected in
below figure, which covers any case where 12<t

RCD(min)

13.

The same procedure is used to convert other specification limits from time units to clock cycles).
A subsequent ACTIVE command to a different row in the same bank can only be issued after the
previous active row has been "closed"(precharged). The minimum time interval between successive
ACTIVE commands to the same bank is defined by t

A subsequent ACTIVE command to another bank can be issued while the first bank is being
accessed, which results in a reduction of total row access overhead. The minimum time interval
between successive ACTIVE commands to different banks is defined by t

RRD

/CK

CKE

/CS

/RAS

/CAS

/WE

A0-A11

BA0,BA1

HIGH

RA = Row Address

BA = Bank Address

Activating a Specific Row

in a Specific Bank

T12

/CK

COMMAND

T13

A0-A11

T14

ACT

NOP

ACT

NOP

RD/WR

NOP

Row

Col

BA0,BA1

Bank x

Bank y

RRD

RCD

DON'T CARE

Example : Meeting t

RCD

7.9.1 BANK/ROW ACTIVATION

7.9 OPERATIONS

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READ bursts are initiated with a READ command, as below figure. The starting column
and bank addresses are provided with the READ command and auto precharge is either
enabled or disabled for that burst access. If auto precharge is enabled, the row being
accessed is precharged at the completion of the burst after t

RAS(min)

has been met. For

the generic READ commands used in the following illustrations, auto precharge is dis-
abled.

During READ bursts, the valid data-out element from the starting column address will
be available following the CAS Latency after the READ command. Each subsequent
data-out element will be valid nominally at the next positive or negative strobe edge.
READ burst figure shows general timing for 2 of the possible CAS latency settings. The
GDDR3(x32) drives the output data edge aligned to the crossing of CK and /CK and to
RDQS. The initial HIGH transition LOW of RDQS is known as the read preamble ; the
half cycle coincident with the last data-out element is known as the read postamble.

Upon completion of a burst, assuming no other commands have been initiated, the DQs
will go High-Z. A detailed explanation of t

DQSQ

(valid data-out skew), t

(data-out win-

dow hold), the valid data window are depicted in Data Output Timing (1) figure. A
detailed explanation of t

(DQS and DQ transition skew to CK) is shown in Data Output

Timing (2) figure.

Data from any READ burst may be concatenated with data from a subsequent READ
command. A continuous flow of data can be maintained. The first data element from the
new burst follows the last element of a completed burst. The new READ command
should be issued x cycles after the first READ command, where x equals the number of
data element nibbles (nibbles are required by the 4n-prefetch architecture) depending
on the burst length. This is shown in consecutive READ bursts figure. Nonconsecutive
read data is shown for illustration in nonconsecutive READ bursts figure. Full-speed ran-
dom read accesses within a page (or pages) can be performed as shown in Random
READ accesses figure. Data from a READ burst cannot be terminated or truncated.

During READ commands the GDDR3 Dram disables its data terminators.

/CK
CK

EN AP

DIS AP

/CS

/RAS

/CAS

/WE

A0-A7, A9

A10, A11

BA0, BA1

CA = Column Address
BA = Bank Address
EN AP = Enable Auto Precharge
DIS AP = Disable Auto Precharge

CKE

HIGH

DON'T CARE

READ Command

7.9.2 READs

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T2n

T3n

CK#

RDQS

1.6

DQ(Last data valid)

DQ(First data no longer valid)

All DQs and RDQS, collectively

DQSQ

(MAX)

T2n

T3n

T2n

T3n

T2n

T3n

DQSQ

(MIN)

DQSQ

(MAX)

DQSQ

(MIN)

DQSH

DQSL

Data Output Timing (1) - t

DQSQ

, t

and Data Valid Window

Data Output Timing (2) - t

DQSQ

, t

and Data Valid Window

T2n

T3n

CK#

RDQS

1.6

All DQs and RDQS, collectively

T2n

T3n

DQSH

DQSL

T2n

T3n

(MAX)

DQSH

DQSL

(MIN)

All DQs and RDQS, collectively

RDQS

1.6

Note : 1. t

DQSQ

represents the skew between the 8 DQ lines and the respective RDQS pin.

2. t

DQSQ

is derived at each RDQS clock edge and is not cumulative over time and begins with first DQ transition and ends

with the last valid transition of DQs.
3. t

is show in the nominal case

4. t

DQHP

is the lesser of tDQSL or tDQSH strobe transition collectively when a bank is active.

5. The data valid window is derived for each RDQS transitions and is defined by t

6. There are 4 RDQS pins for this device with RDQS0 in relation to DQ0-DQ7, RDQS1 in relation DQ8-DQ15, RDQS2 in
relation to DQ16-24 and RDQS3 in relation to DQ25-DQ31.
7. This diagram only represents one of the four byte lanes.
8. t

represents the relationship between DQ, RDQS to the crossing of CK and /CK.

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WRITE bursts are initiated with a WRITE command, as shown in Figure. The starting
column and bank addresses are provided with the WRITE command, and auto pre-
charge is either enabled or disabled for that access. If auto precharge is enabled, the
row being accessed is precharged at the completion of the burst. For the generic
WRITE commands used in the following illustrations, auto precharge is disabled.

During WRITE bursts, the first valid data-in element will be registered in a rising
edge of WDQS following the WRITE latency set in the mode register and subsequent
data elements will be registered on successive edges of WDQS. Prior to the first valid
WDQS edge a half cycle is needed and specified as the WRITE Preamble; the half
cycle in WDQS following the last data-in element is known as the write postamble.

The time between the WRITE command and the first valid falling edge of WDQS
(t

DQSS

) is specified with a relative to the write latency. All of the WRITE diagrams

show the nominal case, and where the two extreme cases (i.e., t

DQSS(min)

and

DQSS(max)

) might not be intuitive, they have also been included. Write Burst figure

shows the nominal case and the extremes of tDQSS for a burst of 4. Upon comple-
tion of a burst, assuming no other commands have been initiated, the DQs will
remain High-Z and any additional input data will be ignored. Data for any WRITE
burst may not be truncated with a subsequent WRITE command. The new WRITE
command can be issued on any positive edge of clock following the previous WRITE
command after the burst has completed. The new WRITE command should be
issued x cycles after the first WRITE command should be equals the number of
desired nibbles (nibbles are required by 4n-prefetch architecture).

An example of nonconsecutive WRITEs is shown in Nonconsecutive WRITE to
READ figure. Full-speed random write accesses within a page or pages can be per-
formed as shown in Random WRITE cycles figure. Data for any WRITE burst may be
followed by a subsequent READ command.

Data for any WRITE burst may be followed by a subsequent PRECHARGE com-
mand. To follow a WRITE the WRITE burst, t

should be met as shown in WRITE to

PRECHARGE figure.

Data for any WRITE burst can not be truncated by a subsequent PRECHARGE com-
mand.

/CK

EN AP

DIS AP

/CS

/RAS

/CAS

/WE

A0-A7, A9

A10, A11

BA0, BA1

CKE

HIGH

WRITE Command

CA = Column Address
BA = Bank Address
EN AP = Enable Auto Precharge
DIS AP = Disable Auto Precharge

DON'T CARE

7.9.3 WRITEs

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WRITE to READ

DON'T CARE

TRANSITIONING DATA

NOTE

NOP

WRITE

T3n

/CK

COMMAND

ADDRESS

Bank

Col b

DQSS

NOP

T4n

WDQS

T10

READ

T17

T18

NOP

DQSS

(NOM)

Bank a.

Col n

CL = 8

RDQS

DQSS

WDQS

DQSS

(MIN)

CL = 8

RDQS

DQSS

WDQS

DQSS

(MAX)

CL = 8

RDQS

tCDLR = 5

T18n

1. DI b = data-in for column b.
2. Three subsequent elements of data-in the programmed order following DI b.
3. A burst of 4 is shown.
4. t

CDLR

is referenced from the first positive CK edge after the last data-in pair.

5. The READ and WRITE commands are to the same device. However, the READ and WRITE commands may be
to different devices, in which case t

CDLR

is not required and the READ command could be applied earlier.

6. A8 is LOW with the WRITE command (auto precharge is disabled).
7. WRITE latency is set to 3

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The PRECHARGE command is used to deactivate the open row in a particular
bank or the open row in all banks. The bank(s) will be available for a subsequent
row access some specified time (t

) after the PRECHARGE command is

issued. Input A8 determines whether one or all banks are to be precharged, and
in the case where only one bank is to be precharged, inputs BA0, BA1 select the
bank. When all banks are to be precharged, inputs BA0, BA1 are treated as
"Don't Care." Once a bank has been precharged, it is in the idle state and must
be activated prior to any READ or WRITE commands being issued to the bank.

ALL BANKS

ONE BANK

/CS

/RAS

/CAS

/WE

A0-A7, A9-A11

BA0, BA1

BA=Bank Address

/CK

CKE

HIGH

DON'T CARE

(if A8 is LOW; otherwise "Don't Care")

PRECHARGE Command

NOP

VALID

Ta0

Ta1

Ta2

/CK

COMMAND

VALID

Ta7

CKE

PDEX

No PEAD/WRITE

access in progress

* Enter power - down mode

Exit power - down mode

Power-Down

* Once the device enters the power down mode, it should be in NOP state at least for 10ns

Unlike SDR SDRAMs,GDDR3(x32) SDRAM requires CKE to be active at all
times an access is in progress; from the issuing of a READ or WRITE command
until completion of the burst. For READs, a burst completion is defined when the
Read Postamble is satisfied; For WRITEs, a burst completion is defined BL/2
cycles after the Write Postamble is satisfied.

Power-down is entered when CKE is registered LOW. If power-down occurs
when there is a row active in any bank, this mode is referred to as active power-
down. Entering power-down deactivates the input and output buffers, excluding
CK,/CK and CKE. For maximum power savings, the user has the option of dis-
abling the DLL prior to entering power-down. However, power-down duration is
limited by the refresh requirements of the device, so in most applications,the self-
refresh mode is preferred over the DLL-disabled power-down mode.

When in power-down, CKE LOW and a stable clock signal must be maintained at
the inputs of the GDDR3 SDRAM, while all other input signals are "Don't Care"
except data terminator disable command.

The power-down state is synchronously exited when CKE is registered HIGH (in
conjunction with a NOP or DESELECT command). A valid executable command
may be applied tPDEX later.

7.9.5 POWER-DOWN (CKE NOT ACTIVE)

7.9.4 PRECHARGE

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TRUTH TABLE - Clock Enable (CKE)

Note :
1. CKEn is the logic state of CKE at clock edge n; CKEn-1was the state of CKE at the previous clock edge.
2. Current state is the state of the GDDR3(x32) immediately prior to clock edge n.
3. COMMANDn is the command registered at clock edge n, and ACTIONn is a result of COMMANDn
4. All state and sequence not shown are illegal or reserved.

CKEn-1

CKEn

CURRENT STATE

COMMANDn

ACTIONn

NOTES

Power-Down

Maintain Power-Down

Self Refresh

Maintain Self Refresh

Power-Down

DESELECT or NOP

Exit Power-Down

Self Refresh

DESELECT or NOP

Exit Self Refresh

All Banks Idle

DESELECT or NOP

Precharge Power-Down Entry

Bank(s) Active

DESELECT or NOP

Active Power-Down Entry

All Banks Idle

AUTO REFRESH

Self Refresh Entry

TRUTH TABLE - CURRENT STATE BANK n

- COMMAND TO BANK n

Note :
1. This table applies when CKE

n-1

was HIGH and CKE

is HIGH (see CKE Truth Table) and after t

XSNR

has been met

(if the previous state was self refresh).

2. This table is bank-specific, except where noted (i.e., the current state is for a specific bank and the commands shown are those allowed to be issued

to that bank when in that state). Exceptions are covered in the notes below.

3. Current state definitions :
Idle : The bank has been precharged, and t

has been met.

Row Active : A row in the bank has been activated, and t

RCD

has been met.

No data bursts/accesses and no register accesses are in progress.
Read : A READ burst has been initiated, with auto precharge disabled.
Write : A WRITE burst has been initiated, with auto precharge disabled.

4. The following states must not be interrupted by a command issued to the same bank. COMMAND INHIBIT or NOP commands, or allowable com-

mands to the other bank should be issued on any clock edge occurring during these states. Allowable commands to the other bank are determined by
its current state and truth table- current state bank n -command to bank n. and according to truth table - current state bank n -command to bank m.

Precharging : Starts with registration of a PRECHARGE command and ends when t

is met.

Once t

is met, the bank will be in the idle state.

Row Activating : Starts with registration of an ACTIVE command and ends when t

RCD

is met.

Once t

RCD

is met, the bank will be in the :row active" state.

CURRENT STATE

/CS

/RAS /CAS

/WE

COMMAND/ ACTION

NOTES

Any

DESELECT (NOP/ continue previous operation)

NO OPERATION (NOP/continue previous operation)

DATA TERMINATOR DISABLE

Idle

ACTIVE (Select and activate row)

AUTO REFRESH

Row Active

LOAD MODE REGISTER

READ (Select column and start READ burst)

WRITE (Select Column and start WRITE burst)

PRECHARGE (Deactivate row in bank or banks)

Read

(Auto-Precharge

Disable)

READ (Select column and start new READ burst)

WRITE (Select column and start WRITE burst)

10, 12

PRECHARGE (Only after the READ burst is complete)

Write

(Auto-Precharge

Disabled)

READ (Select column and start READ burst)

10, 11

WRITE (Select column and start new WRITE burst)

PRECHARGE (Only after the WRITE burst is complete)

8, 11

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Read w/ Auto- : Starts with registration of an READ command with auto precharge enabled and ends
Precharge Enabled when tRP has been met. Once t

is met, the bank will be in the idle state.

Write w/ Auto- : Starts with registration of a WRITE command with auto precharge enabled and ends
Precharge Enabled when t

has been met. Once t

is met, the bank will be in the idle state.

5. The following states must not be interrupted by any executable command ; COMMAND INHIBIT or NOP commands must be applied on each positive
clock edge during these states.
Refreshing : Starts with registration of an AUTO REFRESH command and ends when t

is met.

Once t

is met, the GDDR3(x32) will be in the all banks idle state.

Accessing Mode : Starts with registration of a LOAD MODE REGISTER command and ends when t

MRD

is met, the GDDR3(x32) SDRAM will be in the all banks idle state.

Precharge All : Starts with registration of a PRECHARGE ALL command and ends when t

is met.

Once t

is met, all banks will be in the idle state.

READ or WRITE : Starts with registration of the ACTIVE command and ends the last valid data nibble.
6. All states and sequences not shown are illegal or reserved.
7. Not bank-specific; requires that all banks are idle, and bursts are not in progress.
8. May or may not be bank-specific ; If multiple banks are to be precharged, each must be in a valid state for precharging.
9. Left blank
10. READs or WRITEs listed in the Command/Action column include READs or WRITEs with auto precharge enabled and READs or WRITEs with auto

precharge disabled.

11. Requires appropriate DM masking.
12. A WRITE command may be applied after the completion of the READ burst.

TRUTH TABLE - CURRENT STATE BANK n

- COMMAND TO BANK m

Note :
1. This table applies when CKEn-1 was HIGH and CKEn is HIGH (see TRUTH TABLE- CKE ) and after t

XSNR

has been met (if the previous state was

self refresh).

2. This table describes alternate bank operation, except where noted (i.e., the current state is for bank n and the commands shown are those allowed

to be issued to bank m, assuming that bank m is in such a state that the given command is allowable). Exceptions are covered in the notes below.

CURRENT STATE

/CS

/RAS /CAS

/WE

COMMAND/ ACTION

NOTES

Any

DESELECT (NOP/ continue previous operation)

NO OPERATION (NOP/continue previous operation)

DATA TERMINATOR DISABLE

Idle

Any Command Otherwise Allowed to Bank m

Row Activating,

Active, or

Prechrging

ACTIVE (Select and activate row)

READ (Select column and start READ burst)

WRITE (Select Column and start WRITE burst)

PRECHARGE

Read

(Auto-Precharge

Disable)

ACTIVE (Select and activate row)

READ (Select column and start new READ burst)

WRITE (Select column and start WRITE burst)

PRECHARGE

Write

(Auto-Precharge

Disabled)

ACTIVE (Select and activate row)

READ (Select column and start READ burst)

6, 7

WRITE (Select column and start new WRITE burst)

PRECHARGE

Read
(With

Auto-Precharge)

ACTIVE (Select and activate row)

READ (Select column and start new READ burst)

WRITE (Select column and start WRITE burst)

PRECHARGE

Write
(With

Auto-Precharge)

ACTIVE (Select and activate row)

READ (Select column and start READ burst)

WRITE (Select column and start new WRITE burst)

PRECHARGE

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Rev. 1.1 November 2005

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3. Current state definitions :

Idle : The bank has been precharged, and t

has been met.

Row Active : A row in the bank has been activated, and t

RCD

has been met.

No data bursts/accesses and no register accesses are in progress.

Read : A READ burst has been initiated, with auto precharge disabled.

Write : A WRITE burst has been initiated, with auto precharge disabled.

Read w/ Auto- : See following text
Precharge Enabled

Write w/ Auto- : See following text
Precharge Enabled

3a. The read with auto precharge enabled or write with auto precharge enabled states can each be broken into two parts : the access period and the

precharge period. For read with auto precharge, the precharge period is defined as if the same burst was executed with auto precharge disabled
and then followed with the earliest possible PRECHARGE command that still accesses all of the data in the burst. For write with auto precharge, the
precharge period begins when tWR ends, with tWR command and ends where the precharge period (or t

) begins. During the precharge period of

the read with auto precharge enabled or write with auto precharge enabled states, ACTIVE, PRECHARGE, READ and WRITE commands to the
other bank may be applied. In either case, all other related Limitations apply (e.g., contention between read data write data must be avoided).

3b. The minimum delay from a READ or WRITE command with auto precharge enabled, to a command to a different bank is summarized below.

4. AUTO REFRESH and LOAD MODE REGISTER commands may only be issued when all banks are idle.
5. All states and sequences not shown are illegal or reserved.
6. READs or WRITEs listed in the Command/Action column include READs or WRITEs with auto precharge enabled and READs or WRITEs with auto

precharge disabled.

7. Requires appropriate DM masking.

From Command

To Command

Minimum delay (with concurrent auto precharge)

WRITE w/AP

READ or READ w/AP

[WL + (BL/2)] tCK + tWR

WRITE or WRITE w/AP

(BL/2) * tCK

PRECHARGE

1 tCK

ACTIVE

1 tCK

READ w/AP

READ or READ w/AP

(BL/2) * tCK

WRITE or WRITE w/AP

[CL

+ (BL/2)] + 1 - WL * tCK

PRECHARGE

1 tCK

ACTIVE

1 tCK

256M GDDR3 SDRAM

K4J55323QG

Rev. 1.1 November 2005

45 of 53

TRUTH TABLE - COMMANDs

Name (Function)

RAS

CAS

ADDR

NOTES

DESELECT (NOP)

8, 11

NO OPERATION (NOP)

ACTIVE (Select bank and activate row)

Bank/Row

READ (Select bank and column, and start READ burst)

Bank/Col

WRITE (Select bank and column, and start WRITE burst)

Bank/Col

PRECHARGE (Deactivate row in bank or banks)

Code

AUTO REFRESH or SELF REFRESH (Enter self refresh mode)

6, 7

LOAD MODE REGISTER

Op-Code

DATA TERMINATOR DISABLE

Below Truth table-COMMANDs provides a quick reference of available commands. This is followed by a verbal description of each
command. Two additional Truth Tables appear following the operation section : these tables provide current state/next state information.

TRUTH TABLE - DM Operation

Note :
1. CKE is HIGH for all commands except SELF REFRESH.
2. BA0 and BA1 select either the mode register or the extended mode register (BA0=0, BA1=0 select the mode register; BA0=1, BA1=0 select

extended mode register; other combinations of BA0~BA1 are reserved). A0~A11 provide the op-code to be written to the selected mode register.

3. BA0 and BA1 provide bank address and A0~A11 provide row address.
4. BA0 and BA1 provide bank address; A0~A7 and A9 provide column address; A8 HIGH enables the auto precharge feature (nonpersistent) , and A8

LOW disables the auto precharge feature.

5. A8 LOW : BA0 and BA1 determine which banks are precharged.
A8 HIGH : All banks are precharged.
6. This command is AUTO REFRESH if CKE is HIGH, SELF REFRESH if CKE is LOW.
7. Internal refresh counter controls row addressing; ll inputs and I/Os are "Don't Care" except for CKE.
8. DESELECT and NOP are functionally interchangeable.
9. Cannot be in powerdown or self-refresh state.
10. Used to mask write data ; provided coincident with the corresponding data.
11. Except DATA Termination disable.

Name (Function)

DQS

NOTES

Write Enable

Valid

Write Inhibit

DESELECT

The DESELECT function (/CS high) prevents new commands from being executed by the GDDR3(x32). The GDDR3(x32) SDRAM is
effectively deselected. Operations already in progress are not affected.

NO OPERATION (NOP)

The NO OPERATION (NOP) command is used to instruct selected GDDR3(x32) to perform a NOP (/CS LOW). This prevents
unwanted commands from being registered during idle or wait states. Operations already in progress are not affected.

LOAD MODE REGISTER

The mode registers are loaded via inputs A0-A11. See mode register descriptions in the Register Definition section. The Load Mode
Register command can only be issued when all banks are idle, and a subsequent executable command cannot be issued until tMRD is
met.

ACTIVE

The ACTIVE command is used to open (or activate) a row in a particular bank for a subsequent access. The value on the BA0 and
BA1 inputs selects the bank, and the address provided on inputsA0-A11 selects the row. This row remains active (or open) for
accesses until a PRECHARGE command is issued to that bank. A PRECHARGE command must be issued before opening a different
row in the same bank.

9.0 COMMANDS

256M GDDR3 SDRAM

K4J55323QG

Rev. 1.1 November 2005

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READ

The READ command is used to initiate a burst read access to an active row. The value on the BA0 and BA1 inputs select the bank, and
the address provided on inputs A0-A7, A9 selects the starting column location. The value on input A8 determines whether or not auto
precharge is used. If auto precharge is selected, the row being accessed will be precharged at the end of the READ burst; if auto pre-
charge is not selected, the row will remain open for subsequent accesses.

WRITE

The WRITE command is used to initiate a burst write access to an active row. The value on the BA0 and BA1 inputs select the bank,
and the address provided on inputs A0-A7, A9 selects the starting column location. The value on inputs A8 determines whether or not
auto precharge is used. If auto precharge is selected, the row being accessed will be precharged at the end of the WRITE burst; if auto
precharge is not selected, the row will remain open for subsequent accesses. Input data appearing on the DQs is written to the memory
array subject to the DM input logic level appearing coincident with the data. If a given DM signal is registered LOW. the corresponding
data will be written to memory; If the DM signal is registered HIGH, the corresponding data inputs will be ignored, and a WRITE will not
be executed to that byte/column location.

PRECHARGE

The PRECHARGE command is used to deactivate the open row in a particular bank or the open row in all banks. The bank(s) will be
available for a subsequent row access a specified time (t

) after the PRECHARGE command is issued. Input A8 determines whether

one or all banks are to be precharged, and in the case where only one banks are to be precharged, inputs BA0,BA1 select the bank.
Otherwise BA0, BA1 are treated as "Don't Care." Once a bank has been precharged, it is in the idle state and must be activated prior
to any READ or WRITE command will be treated as a NOP if there is no open row is already in the process of precharging.

AUTO PRECHARGE

Auto precharge is a feature which performs the same individual-bank precharge function described above, but without requiring an
explicit command. This is accomplished by using A8 to enable auto precharge in conjunction with a specific READ or WRITE com-
mand. A precharge of the bank/row that is addressed with the READ or WRITE command is automatically performed upon completion
of the READ or WRITE burst. Auto precharge is non persistent in that it is either enable or disabled for each individual READ or WRITE
command. Auto precharge ensures that the precharge is initiated at the earliest valid state within a burst. This "earliest valid stage" is
determined as if an explicit PRECHARGE command was issued at the earliest possible time, without violating t

RAS(min)

, as described

for each burst type in the Operation section of this data sheet. The user must not issue another command to the same bank until the
precharge time(t

) is completed.

AUTO REFRESH

Auto Refresh is used during normal operation of the GDDR3 SDRAM and is analogous to /CAS-BEFORE-/RAS (CBR) REFRESH in
FPM/EDO DRAMs. This command is non persistent, so it must be issued each time a refresh is required. The addressing is generated
by the internal refresh controller. This makes the address bits a "Don't Care" during an Auto Refresh command. The 256Mb(x32)
GDDR3 requires Auto Refresh cycles at an average interval of 3.9us (maximum).
A maximum Auto Refresh commands can be posted to any given GDDR3(x32) SDRAM, meaning that the maximum absolute interval
between any Auto Refresh command and the next Auto Refresh command is 9 x 3.9us(35.1us). This maximum absolute interval is to
allow GDDR3(x32) SDRAM output drivers and internal terminators to automatically re calibrate compensating for voltage and tempera-
ture changes.

SELF REFRESH

The SELF REFRESH command can be used to retain data in the GDDR3(x32) SDRAM ,even if the rest of the system is powered
down. When in the self refresh mode,the GDDR3(x32) SDRAM retains data without external clocking. The SELF REFRESH command
is initiated like an AUTO REFRESH command except CKE is disabled (LOW). The DLL is automatically disabled upon entering SELF
REFRESH and is automatically enabled and reset upon exiting SELF REFRESH. The active termination is also disabled upon entering
Self Refresh and enabled upon exiting Self Refresh. (20K clock cycles must then occur before a READ command can be issued). Input
signals except CKE are "Don't Care" during SELF REFRESH. The procedure for exiting self refresh requires a sequence of commands.
First, CK and /CK must be stable prior to CKE going back HIGH. Once CKE is HIGH,the GDDR3(x32) must have NOP commands
issued for tXSNR because tine is required for the completion of any internal refresh in progress. A simple algorithm for meeting both
refresh, DLL requirements and out-put calibration is to apply NOPs for 20K clock cycles before applying any other command to allow
the DLL to lock and the output drivers to recalibrate.

256M GDDR3 SDRAM

K4J55323QG

Rev. 1.1 November 2005

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DATA TERMINATION DISABLE
(BUS SNOOPING FOR READ COMMAND)

The DATA TERMINATOR DISABLE COMMAND is detected by the device by snooping the bus for READ commands excluding /CS.
The GDDR3 DRAM will disable its Data terminators when a READ command is detected. The terminators are disable CL-1 Clocks after
the READ command is detected. In a two rank system both dram devices will snoop the bus for READ commands to either device and
both will disable their terminators if a READ command is detected. The command and address terminators and always enabled.

ON-DIE TERMINATION

Bus snooping for READ commands other than /CS is used to control the on-die termination in the dual load configuration. The GDDR3
SDRAM will disable the on-die termination when a READ command is detected, regardless of the state of
/CS, when the ODT for the DQ pins are set for dual loads (120

The on-die termination is disabled x clocks after the READ command

where x equals CL-1 and stay off for a duration of BL/2 + 2, as below figure, Data Termination Disable Timing. In a two-rank system, both
DRAM devices snoop the bus for READ commands to either device and both will disable the on-die termination if a READ command is
detected. The on-die termination for all other pins on the device are always on for both a single-rank system and a dual-rank system.

The on-die termination value on address and control pins is determined during power-up in relation to the state of CKE on the first tran-
sition of RESET. On the rising edge of RESET, if CKE is sampled LOW, then the configuration is determined to be a single-rank system.
The on-die termination is then set to one-half ZQ for the address pins. On the rising edge of RESET, if CKE is sampled HIGH, then the
configuration is determined to be a dual-rank system. The on-die termination for the DQs, WDQS, and DM pins is set in the EMRS.

NOP

READ

T8n

T9n

T10

T11

CK#
CK

COMMAND

ADDRESS

RDQS

Bank a,

Col n

CL = 8

TERMINATION

GDDR3 Data Termination is Disabled

Data Termination Disable Timing

Note : 1. DO n = data-out from column n.
2. Burst length = 4.
3. Three subsequent elements of data-out appear in the specified order following DO n.
4. Shown with nominal t

and t

DQSQ

5. RDQS will start driving high one-half cycle prior to the first falling edge.
6. The Data Terminators are disabled starting at CL-1 and the duration is BL/2 + 2
7. READS to either rank disable both ranks' termination regardless of the logic level of /CS.

DON'T CARE

TRANSITIONING DATA

256M GDDR3 SDRAM

K4J55323QG

Rev. 1.1 November 2005

48 of 53

Recommended operating conditions (Voltage referenced to 0

°C Tc 85°C ; VDD=1.8V + 0.1V, VDDQ=1.8V + 0.1V)

Note :
1. Under all conditions, VDDQ must be less than or equal to VDD.
2. VREF is expected to equal 70% of VDDQ for the transmitting device and to track variations in the DC level of the same. Peak-to-peak noise on VREF

may not exceed + 2 percent of the DC value. Thus, from 70% of VDDQ, VREF is allowed + 25mV for DC error and an additional +25mV for AC noise.

3. The DC values define where the input slew rate requirements are imposed, and the input signal must not violate these levels in order to maintain a valid

level. The inputs require the AC value to be achieved during signal transition edge and the driver should achieve the same slew rate through the AC
values.

4. Input and output slew rate =3V/ns. If the input slew rate is less than 3V/ns, input timing may be compromised. All slew rate are measured between

Vih and Vil. DQ and DM input slew rate must not deviate from DQS by more than 10%. If the DQ,DM and DQS slew rate is less than 3V/ns, timing is
longer than referenced to the mid-point but to the VIL(AC) maximum and VIH(AC) minimum points.

5. VIH overshoot : VIH(max) = VDDQ + 0.5V for a pulse width

500ps and the pulse width can not be greater than 1/3 of the cycle rate.

VIL undershoot : VIL(min)=0.0V for a pulse width

500ps and the pulse width can not be greater than 1/3 of the cycle rate.

Parameter

Symbol

Min

Typ

Max

Unit

Note

Device Supply voltage

1.7

1.8

1.9

Output Supply voltage

DDQ

1.7

1.8

1.9

Reference voltage

REF

0.69*V

DDQ

0.71*V

DDQ

DC Input logic high voltage

IH (DC)

REF

+0.15

DC Input logic low voltage

IL (DC)

REF

-0.15

Output logic low voltage

OL(DC)

0.76

AC Input logic high voltage

IH(AC)

REF

+0.25

3,4,5

AC Input logic low voltage

IL(AC)

REF

-0.25

3,4,5

Input leakage current
Any input 0V-<V

-< V

DDQ

(All other pins not under test = 0V)

-5

Output leakage current
(DQs are disabled ; 0V-<V

OUT

-< V

DDQ

)

IOZ

-5

Note :
Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rat-
ing only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this
specification is not implied. Exposure periods may affect reliability.

Parameter

Symbol

Value

Unit

Voltage on any pin relative to Vss

, V

OUT

-0.5 ~ V

DDQ

+ 0.5V

Voltage on V

supply relative to Vss

-0.5 ~ 2.5

Voltage on V

DDQ

supply relative to Vss

DDQ

-0.5 ~ 2.5

MAX Junction Temperature

+125

°C

Storage temperature

STG

-55 ~ +150

°C

Power dissipation

TBD

Short Circuit Output Current

10.2 POWER & DC OPERATING CONDITIONS

10.0 AC & DC OPERATING CONDITIONS

10.1 ABSOLUTE MAXIMUM RATINGS

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K4J55323QG

Rev. 1.1 November 2005

49 of 53

Recommended operating conditions (

°C Tc 85°C ; VDD=1.8V + 0.1V, VDDQ=1.8V + 0.1V

)

Note :
1. This provides a minimum of 1.16V to a maximum of 1.36V, and is always 70% of VDDQ
2. For AC operations, all DC clock requirements must be satisfied as well.
3. The value of VIX is expected to equal 70% VDDQ for the transmitting device and must track variations in the DC level of the same.
4.

VID is the magnitude of the difference between the input level in CK and the input level on /CK.

5. The CK and /CK input reference level (for timing referenced to CK and /CK) is the point at which CK and /CK cross; the input reference level for signals

other than CK and /CK is VREF.

6. CK and /CK input slew rate must be > 3V/ns

Parameter/ Condition

Symbol

Min

Max

Unit

Note

Clock Input Mid-Point Voltage ; CK and /CK

MP(DC)

1.16

1.36

1,2,3

Clock Input Voltage Level; CK and /CK

IN(DC)

0.42

DDQ

+ 0.3

Clock Input Differential Voltage ; CK and /CK

ID(DC)

0.22

DDQ

+ 0.5

2,4

Clock Input Differential Voltage ; CK and /CK

ID(AC)

0.22

DDQ

+ 0.3

Clock Input Crossing Point Voltage ; CK and /CK

IX(AC)

REF

- 0.15

REF

+ 0.15

Note : 1 . Outputs measured into equivalent load of 10pf at a driver impedance of 40

GDDR3

REF

240

1.26V

=60

DDQ

10pf

Output Load Circuit

10.3 CLOCK INPUT OPERATING CONDITIONS

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K4J55323QG

Rev. 1.1 November 2005

50 of 53

(

°C Tc 85°C ; VDD=1.8V + 0.1V, VDDQ=1.8V + 0.1V

)

Note :
1. Measured with outputs open and ODT off
2. Refresh period is 32ms

Parameter

Symbol

Test Condition

Version

Unit

-12

-14

-16

-20

Operating Current
(One Bank Active)

CC1

Burst Length=4 t

(min)

=0mA, t

= t

(min)

440

420

410

400

Precharge Standby Current
in Power-down mode

CC2

CKE

(max), t

= t

(min)

100

Precharge Standby Current
in Non Power-down mode

CC2

CKE

(min), CS

(min),

= t

(min)

220

200

180

160

Active Standby Current
power-down mode

CC3

CKE

(max), t

= t

(min)

120

110

100

Active Standby Current in
in Non Power-down mode

CC3

CKE

VIH(min), CS VIH(min),

= t

(min)

350

320

310

300

Operating Current
( Burst Mode)

CC4

=0mA ,t

= t

(min),

Page Burst, All Banks activated.

900

820

750

650

Refresh Current

CC5

RFC

510

480

460

440

Self Refresh Current

CC6

CKE

0.2V

Operating Current
(4Bank interleaving)

CC7

Burst Length=4 t

(min)

=0mA,

(min)

1050

935

860

830

(VDD=1.8V, TA= 25

°C, f=1MHz)

Parameter

Symbol

Min

Max

Unit

Input capacitance (

CK, CK )

IN1

1.5

Input capacitance (A

, BA

~BA

)

IN2

1.5

Input capacitance
(

CKE, CS, RAS,CAS, WE )

IN3

1.5

Data & DQS input/output capacitance(DQ

~DQ

)

OUT

1.5

Input capacitance(DM0 ~ DM3)

IN4

1.5

10.5 CAPACITANCE

10.4 DC CHARACTERISTICS

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K4J55323QG

Rev. 1.1 November 2005

51 of 53

Note :
1. The WRITE latency can be set from 1 to 7 clocks. When the WRITE latency is set to 1 or 2 or 3 clocks(this case can be used regardless of frequency),

the input buffers are turned on during the ACTIVE commands reducing the latency but added power. When the WRITE latency is set to 4 ~7 clocks ,
the input buffers are turned on during the WRITE commands for lower power operation. The WRITE latency which is over 4 clocks can be used only in
case that Write Latency*tCK is greater than 7ns.

2. A low to high transition on the WDQS line is not allowed in the half clock prior to the write preamble.
3. The last rising edge of WDQS after the write postamble must be riven high by the controller. WDQS can not be pulled high by the on-die termination

alone.

4. tHZ and tLZ transitions occur in the same access time windows as valid data transitions. These parameters are not referenced to a specific voltage

level, but specify when the device output is no longer driving (HZ) or begins driving (LZ).

5. The cycle to cycle jitter over 1~6 cycle short term jitter

Parameter

Symbol

-12

-14

-16

-20

Unit

Note

Min

Max

Min

Max

Min

Max

Min

Max

DQS out access time from CK

DQSCK

-0.23

+0.23

-0.26

+0.26

-0.29

+0.29

-0.35

+0.35

CK high-level width

0.45

0.55

0.45

0.55

0.45

0.55

0.45

0.55

tCK

CK low-level width

0.45

0.55

0.45

0.55

0.45

0.55

0.45

0.55

tCK

CK cycle time

CL=11

1.25

3.3

CL=10

1.4

CL=9

1.6

CL=8

2.0

CL=7

2.0

WRITE Latency

tCK

DQ and DM input hold time relative to DQS

0.16

0.18

0.20

0.25

DQ and DM input setup time relative to DQS

0.16

0.18

0.20

0.25

Active termination setup time

ATS

Active termination hold time

ATH

DQS input high pulse width

tDQSH

0.48

0.52

0.48

0.52

0.48

0.52

0.48

0.52

tCK

DQS input low pulse widthl

tDQSL

0.48

0.52

0.48

0.52

0.48

0.52

0.48

0.52

tCK

Data strobe edge to Dout edge

tDQSQ

-0.140

0.140

-0.160

0.160

0.180 0.180 0.225

0.225

DQS read preamble

tRPRE

0.4

0.6

0.4

0.6

0.4

0.6

0.4

0.6

tCK

DQS read postamble

tRPST

0.4

0.6

0.4

0.6

0.4

0.6

0.4

0.6

tCK

Write command to first DQS latching transition

tDQSS

WL-0.2 WL+0.2 WL-0.2 WL+0.2

WL-0.2

WL+0.2

WL-0.2

WL+0.2

tCK

DQS write preamble

tWPRE

0.35

0.4

0.6

0.4

0.6

0.4

0.6

tCK

DQS write preamble setup time

tWPRES

DQS write postamble

tWPST

0.4

0.6

0.4

0.6

0.4

0.6

0.4

0.6

tCK

Half strobe period

tHP

tCLmin

tCHmin

tCLmin

tCHmin

tCLmin

tCHmin

tCLmin

tCHmin

tCK

Data output hold time from DQS

tQH

0.14

0.16

0.18

0.225

Data-out high-impedance window
from CK and /CK

tHZ

-0.3

Data-out low-impedance window from
CK and /CK

tLZ

-0.3

Address and control input hold time

tIH

0.3

0.35

0.4

0.5

Address and control input setup time

tIS

0.3

0.35

0.4

0.5

Address and control input pulse width

tIPW

0.9

1.0

1.1

1.3

Jitter over 1~6 clock cycle error

0.03

tCK

Cycle to cyde duty cycle error

tDCERR

0.03

tCK

Rise and fall times of CK

tR, tF

0.2

tCK

10.6 AC CHARACTERISTICS(I-I)

256M GDDR3 SDRAM

K4J55323QG

Rev. 1.1 November 2005

52 of 53

AC CHARACTERISTICS (II)

Parameter

Symbol

-12

-14

-16

-20

Unit Note

Min

Max

Min

Max

Min

Max

Min

Max

Row active time

tRAS

100K

tCK

Row cycle time

tRC

tCK

Refresh row cycle time

tRFC

tCK

RAS to CAS delay for Read

tRCDR

tCK

RAS to CAS delay for Write

tRCDW

tCK

Row precharge time

tRP

tCK

Row active to Row active

tRRD

tCK

Last data in to Row precharge (PRE or Auto-PRE)

tWR

tCK

Last data in to Read command

tCDLR

tCK

Mode register set cycle time

tMRD

tCK

Auto precharge write recovery time + Precharge

tDAL

tCK

Exit self refresh to Read command

tXSR

20000

tCK

Power-down exit time

tPDEX

7tCK

+tIS

6tCK

+tIS

6tCK

+tIS

4tCK

+tIS

tCK

Refresh interval time

tREF

7.8

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