- 1 -
256M GDDR3 SDRAM
K4J55323QF-GC
Rev 1.8 (Apr. 2005)
256Mbit GDDR3 SDRAM
Revision 1.8
April 2005
Samsung Electronics reserves the right to change products or specification without notice.
INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS,
AND IS SUBJECT TO CHANGE WITHOUT NOTICE.
NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE,
EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE,
TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY. ALL
INFORMATION IN THIS DOCUMENT IS PROVIDED
ON AS "AS IS" BASIS WITHOUT GUARANTEE OR WARRANTY OF ANY KIND.
1. For updates or additional information about Samsung products, contact your nearest Samsung office.
2. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar
applications where Product failure could result in loss of life or personal or physical harm, or any military or
defense application, or any governmental procurement to which special terms or provisions may apply.
- 2 -
256M GDDR3 SDRAM
K4J55323QF-GC
Rev 1.8 (Apr. 2005)
Revision History
Revision 1.8 (April 9, 2005)
- Modified note description for the Write Latency on page 47.
Revision 1.7 (Jan. 18 , 2005)
- Added Lead Free package part number in the data sheet.
Revision 1.6 (Dec 2 , 2004)
- Changed ICC2P and ICC6 for all frequency. Separted ICC6 for -GC and -GL.
Revision 1.5 (Oct 5 , 2004)
- Added K4J55323QF-G(V)C15
- Timing diagram corrected on page 28
Revision 1.4 (July 9 , 2004)
- Added K4J55323QF-G(V)L20 which is VDD&VDDQ=1.8V(typical)
Revision 1.3 (June 14 , 2004)
- Changed DC spec value for all the frequency. Refer to the DC characteristics of page 45.
- Removed -GC12 from the spec.
Revision 1.2 (February 18 , 2004)
- Changed VDD/VDDQ from 1.9V+ 0.1V to 2.0V+ 0.1V in all frequencies.
- DC changes : Refer to the DC characteristics of page 45.
Revision 1.1 (January 29 , 2004)
- Typo corrected
Revision 1.0 (January 15 , 2004)
- Changed VDD/VDDQ of K4J55323QF-GC12 from 2.1V+ 0.1V to 1.9V+ 0.1V
- Changed VDD/VDDQ of K4J55323QF-GC14/16/20 from 1.8V+ 0.1V to 1.9V+ 0.1V
- Changed tCK(max) from 3.0ns to 3.3ns
- DC spec finalized. Typo corrected
- 3 -
256M GDDR3 SDRAM
K4J55323QF-GC
Rev 1.8 (Apr. 2005)
Revision History
Revision 0.5 (January 7 , 2004)
- Preliminary spec
- Added "Dummy MRS" command during the power-up sequence. Typo corrected
Revision 0.4 (December 10 , 2003)
- Preliminary spec
- Typo corrected
- Added K4J55323QF-GC12 (800MHz) in the spec
- Key AC parameter changes : Refer to the AC spec table on page 46,47
. Added tDAL in the AC characteristics table,
. Added AC parameter of -GC12 in the AC characteristics table,
. Changed tRC of -GC14 from 31tCK to 30tCK,
. Changed tRFC of -GC16 from 34tCK to 33tCK,
- DC changes : Refer to the DC characteristics table of page 45.
- Capacitance table change : Refer to the Capacitance table of page 45.
Revision 0.3 (November 13, 2003)
- Target Spec
- Typo corrected
- Removed 800MHz from the spec
- Changed ICC6 from 4mA to 7mA
- Key AC parameter changes : Refer to the AC spec table on page 46,47
. Changed tWR of -GC14 from 6tCK to 9tCK,
. Changed tWR of -GC16 from 5tCK to 8tCK,
. Changed tWR of -GC20 from 4tCK to 6tCK
. Changed tPDEX and tXSR at low power from 100tCK to 300tCK
Revision 0.2 (October 17, 2003)
- Target Spec
- Typo corrected
Revision 0.1 (September 26, 2003)
- Target Spec
- Typo corrected
Revision 0.0 (September 25, 2003)
- Target Spec
- 4 -
256M GDDR3 SDRAM
K4J55323QF-GC
Rev 1.8 (Apr. 2005)
2.0V + 0.1V power supply for device operation
2.0V + 0.1V power supply for I/O interface
On-Die Termination (ODT)
Output Driver Strength adjustment by EMRS
Calibrated output drive
Pseudo Open drain compatible inputs/outputs
4 internal banks for concurrent operation
Differential clock inputs (CK and CK)
Commands entered on each positive CK edge
CAS latency : 5, 6, 7, 8 and 9 (clock)
Additive latency (AL): 0 and 1 (clock)
Programmable Burst length : 4
Programmable Write latency : 1, 2, 3, 4, 5 and 6 (clock)
Single ended READ strobe (RDQS) per byte
Single ended WRITE strobe (WDQS) per byte
GENERAL DESCRIPTION
FEATURES
RDQS edge-aligned with data for READs
WDQS center-aligned with data for WRITEs
Data Mask(DM) for masking WRITE data
Auto & Self refresh mode
Auto Precharge option
32ms, auto refresh (4K cycle)
144 Ball FBGA
Maximum clock frequency up to700MHz
Maximum data rate up to 1.4Gbps/pin
DLL for outputs
2M x 32Bit x 4 Banks Graphic Double Data Rate 3 Synchronous DRAM
with Uni-directional Data Strobe
ORDERING INFORMATION
*K4J55323QF-GL20/VL20 : VDD & VDDQ = 1.8V+0.1V(1.7V ~ 1.9V)
*K4J55323QF-V is the Lead Free package part number
Part NO.
Max Freq.
Max Data Rate
Interface
Package
K4J55323QF-GC14
700MHz
1400Mbps/pin
Pseudo
Open Drain
144 - Ball FBGA
K4J55323QF-GC15
667MHz
1334Mbps/pin
K4J55323QF-GC16
600MHz
1200Mbps/pin
K4J55323QF-GC20*
500MHz
1000Mbps/pin
The 8Mx32 GDDR3 is 268,435,456 bits of hyper synchronous data rate Dynamic RAM organized as 4 x 2,097,152 words
by 32 bits, fabricated with SAMSUNG
's
high performance CMOS technology. Synchronous features with Data Strobe allow
extremely high performance up to 5.6GB/s/chip. I/O transactions are possible on both edges of the clock cycle. Range of
operating frequencies, and programmable latencies allow the device to be useful for a variety of high performance memory
system applications.
FOR 2M x 32Bit x 4 Bank GDDR3 SDRAM
- 5 -
256M GDDR3 SDRAM
K4J55323QF-GC
Rev 1.8 (Apr. 2005)
PIN CONFIGURATION
NOTE :
1. RFU1 is reserved for A12
2. RFU2 is reserved for BA2
3. (M,13) VREF for CMD and ADDRESS
4. (M,2) VREF for Data input
DQ23
A3
VDD
VSS
RFU
2
VDD
VDD
RFU
1
VSS
VDD
A4
DQ8
VREF
A2
A10
/RAS
RESET
CKE
RFU5
ZQ
/CS
A9
A5
VREF
A0
A1
A11
BA0
/CAS
CK
/CK
/WE
BA1
A8/AP
A6
A7
2
3
4
5
6
7
8
9
10
11
12
13
B
C
D
E
F
G
H
J
K
L
M
N
WDQS0
RDQS0
VSSQ
DQ3
DQ2
DQ0
DQ31
DQ29
DQ28
VSSQ
RDQS3
WDQS3
DQ4
DM0
VDDQ
VDDQ
DQ1
VDDQ
VDDQ
DQ30
VDDQ
VDDQ
DM3
DQ27
DQ6
DQ5
VSSQ
VSSQ
VSSQ
VDD
VDD
VSSQ
VSSQ
VSSQ
DQ26
DQ25
DQ7
RFU3
VDD
VSS
VSSQ
VSS
VSS
VSSQ
VSS
VDD
RFU4
DQ24
DQ17
DQ16
VDDQ
VSSQ
VSSQ
VDDQ
DQ15
DQ14
NC,
VSS
NC,
VSS
NC,
VSS
NC,
VSS
DQ19
DQ18
VDDQ
VSSQ
VSSQ
VDDQ
DQ13
DQ12
NC,
VSS
NC,
VSS
NC,
VSS
NC,
VSS
WDQS2
RDQS2
VDDQ
VSSQ
VSSQ
VDDQ
RDQS1
WDQS1
NC,
VSS
NC,
VSS
NC,
VSS
NC,
VSS
DQ20
DM2
VDDQ
VSSQ
VSSQ
VDDQ
DM1
DQ11
NC,
VSS
NC,
VSS
NC,
VSS
NC,
VSS
DQ21
DQ22
VDDQ
VSSQ
VSS
VSS
VSS
VSS
VSSQ
VDDQ
DQ9
DQ10
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