DAC1236X
0.25
m 1.8V/2.5V 10-BIT 2MSPS DAC
1
GENERAL DESCRIPTION
DAC1236X is a CMOS 10Bit D/A converter for general application. This digital to analog converter has a R-string
structure.
Its settling time is 500ns (Typical value).
FEATURES
-- Resolution:
10Bit
-- Differential
Linearity
Error:
1.0
LSB
-- Integral
Linearity
Error:
2.0
LSB
-- Settling
Time:
500ns
-- Low
Power
Consumption:
800
A
-- Power
Down
Mode
-- Operation
Temperature
Range:
0
C
~
70
C
-- Power
Supply:
1.8V
Single
(2.5V Operation Available)
TYPICAL APPLICATIONS
-- Hard Disk Drive (HDD)
-- Battery Operated Instruments
-- Motor Control Systems
-- General Applications
0.25
m 1.8V/2.5V 10-BIT 2MSPS DAC
DAC1236X
2
FUNCTIONAL BLOCK DIAGRAM
D[9:0]
10
N
R-String
VRB
VRT
VOUT
CNTRL
PWDN
AMPSEL
VDD18A1
VSS18A1
VDD18A2
VSS18A2
Dout
1-of-2
N
Decoder
Dout
1-of-2
M
Decoder
M
VBBA
2
N
2
M
SEL
SELB
PWDNA
PWDNB
SEL
SEL
SELB
SELB
PWDNA
PWDNB
SW
SW
SW
SW
1.8V
AMP
2.5V
AMP
_
+
_
+
Ver 2.1 (June 2002)
No responsibility is assumed by SEC for its use nor for any infringements of patents or other rights of third parties that may
from its use. The content of this datasheet is subject to without any notice.
DAC1236X
0.25
m 1.8V/2.5V 10-BIT 2MSPS DAC
3
CORE PIN DESCRIPTION (FOR 1.8V)
Name
I/O Type
I/O Pad
Pin Description
D[9:0]
DI
picc_abb
Digital Input Data (10bit)
D[9]: MSB , D[0]: LSB
AMPSEL
DI
picc_abb
Amp Selection (High: 1.8V Amp)
PWDN
DI
picc_abb
Power Down (Active Low)
VRT
AB
pia_abb
Voltage Reference Top
VRB
AB
pia_abb
Voltage Reference Bottom
VOUT
AO
poa_abb
Analog Voltage Output
VDD18A1
AP
vdd1t_abb
Analog Power (+1.8V)
VSS18A1
AG
vdd1t_abb
Analog Ground (0.0V)
VDD18A2
DP
vdd1t_abb
Digital Power (+1.8V)
VSS18A2
DG
vss1t_abb
Digital Ground (0.0V)
VBBA
AG
vbb_abb
Analog Sub Bias (0.0V)
CORE PIN DESCRIPTION (FOR 2.5V)
Name
I/O Type
I/O Pad
Pin Description
D[9:0]
DI
picc_abb
Digital Input Data (10bit)
D[9]: MSB , D[0]: LSB
AMPSEL
DI
picc_abb
Amp Selection (Low: 2.5V Amp)
PWDN
DI
picc_abb
Power Down (Active Low)
VRT
AB
pia_abb
Voltage Reference Top
VRB
AB
pia_abb
Voltage Reference Bottom
VOUT
AO
poa_abb
Analog Voltage Output
VDD18A1
AP
vdd2t_abb
Analog Power (+2.5V)
VSS18A1
AG
vdd2t_abb
Analog Ground (0.0V)
VDD18A2
DP
vdd2t_abb
Digital Power (+2.5V)
VSS18A2
DG
vss2t_abb
Digital Ground (0.0V)
VBBA
AG
vbb_abb
Analog Sub Bias (0.0V)
I/O TYPE ABBR.
-- AI: Analog Input
-- DI: Digital Input
-- AO: Analog Output
-- DO: Digital Output
-- AB: Analog Bidirectional
-- DB: Digital Bidirectional
-- AP: Analog Power
-- DP: Digital Power
-- AG: Analog Ground
-- DG: Digital Ground
0.25
m 1.8V/2.5V 10-BIT 2MSPS DAC
DAC1236X
4
CORE CONFIGURATION
VRT
VRB
D[9:0]
AMPSEL
VOUT
VDD18A1
VSS18A1
VDD18A2
VSS18A2
VBBA
PWDN
dac1236x
(dac1236a)
DAC1236X
0.25
m 1.8V/2.5V 10-BIT 2MSPS DAC
5
ABSOLUTE MAXIMUM RATINGS
Characteristics
Symbol
Value
Unit
Supply Voltage
VDD (VDD18A1,VDD18A2)
3.3
V
Analog Output Voltage
VOUT
VSS18A1 to VDD18A1
V
Digital Input Voltage
D[9:0]
VSS18A2 to VDD18A2
V
Reference Voltage
VRT
VRB
VDD18A1
VSS18A2
V
Operating Temperature Range
Topr
0 to 70
C
NOTES:
1. ABSOLUTE MAXIMUM RATING specifies the values beyond which the device may be damaged permanently. Exposure
to ABSOLUTE MAXIMUM RATING conditions for extended periods may affect reliability. Each condition value is applied
with the other values kept within the following operating conditions and function operation under any of these conditions
is
not implied.
2. All voltages are measured with respect to VSS(VSS18A1 or VSS18A2 or VBBA) unless otherwise specified.
3. 100pF capacitor is discharged through a 1.5k
resistor (Human body model)
RECOMMENDED OPERATING CONDITIONS
Characteristics
Symbol
Min
Typ
Max
Unit
Supply Voltage
(for 1.8V operation)
VDD18A1 - VSS18A1
VDD18A2 - VSS18A2
1.71
1.8
1.89
V
Supply Voltage
(for 2.5V operation)
VDD18A1 - VSS18A1
VDD18A2 - VSS18A2
2.3
2.5
2.7
V
Supply Voltage Difference
VDD18A1 - VDD18A2
-0.1
0.0
0.1
V
Reference Voltage
VRT
VRB
-
VSS18A1
-
-
VDD18A1
-
V
Digital Input 'Low' Voltage
Digital Input 'High' Voltage
VIL
VIH
-
0.7VDD
-
-
0.3VDD
-
V
Operating Temperature
Topr
0
-
70
C
NOTES:
1. It is strongly recommended that to avoid power latch-up all the supply pins (VDD18A1 , VDD18A2) be driven from the
same source.
2. Digital Input : VDD
VDD18A2
0.25
m 1.8V/2.5V 10-BIT 2MSPS DAC
DAC1236X
6
DC LECTRICAL CHARACTERISTICS
(Converter Specifications : VDD18A1=VDD18A2=1.8V, VSS18A1=VSS18A2=VBBA=0V,AMPSEL=High,
PWDN=High, Top=25
C, VRT=1.8V, VRB=0.0V unless otherwise specified.)
Characteristics
Symbol
Min
Typ
Max
Unit
Conditions
Resolution
Bit
-
10
-
Bits
-
Differential Linearity Error
DLE
-
1.0
-
LSB
-
Integral Linearity Error
ILE
-
2.0
-
LSB
-
Zero Scale Error
1
V
ZSE
-
5
-
mV
VRT=1.8V , VRB=0.0V
Full Scale Voltage Error
2
V
FSE
-
5
-
mV
Maximum Output Voltage
V
OMAX
-
1.798
-
V
V
OMAX
=VOUT(D[9:0]=High)
V
LSB
= V
OMAX
/ 1023
LSB Size
V
LSB
-
1.758
-
mV
(Converter Specifications: VDD18A1=VDD18A2=2.5V, VSS18A1=VSS18A2=VBBA=0V, AMPSEL=Low,
PWDN=High, Top=25
C, VRT=2.5V, VRB=0.0V unless otherwise specified.)
Characteristics
Symbol
Min
Typ
Max
Unit
Conditions
Resolution
Bit
-
10
-
Bits
-
Differential Linearity Error
DLE
-
1.0
-
LSB
-
Integral Linearity Error
ILE
-
2.0
-
LSB
-
Zero Scale Error
1
VZSE
-
5
-
mV
VRT=2.5V, VRB=0.0V
Full Scale Voltage Error
2
VFSE
-
5
-
mV
Maximum Output Voltage
V
OMAX
-
2.498
-
V
V
OMAX
=VOUT(D[9:0]=High)
VLSB = V
OMAX
/ 1023
LSB Size
V
LSB
-
2.44
-
mV
NOTES:
1.
VZSE=VOUT(D[9:0]=Low) - VRB
2.
VFSE=VOUT(D[9:0]=High) - {(VRT-VRB) 1023/1024 + VRB}
DAC1236X
0.25
m 1.8V/2.5V 10-BIT 2MSPS DAC
7
AC ELECTRICAL CHARACTERISTICS (FOR 1.8V)
(Converter Specifications: VDD18A1=VDD18A2=1.8V, VSS18A1=VSS18A2=VBBA=0V, load cap=25pF
AMPSEL=High, Top=25
C, VRT=1.75V, VRB=0.05V unless otherwise specified.)
Characteristics
Symbol
Min
Typ
Max
Unit
Conditions
Supply Current
(Power Down Mode)
Ivdd1
-
0.8
-
mA
Ivdd1 = I
VDD18A1
+ I
VDD18A2
VRT=1.8V , VRB = 0.0V
Data Input: All Low or All High
Ivdd2
-
1.22
-
mA
Ivdd2 =I
VDD18A1
+ I
VDD18A2
Data Input: All Low or All High
Ivdd3
-
-
10
A
Ivdd3 = I
VDD18A1
+ I
VDD18A2
Data Rate = 2MHz
Load cap = 25pF,
PWDN=LOW
Reference Current
Ivrt
-
0.8
-
mA
Short Circuit Current
I
SC
-
7
-
mA
VOUT: VSSA or VDDA
Data Input: All High or All Low
Analog Output Delay
Td
-
65
-
ns
Data Rate = 2MHz
Data: All LOW
All HIGH
Analog Output Rise
Time
Tr
-
100
-
ns
Data Rate = 2MHz
Data: All LOW
All HIGH
Analog Output Fall
Time
Tf
-
100
-
ns
Data Rate = 2MHz
Data: All HIGH
All LOW
Analog Output
Settling Time
Ts
-
500
-
ns
Data Rate = 2MHz
Data: All LOW
All HIGH
Power Down On Time
Ton
-
500
-
ns
PWDN: HIGH
LOW
Power Down Off Time
Toff
-
500
-
ns
PWDN: LOW
HIGH
0.25
m 1.8V/2.5V 10-BIT 2MSPS DAC
DAC1236X
8
AC ELECTRICAL CHARACTERISTICS (FOR 2.5V)
(Converter Specifications : VDD18A1=VDD18A2=2.5V, VSS18A1=VSS18A2=VBBA=0V, load cap=25pF
AMPSEL=Low, Top=25
C, VRT=2.45V, VRB=0.05V unless otherwise specified.)
Characteristics
Symbol
Min
Typ
Max
Unit
Conditions
Supply Current
Ivdd1
-
1.2
-
mA
Ivdd1 = I
VDD18A1
+ I
VDD18A2
VRT=1.8V , VRB = 0.0V
Data Input: All Low or All High
Supply Current
Ivdd2
-
1.6
-
mA
Ivdd2 = I
VDD18A1
+ I
VDD18A2
Data Input: All Low or All High
Supply Current
(Power Down Mode)
Ivdd3
-
-
10
uA
Ivdd3 = I
VDD18A1
+ I
VDD18A2
Data Rate = 2MHz
Load cap = 25pF , PWDN=LOW
Reference Current
Ivrt
-
1.2
-
mA
Short Circuit Current
I
SC
-
10
-
mA
VOUT: VSSA or VDDA
Data Input: All High or All Low
Analog Output Delay
Td
-
65
-
ns
Data Rate = 2MHz
Data: All LOW
All HIGH
Analog Output Rise
Time
Tr
-
100
-
ns
Data Rate = 2MHz
Data: All LOW
All HIGH
Analog Output Fall
Time
Tf
-
100
-
ns
Data Rate = 2MHz
Data: All HIGH
All LOW
Analog Output
Settling Time
Ts
-
500
-
ns
Data Rate = 2MHz
Data: All LOW
All HIGH
Power Down On Time
Ton
-
500
-
ns
PWDN: HIGH
LOW
Power Down Off Time
Toff
-
500
-
ns
PWDN: LOW
HIGH
DAC1236X
0.25
m 1.8V/2.5V 10-BIT 2MSPS DAC
9
TIMING DIAGRAM
DATA
VOUT
Td
0000000000
1111111111
50%
50%
VOUT
0000000000
1111111111
0000000000
10%
90%
DATA
Tr
Tf
VOUT
0000000000
1111111111
0000000000
50%
0.5LSB
DATA
Ts
PWDN
VOUT
Ton
50%
Toff
50%
0.5LSB
0.5LSB
0.0V
1. Output delay is measured from the 50% point of the rising edge of input data to the full scale transition.
2. Settling time is measured from the 50% point of full scale transition to the output remaining within
1/2 LSB.
3. Output rise/fall time is measured between the 10% and 90% points of full scale transition.
FUNCTIONAL DESCRIPTION
1. The dac1236x(dac1236a) has a 10bit R-string block, two decoders, two OP amps, and control block.
2. The digital outputs of two decoders decide the voltage level of R-string block.
(
)
V
VRT
VRB
2
D[n]
VRB
Rstring
n
n 0
9
10
2
=
-
+
=
The two OP amps have different supply voltages. One is operated at 1.8V supply voltage and the other is
operated at 2.5V supply voltage. The CNTRL block controls several conditions which are the OP amp
selection,
and power down mode. If you use the dac1236x(dac1236a) at 1.8V supply voltage, next conditions is needed.
(AMPSEL=High, PWDN=High)
4. In power down mode, only analog current (I
VDDA18A1
) is reduced and reference current (Ivrt) is always
dissipated.
5. Normal Conditions (for 1.8V operation): VRT=1.75V , VRB=0.05V, AMPSEL=High , PWDN=High. You can
change the voltages of VRT and VRB to 1.8V and 0.0V , but the performance of dac1236x(dac1236a) will be
degraded. For 2.5V operation: VRT=2.45V , VRB=0.05V , AMPSEL=Low , PWDN=High
0.25
m 1.8V/2.5V 10-BIT 2MSPS DAC
DAC1236X
10
CORE EVALUATION GUIDE (FOR 1.8V)
HOST
DSP
COR
E
MUX
TEST PATH
10
10
10
Cc
Ct
VDD18A2
VSS18A2
VDD18A1
VSS18A1
VBBA
1.8
V
GND
1.8
V
GND
Cc
Ct
Ct
Cc
Ct
Cc
1.75
V
GND
0.05
V
GND
D[9:0]
AMPSEL
PWDN
VRT
VRB
VOUT
dac1236x
(dac1236a)
VOUT
Location
Description
Ct
10uF Tantalum Capacitor
Cc
0.1uF Ceramic Capacitor
TESTABILITY
Whether you use MUX or the internal logic for testability, it is required to be able to select values of digital inputs
(D[9:0]). See above figure. Only if it is, you can check the main function. (Linearity)
Normal Test Condition (for 1.8V operation): VRT=1.75V, VRB=0.05V, AMPSEL=High, PWDN=High
DAC1236X
0.25
m 1.8V/2.5V 10-BIT 2MSPS DAC
11
PHANTOM CELL INFORMATION
dac1236x
(dac1236a)
VDD18A1
VSS18A1
VBBA
VDD18A2
VSS18A2
D[9]
D[8]
D[7]
D[6]
D[5]
D[4]
D[3]
D[2]
D[1]
D[0]
VRB
VRT
VDD18A1
VSS18A1
VBBA
VOUT
AMPSEL
PWDN
dac1236x
(dac1236a)
VDD18A1
VSS18A1
VBBA
VDD18A2
VSS18A2
D[9]
D[8]
D[7]
D[6]
D[5]
D[4]
D[3]
D[2]
D[1]
D[0]
VRB
VRT
VDD18A1
VSS18A1
VBBA
VOUT
AMPSEL
PWDN
Pin Name
Property
Pin Usage
Pin Layout Guide
D[9:0]
DI
Internal /
External
1. Digital Input Signal lines must have same length to
reduce propagation delay.
AMPSEL
DI
Internal /
External
PWDN
DI
Internal /
External
VRT
AB
External
1. Voltage reference lines (VRT and VRB) must be wide metal
to reduce voltage drop of metal lines.
VRB
AB
External
2. VOUT signal should not be crossed by any signals and
should not run next to digital signals to minimize capacitive
coupling between the two signals.
VOUT
AO
Internal /
External
VDD18A1
AP
External
1. It is recommended that you use thick analog power metal.
When connected to PAD, the path should be kept as short
as possible.
VSS18A1
AG
External
2. Digital power and analog power are separately used.
VDD18A2
DP
External
VSS18A2
DG
External
VBBA
AG
External
1.
It is recommended that you use thick analog power metal. when connecting to PAD, the path should be kept as short as
possible.
2. Digital power and analog power are separately used.
3. When the core block is connected to other blocks, it must be double guard-ring using N-well and P+ active to remove
the
substrate and coupling noise. In that case, the power metal should be connected to PAD directly.
4. The Bulk power is used to reduce the influence of substrate noise.
5. Digital input signal lines must be same length to reduce the difference of delay.
0.25
m 1.8V/2.5V 10-BIT 2MSPS DAC
DAC1236X
12
PACKAGE CONFIGURATION (FOR 1.8V)
VRB
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
VDD18A2
VDD18A2
VSS18A2
VSS18A2
NC
NC
NC
D[9]
D[8]
D[7]
D[6]
D[5]
D[4]
D[3]
D[2]
D[1]
D[0]
NC
NC
NC
NC
NC
VRB
VRB
VBBA
VBBA
(TEST PIN)
AMPSEL
VSSZ
VSSZ
VDDZ
VDDZ
NC
VSS18A1
VSS18A1
VDD18A1
VDD18A1
NC
NC
NC
NC
PWDN
VOUT
VOUT
NC
NC
VRT
VRT
Cc
Ct
L1
L2
Cc
Ct
+
+
0.0V
1.8V
(VSS)
(VDD)
+
Ct
Cc
PWDN
VOUT
VRT
(1.75 V Typ.)
(1.8V in normal operation)
Ct
+
Cc
(0.05V Typ.)
D[9]
D[8]
D[7]
D[6]
D[5]
D[4]
D[3]
D[2]
D[1]
D[0]
L3
L5
L4
1.8V
0.0V
DAC
1236
X
(DAC1236A)
VRB
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
VDD18A2
VDD18A2
VSS18A2
VSS18A2
NC
NC
NC
D[9]
D[8]
D[7]
D[6]
D[5]
D[4]
D[3]
D[2]
D[1]
D[0]
NC
NC
NC
NC
NC
VRB
VRB
VBBA
VBBA
(TEST PIN)
AMPSEL
VSSZ
VSSZ
VDDZ
VDDZ
NC
VSS18A1
VSS18A1
VDD18A1
VDD18A1
NC
NC
NC
NC
PWDN
VOUT
VOUT
NC
NC
VRT
VRT
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
VDD18A2
VDD18A2
VSS18A2
VSS18A2
NC
NC
NC
D[9]
D[8]
D[7]
D[6]
D[5]
D[4]
D[3]
D[2]
D[1]
D[0]
NC
NC
NC
NC
NC
VRB
VRB
VBBA
VBBA
(TEST PIN)
AMPSEL
VSSZ
VSSZ
VDDZ
VDDZ
NC
VSS18A1
VSS18A1
VDD18A1
VDD18A1
NC
NC
NC
NC
PWDN
VOUT
VOUT
NC
NC
VRT
VRT
Cc
Ct
L1
L2
Cc
Ct
+
+
0.0V
1.8V
(VSS)
(VDD)
+
Ct
Cc
PWDN
VOUT
VRT
(1.75 V Typ.)
(1.8V in normal operation)
Ct
+
Cc
(0.05V Typ.)
D[9]
D[8]
D[7]
D[6]
D[5]
D[4]
D[3]
D[2]
D[1]
D[0]
L3
L5
L4
1.8V
0.0V
DAC
1236
X
(DAC1236A)
Location
Description
Ct
10uF Tantalum Capacitor
Cc
0.1uF Ceramic Capacitor
L1~L5
Ferrite Bead ( 0.1mh )
DAC1236X
0.25
m 1.8V/2.5V 10-BIT 2MSPS DAC
13
PACKAGE CONFIGURATION (FOR 2.5V)
VRB
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
VDD18A2
VDD18A2
VSS18A2
VSS18A2
NC
NC
NC
D[9]
D[8]
D[7]
D[6]
D[5]
D[4]
D[3]
D[2]
D[1]
D[0]
NC
NC
NC
NC
NC
VRB
VRB
VBBA
VBBA
(TEST PIN)
AMPSEL
VSSZ
VSSZ
VDDZ
VDDZ
NC
VSS18A1
VSS18A1
VDD18A1
VDD18A1
NC
NC
NC
NC
PWDN
VOUT
VOUT
NC
NC
VRT
VRT
Cc
Ct
L1
L2
Cc
Ct
+
+
0.0V
2.5V
(VSS)
(VDD)
+
Ct
Cc
PWDN
VOUT
VRT
(2.45V Typ.)
(2.5V in normal operation)
Ct
+
Cc
(0.05V Typ.)
D[9]
D[8]
D[7]
D[6]
D[5]
D[4]
D[3]
D[2]
D[1]
D[0]
L3
L5
L4
0.0V
0.0V
DAC1236X
(DAC1236A)
VRB
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
VDD18A2
VDD18A2
VSS18A2
VSS18A2
NC
NC
NC
D[9]
D[8]
D[7]
D[6]
D[5]
D[4]
D[3]
D[2]
D[1]
D[0]
NC
NC
NC
NC
NC
VRB
VRB
VBBA
VBBA
(TEST PIN)
AMPSEL
VSSZ
VSSZ
VDDZ
VDDZ
NC
VSS18A1
VSS18A1
VDD18A1
VDD18A1
NC
NC
NC
NC
PWDN
VOUT
VOUT
NC
NC
VRT
VRT
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
VDD18A2
VDD18A2
VSS18A2
VSS18A2
NC
NC
NC
D[9]
D[8]
D[7]
D[6]
D[5]
D[4]
D[3]
D[2]
D[1]
D[0]
NC
NC
NC
NC
NC
VRB
VRB
VBBA
VBBA
(TEST PIN)
AMPSEL
VSSZ
VSSZ
VDDZ
VDDZ
NC
VSS18A1
VSS18A1
VDD18A1
VDD18A1
NC
NC
NC
NC
PWDN
VOUT
VOUT
NC
NC
VRT
VRT
Cc
Ct
L1
L2
Cc
Ct
+
+
0.0V
2.5V
(VSS)
(VDD)
+
Ct
Cc
PWDN
VOUT
VRT
(2.45V Typ.)
(2.5V in normal operation)
Ct
+
Cc
(0.05V Typ.)
D[9]
D[8]
D[7]
D[6]
D[5]
D[4]
D[3]
D[2]
D[1]
D[0]
L3
L5
L4
0.0V
0.0V
DAC1236X
(DAC1236A)
Location
Description
Ct
10uF Tantalum Capacitor
Cc
0.1uF Ceramic Capacitor
L1~L5
Ferrite Bead ( 0.1mh )
0.25
m 1.8V/2.5V 10-BIT 2MSPS DAC
DAC1236X
14
PACKAGE PIN DESCRIPTION
Name
Pin No
I/O Type
Pin Description
VDD18A2
1,2
DP
Digital Power (1.8V)
VSS18A2
3,4
DG
Digital Ground (0.0V)
D[9:0]
8~17
DI
Digital Input Data
VRB
23,24
AB
Voltage Reference Bottom (0.05V)
VRT
25,26
AB
Voltage Reference Top (1.75V)
VOUT
29,30
AO
Analog Voltage Output
PWDN
31
DI
Power Down Mode (Low Active)
VDD18A1
36,37
AP
Analog Power (1.8V)
VSS18A1
38,39
AG
Analog Ground (0.0V)
VDDZ
41,42
AP
Pad Power (1.8V)
VSSZ
43,44
AG
Pad Ground (0.0V)
AMPSEL
45
DI
Amp Selection Mode (High: 1.8V Amp Selected)
(TEST PIN)
46
DI
This pin must be connected to ground (0.0V)
VBBA
47,48
AG
Analog Sub Bias (0.0V)
NC
5,6,7,18,19
20,21,22,27
28,32,33,34
35,40
DO
No Connection
I/O TYPE ABBR.
-- AI: Analog Input
-- DI: Digital Input
-- AO: Analog Output
-- DO: Digital Output
-- AB: Analog Bidirectional
-- DB: Digital Bidirectional
-- AP: Analog Power
-- DP: Digital Power
-- AG: Analog Ground
-- DG: Digital Ground
DAC1236X
0.25
m 1.8V/2.5V 10-BIT 2MSPS DAC
15
PC BOARD LAYOUT CONSIDERATION
1. PC BOARD CONSIDERATIONS
To minimize noise on the power lines and the ground lines, the digital inputs need to be shielded and decoupled.
This trace length between groups of VDD (VDD18A1,VDD18A2) and VSS (VSS18A1,VSS18A2) pins should be
as short as possible so as to minimize inductive ringing.
2. SUPPLY DECOUPLING AND PLANES
For the decoupling capacitor between the power line and the ground line, 0.1uF ceramic capacitor is used in
parallel with a 10uF tantalum capacitor.
The digital power plane(VDD18A2) and analog power plane(VDD18A1) are connected through a ferrite bead, and
also the digital ground plane(VSS18A2) and the analog ground plane(VSS18A1). This ferrite bead should be
located within 3inches of the DAC1236X(DAC1236A). The analog power plane supplies power to the
DAC1236X(DAC1236A) of the analog output pin and related devices.
0.25
m 1.8V/2.5V 10-BIT 2MSPS DAC
DAC1236X
16
FEEDBACK REQUEST
We appreciate your interest in out products. you have further questions, please specify in the attached form.
Thank you very much.
DC/AC Electrical Characteristic
Characteristics
Min
Typ
Max
Unit
Remarks
Supply Voltage
V
Power dissipation
mW
Resolution
Bits
Analog Output Voltage
V
Operating Temperature
C
Output Load Capacitor
pF
Output Load Resistor
k
Integral Non-Linearity Error
LSB
Differential Non-Linearity Error
LSB
Maximum Conversion Rate
MHz
Voltage Output DAC
Reference Voltage TOP
BOTTOM
V
Analog Output Voltage Range
V
Digital Input Format
Binary Code or 2's Complement Code
Current Output DAC
Analog Output Maximum Current
mA
Analog Output Maximum Signal
Frequency
kHz
Reference Voltage
V
External Resistor for Current
Setting(RSET)
W
Pipeline Delay
sec
--
Do you want power down mode?
--
Do you want internal reference voltage (BGR)?
--
Which do you want serial input data type or parallel input data type?
--
Do you need 3.3V or 5V power supply in your system?
DAC1236X
0.25
m 1.8V/2.5V 10-BIT 2MSPS DAC
17
HISTORY CARD
Version
Date
Modified Items
Comments
Ver 1.4
99.12.14
Version updated.
All pictures and texts are modified with dac1253x's data sheet.
The format ant fonts of data sheet are same with dac1253x's
data sheet.
Reference data
sheet
DAC1253X
Ver 1.5
Version updated.
Lee Jong Hwa modified the data sheet of dac1236x for
Coactive application. But it is not regular version
Ver 1.6
00.02.22
Version updated
page 4: AMPSEL=Low
AMPSEL=High
page 5: formula modified
page 8: dac1236x(core name)
DAC1236X (chip name)
AMPSEL: 0.0V
1.8V
page 9: VRT/VRB: AI
AB (same with page 2)
VBBA: AB
AG
Ver 1.7
00.08.10
Version updated
page 7: Pin description table is added.
page 12: History card is added.
Ver 1.8
01.03.28
Version Updated
page 11:
C
K
(Output Load Resistor)
Ver 1.9
02.04.04
Version Updated
page 3 : 2.5V operation
page 4 : 2.5V operation
page 6 : 2.5V operation
page 7 : Functional Description Modified
page 11: W
W (External Resistor for Current setting(RSET))
page 11: Internal
Internal
Ver 2.0
02.05.06
Version updated
2.5V spec. and diagrams are added.
Ver 2.1
03.06.20
Version updated
Page 5: measured
is measured
Page 11: additional questions are modified.
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