DAC0415X

0.18

m 16/20/24-BIT 44.1/32/48kHZ SIGMA-DELTA STEREO DAC

GENERAL DESCRIPTION

This product is Sigma-Delta Digital-To-Analog Converter for High grade Digital Audio Applications. The product

contains Serial-to-Parallel Interface Converter and Compensation Filter, Digital Volume Attenuator by the Mode

Interface, De-Emphasis Filter, FIR filter, Sinc Filter, Digital Sigma-Delta Modulator, Analog Postfilter, AIF (Anti-

Image-Filter). The normal input and output channels provides 95dB SNR (Signal to Noise Ratio) over in band (20kHz :

Sampling Rate = 44.1KHz).

The product employs the 1bit 4th-order Sigma-Delta architecture with 16bit resolution, over sampling of 64X. And

Analog Postfilter with low clock sensitivity and Linear phase, filters the Shaping-Nosie and outputs Analog voltage

with high resolution. An on-chip reference voltage is included to allow single supply operations.

FEATURES

-- 16/20/24bit Sigma-Delta Digital

-to-

Analog Converter

-- Sampling Frequency Rate 32/44.1/48kHz
-- Input Rate 1Fs or 2Fs by Normal Mode/Double
-- Mode Selection
-- On-Chip Compensation Filter
-- On-Chip 4 times Oversampling Digital Filter
-- On-Chip Analog Postfilter
-- Filtered Line-Level Outputs, Linear Phase Filtering
-- On-Chip Voltage Reference
-- Low Clock Jitter Sensitivity
-- 96dB SNR
-- L/R Independent Digital Soft Attenuation
-- On-Chip De-Emphasis Filter (32/44.1/48kHz)
-- Zero Input Detection Mute
-- Soft Mute Control
-- Mono/Stereo Setting
-- Single 1.8V / 3.3V(Digital/Analog) Power Supply

APPLICATIONS

-- CD Player, CD-ROM, MP3 Player, Video-CD, Mini-Disk, DVD etc.

0.18

m 16/20/24-BIT 44.1/32/48kHZ SIGMA-DELTA STEREO DAC

DAC0415X

BLOCK DIAGRAM

AVDD18D AVSS18D

AVDD33A AVSS33A

S/P

Converter

Attenuator

Compensation

Filter

De-emphsis

FIR Filter

Sinc Filter

Sigma-Delta

Modulator

DAC

Analog

Postfilter

Anti-

Imaging

Filter

Mode Interface & Timing Control

Test Mode Interface

Voltage

Reference

MSCK

BCK

LRCK

SDATA

ZDENH

AOUTL

VCOMML(I)*

VCOMCL(I)*

VCOML(I)*

VREFML(I)*

VREFPL(I)*

VHALF(O)*

VREFIN(I)*

VREF(O)*

VREFPR(I)*

VREFMR(I)*

VCOMR(I)*

VCOMCR(I)*

VCOMMR(I)*

AOUTR

MODE

MCKDEM MDAFS1

MLDFS0

DN IIS

IFS

MUTEL

ZDENL RSTB

PDL

IDNUM<3...0>

BISTONP

SDIAG

SERRORB

TSEL

OFS64

ODSL ODSR IFS64 IADSL IADSR

IFEF(B)*

(I)* : Input

(O)* : Output

(B)* : Bidirection

Ver 4.1 (Feb. 2002)

This data sheet is a preliminary version. No responsibility is assumed by SEC for its use nor for any infringements of

patents or other rights of third parties that may result from its use. The content of this data sheet is subject to

change without any notice.

DAC0415X

0.18

m 16/20/24-BIT 44.1/32/48kHZ SIGMA-DELTA STEREO DAC

EMBEDDED CORE BLOCK DIAGRAM

Audio Processor

(DSP)

dac0415x

MSCK

BCK

LRCK
SDATA

MODE
MCKDEM

MDAFS1

MLDFS0
DN

IIS

IFS
MUTEL

ZDENL

RSTB
PDL

IDNUM<3:0>

ZDENH

BISTONP

TSEL

IFS64
IADSL

IADSR

External

Inputs

MUX_SEL

AVSS18D

These are test pins for internal blocks of the core.

So you don't need the internal test mode.
Make the test control pins disable ('L') state and

Output and bidirectional pins leave floating.

AOUTL

AOUTR

VHALF

VREF

VREFIN This pin must be

connected to VHALF

PAD

External

VCOML

VCOMCL

VCOMML

VREFPL

VCOMR

VCOMCR

VCOMMR

VREFPR

Each ports must be

connected to VREF
PAD

VREFML

VREFMR

Each ports must be

connected to
AVSS33A PAD

IREF

SDIAG

SERRORB

OFS64

ODSL

ODSR

0.18

m 16/20/24-BIT 44.1/32/48kHZ SIGMA-DELTA STEREO DAC

DAC0415X

EMBEDDED CORE USER GUIDE

-- Digital serial data input and clock input refer to digital input format.
-- Digital control pins inform refer to pin description.
-- Mode I/F pin inform refer to Mode Interface. IDNUM<3:0> are ID number setting pins for Mode Interface.
-- External application of analog output pins refer to application circuit.
-- If you want to test only embedded analog core block (Sigma-Delta DAC), you can do it just adding the 4 pins to

supply digital serial input data (MSCK, BCK, LRCK, SDATA) and MUX block.

-- Analog power(AVDD33A,AVSS33A) and digital power(AVDD18D,AVSS18D) should be separated.
-- Bulk Power pin should be connected to analog ground(AVSS33A).
-- Two pads should be dedicated to analog power(AVDD33A, AVSS33A)
-- If you need not use test mode for the testability of internal core block, you make internal core block test pins

disable state. (Test Input pins are 'L' state and Test output, bi-direction pins leave floating)

DAC0415X

0.18

m 16/20/24-BIT 44.1/32/48kHZ SIGMA-DELTA STEREO DAC

CORE PIN DESCRIPTION

Pin Name

I/O Type

I/O Pad

Pin Description

Power Supply Pins
AVDD18D

vdd1t_abb

Digital Supply

AVSS18D

vss1t_abb

Digital Ground

AVDD33A

vdd3t_abb

Analog Supply

AVSS33A

vss3t_abb

Analog Ground

Digital Pins
MSCK

picc_abb

Master Clock Input.

BCK

picc_abb

Bit Clock Input.

LRCK

picc_abb

Sample Rate Clock Input. (Fs or 2Fs)

SDATA

picc_abb

Serial Digital Input

ZDENH

pob2_abb

Zero Data Detection Output

When Input Data is continuously zero for more than 4096*sampling

time(fs), ZDENH becomes to H.

MODE

picc_abb

SoftWare / HardWare Control Select ("H" / "L")

MCKDEM
(MCLK/DEEM)

picc_abb

Mode Interface Clock Input / De-Emphasis On/Off. "H" is enabled.

"L" is disabled.

(When MODE pin is "H", MCLK is active. When MODE pin is "L",

DEEM is active)

MDAFS1
(MDATA/SFS1)

picc_abb

Mode Interface Command Data Input / De-Emphasis Frequency

Selection1

(When MODE pin is "H", MDATA is active. When MODE pin is "L",

SFS1 is active)

MLDFS0
(MLD/SFS0)

picc_abb

Mode Interface Command load Input(when low,load) / De-Emphasis

Frequency Selection0

(When MODE pin is "H", MLD is active. When MODE pin is "L",

SFS0 is active)

picc_abb

Input Rate Select. High is Double(2Fs) Mode, Low is Normal(Fs)

Mode.