bw1221l.gul
Ver 1.1 (Dec. 1998)
No responsibility is assumed by SEC for its use nor for any
infringements of patents or other rights of third parties that may
result from its use. The content of this datasheet is subject to
change without any notice.
GENERAL DESCRIPTION
The BW1221L is a CMOS Dual 10Bit D/A
converter for general & video applications.
Its maximum conversion rate is 80MSPS
(typical 50MSPS) and supply voltage is
3.3V single. An external 1.0V voltage
reference(VREF) and a single resistor
(RSET) control the full_scale output current.
FEATURES
- 80MSPS 1CLK pipeline delay operation
- +3.3V CMOS monolothic construction
- 0.4LSB differential linearity error(Typ)
- 1.5LSB integral linearity error(Typ)
- External voltage reference
- Dual Channel DAC
- 10-Bit voltage parallel input per channel
- High impedance single current output
- Bineary coding input
- High impedance analog output current
source
FUNCTIONAL BLOCK DIAGRAM
TYPICAL APPLICATIONS
- High Definition Television(DTV,HDTV)
- High Resolution Color Graphics
- Hard Disk Driver(HDD)
- CAE/CAD/CAM
- Image Processing
- Instrumentation
- Conventional Digital to Analog Conversion
CLKGEN
OPA
CM
D2[9:0]
CLK
VREF
IREF
PD
IO2
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D1[9:0]
1 / 13
10BIT 80MSPS DUAL DAC
BW1221L
SAMSUNG ELECTRONICS Co. LTD
SEC ASIC
BW1221L
10BIT 80MSPS Dual DAC
ANALOG
NAME
I/O
TYPE
I/O PAD
PIN DESCRIPTION
D1[9:0]
DI
picc_bb
1st Channel Digital input
D2[9:0]
DI
picc_bb
2nd Channel Digital input
IO1
AO
poa_bb
1st Channel Current Output
IO2
AO
poa_bb
2nd Channel Current Output
CLK
DI
picc_bb
Clock Input
VREF
AI
pia_bb
Reference voltage input
COMP
AI
pia_bb
External capacitance connection
PD
DI
picc_bb
Power-Down High Enable
IREF
AI
pia_bb
external resistor connection
VDDA
AP
vdda
Analog Power
VDDD
DP
vddd
Digital Power
VSSA
AG
vssa
Analog Ground
VSSD
DG
vssd
Digital Ground
VBB
AG
vbba
Bulk Bias
I/O TYPE ABBR.
- AI : Analog Input
- DI : Digital Input
- AO : Analog Output
- DO : Analog Output
- AP : Analog Power
- DP : Digital Power
- AG : Analog Ground
- DG : Digital Ground
- AB : Analog Bidirection
- DB : Digital Bidirection
CORE CONFIGURATION
bw1221l
IO2
IO1
CLK
VDDA
VDD
VSSA
VSS
VBB
PD
IREF
VREF
COMP
D2[9:0]
D1[9:0]
2 / 13
SEC ASIC
BW1221L
10BIT 80MSPS Dual DAC
ANALOG
CHARACTERISTICS
SYMBOL
VALUES
UNIT
Supply Voltage
VDDA
VDDD
5
V
Voltage on any Digital Voltage
Vin
VSSD-0.3 to VDDD+0.3
V
Storage Temperature Range
Tstg
-45 to 125
C
CHARACTERISTICS
SYMBOL
MIN
TYP
MAX
UNIT
Operating Supply Voltage
VDDA,VDDD
3.15
3.3
3.45
V
Digital input Voltage HIGH
LOW
V
IH
V
IL
0.7VDDD
-
3.3
0.0
-
0.3VDDD
V
Operating Temperature Range
T
opr
0
25
70
C
Output Load(effective)
R
L
-
37.5
-
Data Input Setup Time
T
S
-
2
-
ns
Data Input Hold Time
T
H
-
2
-
ns
Clock Cycle Time
t
CLK
12.6
20
-
ns
Clock Pulse Width High
t
PWH
6
10
-
ns
Clock Pulse Width Low
t
PWL
6
10
-
ns
IREF Current
I
REF
1.5
1.77
2.0
mA
Zero_level Voltage
V
OZ
-5.0
-1.2
5.0
mV
External Reference Voltage
V
REF
-
1.0
-
V
NOTE:
* It is strongly recommended that to avoid power latch-up all the supply
Pins(VDDA,VDDD) be driven from the same source, and all ground Pins(
VSSA,VSSD,VBB) be driven from the same source.
* Absolute Maximum Rating values should be applied individually while all other
parameters are within specified operating conditions. Function operation
under any of these conditions is not implied.
* Applied voltage must be limited to specified range.
* Absolute Maximum Ratings are values beyond which the device may be
damaged permanently. Normal operation is not guaranteed.
ABSOLUTE MAXIMUM RATINGS
RECOMMENDED OPERATING CONDITIONS
NOTE:
It is strongly recommended that all the supply pins(VDDA,VDDD) should be driven
from the same source to avoid power latch-up.
3 / 13
SEC ASIC
BW1221L
10BIT 80MSPS Dual DAC
ANALOG
CHARACTERISTICS
SYMBOL
MIN
TYP
MAX
UNIT
Resolution
-
-
10
-
Bits
Differential Linearity Error
DLE
-
0.4
1.0
LSB
Integral Linearity Error
ILE
-
1.5
2.0
LSB
Full Scale Current per Channel
I
fs
23
25
28
mA
Monotonicity
-
-
Guaranteed
-
-
LSB Size
-
23
25
28
uA
Maximum Output Compliance
V
oc
-0.5
0.0
0.2
V
Exteranl Refence Voltage
-
-
1.0
-
V
Power Supply Current
I
s
50
54
60
mA
CHARACTERISTICS
SYMBOL
MIN
TYP
MAX
UNIT
Conversion Speed
f
MAX
-
50
80
MHz
Analog Output Delay
T
d
-
11
20
ns
Analog Output Rising Time
T
r
-
15
25
ns
Analog Output Falling Time
T
f
-
19
30
ns
Analog Output Settling Time
T
set
-
100
150
ns
Glitch Impulse
GI
-
120
200
pVsec
Pipeline Delay
T
op
-
1
-
Clock
Power Supply Rejection Ratio
(f=1KHz, COMP=0.1uF)
PSS
-
0.0
0.5
%
Feedthrough
fdth
-
-33
-28
dB
Power_Down On Time
T
pn
-
4
6
ms
Power_Down Off Time
T
pf
-
0.1
0.3
ms
DC ELECTRICAL CHARACTERISTICS
NOTES
* Converter Specifications (unless otherwise specified)
VDDA=3.3V
VDDD=3.3V VSSA=VSSD=VBB=GND
Ta=25C R
L1
=R
L2
=37.5
, V
REF
=1.0V, R
set
= 564
* TBD : To Be Determined
AC ELECTRICAL CHARACTERISTICS
NOTE:
The above pararameters are not tested through the temperature range.
Clock and data feedthrough is a function of the amount of overshoot and undershoot on the
digital inputs. Settling time does not include clock and data feedthrough. Glitch impulse include
clock and data feedthrough.
4 / 13
SEC ASIC
BW1221L
10BIT 80MSPS Dual DAC
ANALOG
FUNCTIONAL DESCRIPTION
This is dual 10bit 80MSPS digital to analog data
converter and uses segment architecture for 5bits of
MSB sides and binerary-weighted architecture for 5bits
of LSB side. It contains of 1st latch block, decoder
block, 2nd latch block, OPA block, CM(current
mirror)block and analog switch block. This core uses
reference current to decide the 1LSB current size by
dividing the reference current by 68times. So the
reference current must be constant and the reference
curretn of CM can be constant by using OPA block
with high DC gain. The most significant block of this
core is analog switch block and it must maintain the
uniformity at each switch, so layout designer must
care of the matching characteristic on analog switch
and CM block. And more than 80%
of supply
current is dissipated at analog switch block and OPA
block. And it uses samsung(SEC) standard cell as all
digital cell of latch,decoder and buffer. And to adjust
full current output, you must decide the "Rset"
resistor value(connected to IREF pin) and "Vbias"
voltage value(connected to VREF pin). Its voltage
output can be obtained by connecting R
L1
(connected to
IO1 pin) and R
L2
(connected to IO2 pin). Its maximum
output voltage limit is 1.2V. So you must decide the
R
L1
, R
L2
, Vbias and Rset carefully not Vout(p-p) to
exceed 1.2V. It contains PD pin for power-save but
regretfuly
it isn't complete. If you want more
complete power-save mode, call back
us(SEC). We
can provide you more complete power-save mode
control scheme.
5 / 13
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