AN1500A
PDS038-SA2532K-001 Rev. C 21-03-00
This application note describes the use of the SA2532K Single Chip Telephone IC developed specifically to meet
with India's Department of Telecommunication (DOT) Specification for the Electronic Telephone Instruments. This
application note is based on the use of the multi-purpose demo board DB1500I with the SA2532K IC
High performance telephone with speech circuit, DTMF/Pulse dialer and tone ringer
Very few external low cost components
CMOS technology, far less sensitive to EMC
EMC proof single sided layout, provision for EMC blocking capacitors installed
Internally set real AC impedance to reduce external components
Sidetone programmable by two resistors and one capacitor
Ring frequency discrimination
Line loss compensation selectable by jumper
2 different flash timings selectable by 2 flash keys
31 digit last number redial
Sliding cursor protocol and pause key
One-touch repeat dialing
1 direct memory
Tone / Pulse switch
Modular connectors for handset and line cord, line connector a/b- terminals selectable by jumper
Layout prepared for 16kHz blocking filters
19-key SPST Keyboard on board
Tone LED output Indicator
Several hook transistor configurations
Over-voltage and over-current circuit options
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AN1500A
APPLICATION NOTE
SINGLE CHIP TELEPHONE DEMO BOARD
SA2532K
1 Scope
2 Key Features
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TABLE OF CONTENTS
1
SCOPE................................................................................................................................................................. 1
2
KEY FEATURES ................................................................................................................................................. 1
3
OTHER APPLICABLE DOCUMENTS AND PAPERS ........................................................................................ 4
4
REVISION STATUS............................................................................................................................................. 4
5
SA2532K PIN LAYOUT . ..................................................................................................................................... 4
6
GENERAL DESCRIPTION .................................................................................................................................. 5
7
DEMO BOARD CONFIGURATION..................................................................................................................... 5
7.1
S
ETTING A
/
B LINE CONNECTION
........................................................................................................................ 6
7.2
C
ONNECTING A HANDSET
................................................................................................................................ 6
7.3
S
ETTING DIALING MODE
................................................................................................................................... 6
7.4
S
ETTING LINE LOSS COMPENSATION
(AGC)...................................................................................................... 6
7.5
AC
IMPEDANCE
............................................................................................................................................... 6
8
DESCRIPTION OF KEYBOARD FUNCTIONS................................................................................................... 7
8.1
N
UMERIC KEYS
............................................................................................................................................... 7
8.2
F
LASH KEYS
(R,R2) ........................................................................................................................................ 7
8.3
L
AST NUMBER REDIAL KEY
(LNR) .................................................................................................................... 7
8.4
P
AUSE KEY
(PAUSE)...................................................................................................................................... 7
8.5
T
ONE
/ P
ULSE SWITCHING
............................................................................................................................... 7
8.6
E
NTER
/M5...................................................................................................................................................... 7
9
USING THE SA2532K ......................................................................................................................................... 8
10
SLIDING CURSOR PROTOCOL AND PAUSE INSERTION .......................................................................... 9
11
AC IMPEDANCE OF THE SA2532K ............................................................................................................... 9
11.1 D
EMO BOARD MEASUREMENTS
: ....................................................................................................................... 9
11.1.1
Definition:............................................................................................................................................... 9
11.1.2
Measurement:...................................................................................................................................... 10
12
SIDETONE CANCELLATION........................................................................................................................ 10
12.1 D
UAL
S
OFT CLIPPING
: ................................................................................................................................... 11
12.2 S
IDE TONE BALANCE NETWORK
:..................................................................................................................... 11
12.3 E
XAMPLE
:..................................................................................................................................................... 11
13
THE DOUBLE WHEATSTONE PRINCIPLE ................................................................................................. 11
13.1 S
IDETONE CANCELLATION
.............................................................................................................................. 12
13.2 AC
IMPEDANCE
............................................................................................................................................. 12
14
FURTHER ADJUSTMENTS .......................................................................................................................... 13
14.1 F
REQUENCY RESPONSE SHAPING
: T
RANSMIT
................................................................................................. 13
14.1.1
Microphone gain setting....................................................................................................................... 13
14.1.2
Tx frequency shaping: ......................................................................................................................... 13
14.2 F
REQUENCY RESPONSE SHAPING
: R
ECEIVE
................................................................................................... 14
14.2.1
Receive gain setting: ........................................................................................................................... 14
14.2.2
Rx frequency shaping.......................................................................................................................... 14
14.2.3
Metering pulses filtering....................................................................................................................... 14
15
OFF-HOOK CONDITIONS & DC MASK ...................................................................................................... 15
15.1 L
INE CURRENT PATH
...................................................................................................................................... 15
15.2 DC
MASK PATH
............................................................................................................................................. 15
15.2.1
Setting for low DC mask: ..................................................................................................................... 15
15.3 S
PEECH MODE
.............................................................................................................................................. 16
15.4 DTMF
DIALING
............................................................................................................................................. 16
15.5 P
ULSE DIALING
.............................................................................................................................................. 16
15.6 P
RE
-
DIGIT
, I
NTER
-
DIGIT
,
INTER
-
TONE AND ACCESS PAUSES
............................................................................ 17
16
HOOK TRANSISTOR OPTIONS ................................................................................................................... 17
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16.1
ELECTRICAL REQUIREMENTS
.......................................................................................................................... 17
16.2 S
INGLE BIPOLAR TRANSISTOR
........................................................................................................................ 17
16.3 B
IPOLAR DARLINGTON TRANSISTOR
............................................................................................................... 18
16.4 VMOS-FET
WITH SURGE PROTECTION
.......................................................................................................... 18
16.5 VMOS-FET
WITH OVERCURRENT PROTECTION
.............................................................................................. 18
16.6 C
URRENT
L
IMITING
........................................................................................................................................ 19
16.7 O
VERVOLTAGE PROTECTION OF THE
PCB:..................................................................................................... 19
16.8 DC-
MASK FOR VARIOUS HOOK TRANSISTOR ARRANGEMENTS
.......................................................................... 20
17
SHUNT- AND RINGER TRANSISTORS ..................................................................................................... 20
18
ON-HOOK CONDITIONS .............................................................................................................................. 20
18.1 Q
UIESCENT CURRENT PATH
........................................................................................................................... 21
19
RINGING MODE ............................................................................................................................................ 21
19.1 R
INGING FREQUENCY COMPARATOR
.............................................................................................................. 21
20
OSCILLATOR INPUT .................................................................................................................................... 21
21
EMC & RFI ISSUES ....................................................................................................................................... 21
21.1 T
ECHNOLOGY
: .............................................................................................................................................. 21
21.2 L
AYOUT HINTS
: ............................................................................................................................................. 21
21.3 EMC
BLOCKING PARTS
: ................................................................................................................................ 22
21.4 B
LOCKING OF
AGND: ................................................................................................................................... 22
22
BOARD SCHEMATIC .................................................................................................................................... 23
23
BOARD LAYOUT........................................................................................................................................... 24
24
PART LIST ..................................................................................................................................................... 25
25
APPLICATIONS ............................................................................................................................................. 26
26
LIABILITY AND COPYRIGHT STATEMENT ................................................................................................ 27
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1. Data Sheet SA2532KA/B
2. Pin-out Comparison SA2531 - SA2532
3. Application Note for Speaker Phone: Application Note SAN2202
4. Application Note for uC interface : Application Note SAN3010
5. Application Note for the Extraction of Power : Application Note SAN3020
6. Application note for using Dynamic Mic : Application Note SAN3021
AN1500 Application Note (this document):
AN1500 Demo Board Schematic
Rev.: B
DB1500I Demo Board Layout
Rev.: 1.0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
LS
RO1
RO2
VDD
AGND
STB
CI
MO
LLC
HS/DPN
OSC
MODE OUT
C4
C3
RI
LI
VSS
CS
M2
M1
MODE
FCI
R1
R2
R3
R4
C1
C2
SA2532K
3 Other applicable documents and papers
4 Revision status
5 SA2532K Pin Layout .
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The SA2532K device was developed to provide "plug & play" solution for the Indian DOT, emphasizing high
performance voice transmission and reception. In spite of the fact that voice transmission and reception are the
most vital features in telephony, they are very often ignored or given lower priority compared with some more or
less useless non-voice features. No compromises were accepted during the design phase of the SA2532K, which
is based on the SA2531/2 speech circuit and which supersedes even the hardest PTT requirements worldwide.
The dialler part is based on a long history of producing a wide range of dialer circuits with user-friendly features in
compliance with various national PTT regulations. This knowledge enabled us to develop a specific product to meet
with DOT type approval.
The last piece in the puzzle to complete the full picture of the first CMOS single chip POT was the tone ringer. A
ring frequency discrimination circuit was implemented to avoid false "bell-tinkle" during pulse dialing from a parallel
telephone. The 3-tone melody generator provides the ringing signal.
Note: all the subsequent component numbering is referenced to the AN1500 schematic, shown in pt.22
The SA2532K is the rare combination of advanced technology and down-to-earth simplicity providing easy and
uncomplicated design effort for the telephone manufacturer. No fussing around: Simply go by the straight forward
guidelines supplied by a highly experienced application group. No technology stress but appealing functionality.
See Fig. 1 for configuration locations:
Fig. 1: Demo board configuration
6 General Description
7 Demo board configuration
J2: Dial Mode
Selection
Line connector
Handset Connector
J3: line loss compensation
selector
Sidetone Network
Ringer Capsule
Connector
J1 :Line terminal selection
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7.1 Setting a/b line connection
J1 allows selection of a/b line terminals to
easily adapt the demo board to various
PTT line connections:
7.2 Connecting a handset
A handset connected at Z2 should have the following
connections:
remark: observe polarity of the electret microphone
7.3 Setting dialing mode
By J2, a selection of 3 different dialing modes can be
made, 2 pulse (=LD) dialing modes and a DTMF
dialing mode.
If LD Mode is selected then it is possible to switch
into MF mode by pressing the
!
key but the mode
will return to LD after a hookswitch operation or after
a Recall (flash). In LD mode pulsing is at 10 pulses
per second.
7.4 Setting line loss compensation (AGC)
Line loss compensation = line current dependent
gain setting of Tx and Rx amplifiers can be set by
jumper setting to 3 different modes : high, low and
no LLC (=default).
7.5 AC impedance
The Characteristic or output impedance of the SA2532K is set internally to 600
. No further components are
required. For a complex impedance refer to pt 11.
inner two pins (default)
outer two pins (optional)
LD Mode
make/break
ratio 1:2
LD Mode
make/break
ratio 2:3
MF Mode
LLC 45 to 75mA
LLC 20 to 50mA
no LLC
Handset
J2
J2
J2
J3
J3
J3
J1
J1
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The user-friendly operating procedures comply with different PSTN and PABX systems worldwide. By choosing
between the total of 19 keys it is possible to fit the SA2532K into most telephone designs.
The keyboard is connected to 8 pins of the SA2532K (C1...C4, R1...R4) by a n*m SPST keyboard matrix. To
extend two of the rows, a diode (D9 and D10) are added. This arrangement allows detection of 19 keys on a 4*4
matrix.
8.1 Numeric keys
The numeric keys (1..0,
!
,#) are standard number dial keys for both DTMF and pulse dialing (
!
and # only DTMF).
Additionally the
!
key can be used for temporary MF switching.
8.2 Flash keys (R,R2)
Selection of flash timing can be made by selecting one of the 2 flash keys :R1= 100ms and R2= 270ms.
8.3 Last number redial key (LNR)
The last number redial facility allows redialing of the last manually entered number by one keystroke. LNR is
repeatable after each off-hook. The LNR key also supports the sliding cursor protocol (see pt. 10) to allow
convenient redialing with PABX systems.
8.4 Pause key (PAUSE)
This key is to insert a pause in a digit string. Each pause is 2 seconds if inserted within the first 5 digits otherwise a
wait function will halt dialling until a PS or LNR key is depressed.
8.5 Tone / Pulse switching
When any of the LD dialing modes is selected (see pt. 7.3), a switch to temporary MF can be performed by
pressing the
!
key to get into DTMF mode and one of the flash (R)-keys to get back to pulse dialing. Once in MF
mode the mode output LED is active.
Remark: temporary MF can only be activated, when the initial dialing mode selected by J2 (see pt. 7.3) is in one of
the pulse dialing modes.
8.6 Enter/M5
The ENTER key is used to program the memory (M5). Pressing ENTER followed by the key M5 opens the memory
location for storing the number.
8 Description of keyboard functions
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The DB1500I demo board is delivered with an SA2532K installed and the key functions are according to the chip
are illustrated below.
Fig. 2: SA2532K keyboard labels
9 Using the SA2532K
MUTE
1
2
M5
8
7
6
5
4
3
0
R2
R
#
*
9
PAUSE
LNR
ENTER
C1
C2
C3
C4
R1
R2
R3
R4
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To accommodate easy and uncomplicated redialing behind a PABX, a sliding cursor protocol is implemented:
if a manually entered digit string matches the contents of the LNR memory, pressing LNR will only dial out the
remaining digits :
example: desired number 0123456 (where 01 is the access code)
off-hook, manual entry = 01
-wait for dial tone
-23456
- line is busy
-on-hook
(LNR contents is 0123456)
off-hook, manual entry = 01
-wait for dial tone
- press LNR key:
LNR dials out the remaining digits: 23456
The SA2532K is designed for applications requiring a characteristic impedance of 600 Ohms, no connection should
be made to CI (pin 7) if a real impedance is required. Should a complex impedance be required a capacitor of
approximately 1/10 of the complex part of the impedance should be connected to CI. Every complex impedance
consists of a real and complex part. The ac impedance of the SA2532K is calculated by
Z
AC
= Z
SYN
+ Z1
Where :
Z1 = the external resistor connected between pin 1(LS) and pin 27 (LI) . This resistor is also used by the device for
current monitoring and sets the DC resistance. To maintain correct operation the value of this resistor should be
set to 30 Ohm.
Z
SYN
= the internally synthezised impedance.
For real impedances
Z
SYN
= 19 * Z1
Z
AC
= (19*Z
SYN
) + Z1
Z
AC
= 20 * Z1 = 600 Ohm
If a impedance lower than Z
AC
is required, then a external parallel impedance should be added between LS and
V
SS
. To calculate the resulting AC impedance, any parallel impedance path between LS and V
SS
should be
considered. For example, if a bipolar line transistor is used, the resistance from the transistors base to VSS (Z
P
) is
in the order of 10K (R10). If a MOSFET is used then Z
P
is in the order of 100K which is negligible.
Z
AC
= 600//Z
P
Care must be taken when selecting the value of ZP since the value chosen should be such that the line transistor is
driven into full saturation.
11.1 Demo board measurements:
11.1.1 Definition:
return loss is defined as:
returnloss
Zref
Zx
Zref
Zx
=
+
-
20*log
where:
Zref = the reference AC impedance (= the line termination)
Zx = the AC impedance of the telephone under test
10 Sliding cursor protocol and pause insertion
11 AC impedance of the SA2532K
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11.1.2 Measurement:
Echo return loss (according to BAPT223
ZV5) is measured by bridge balance
measurement as shown in Fig.3:
R1 and R2 must be matched to 0.1%,
the measuring equipment must be
isolated from earth and should have an
input resistance of >25k
.
Capacitors C1 and C2 must be >10F.
The Telephone under test is supplied by
a (high ohmic) current source and
measurements are taken in speech
mode with a connected handset.
Fig. 3: Return loss measurement setup
Calculation of results:
The sending level, measured in "cal"-position of switch SW is tuned to ps=-10dB
950mV
= 300mV
rms
,thus the sinewave
generator's level is -4dB
950mV
= 600mV
rms
.The receive level (=pe) is measured in "meas"-position of switch SW.
The echo return loss is then calculated by:
ar
dB
= ps - pe
(ps, pe levels in dB
950mV
)
or
ar
dB
= 20* log (ps / pe)
(ps, pe levels in mV
rms
)
Fig.4 shows some typical
results, measured with the
DB1500I demo board with
Z
ref
= 600
, Z
ref
= 220
+
820
//115nF and Z
ref
=
270
+ 750
//150nF.
The board was configured
as shown in the schematic,
using a single bipolar
(2SA1210) line transistor.
Fig. 4: typ. return loss measurement results with the DB1500I demo board
12
14
16
18
20
22
24
26
28
30
0
300
600
900
1200
1500
1800
2100
2400
2700
3000
3300
3600
3900
f [Hz]
Ec
h
o
re
tu
rn
l
o
s
s
[d
B
]
600 Ohms
220+820//115nF
270+750//150nF
12 Sidetone cancellation
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The side tone is probably one of the most important parameters, if not the most important parameter. It determines
very much the overall instinctive performance of a telephone since it has direct influence on other parameters. In a
subjective test the two most inherent parameters are distortion and side tone, or other parameters directly
influenced by those two, e.g. echo, acoustic stability, clearness, etc.
During the design of the SA2532K family considerable effort was put into the system definition of the side tone
cancellation. It was clear that even the highest side tone cancellation could give an unpleasant harsh distortion at
very large signal levels if no efficient limiter was provided. This led to the designing of what turned out to be the
best "soft clipping" circuit yet developed, surpassing any solution used in a telephone so far.
The encounter is a side tone which is easy to calculate and which gives a well defined cancellation virtually
independent of other parameters like return loss (ac impedance) and dynamic range (absolute input signal levels).
12.1 Dual Soft clipping:
The dual soft clipping circuit prevents harsh distortion and acoustic shock in both directions by limiting the
maximum output of the Tx/Rx amplifiers at a level which still maintains a non-distorted signal (see V
AGC
levels in
data sheet).
If the output of the amplifier is already at the soft clip level and the input level is further increased, then the
amplifier's gain is reduced, so that the output level remains non-distorted at the soft clip level. Even fast input signal
peaks are detected because of the fast attack time (see t
ATTACK
) of the soft clip circuit. Instabilities are prevented by
using a long decay time (see t
DECAY
in data sheet).
12.2 Side tone balance network:
The side tone balance network is simply calculated as:
Z
BAL
= Z
LINE
x 10
12.3 Example:
For a line termination of
270
+750
//150nF
the resulting sidetone balance network would be:
2k7 + 7k5//15nF
Within the AN2201 application, this would apply to R13= 2k7
R14= 7k5
C4 = 15nF
The family of SA2532K single chip telephones are using a double Wheatstone bridge for return loss and side tone
cancellation. This unique configuration makes it very easy and uncomplicated to set the side tone network.
Fig. 5 explains the principle of the Double Wheatstone bridge: For easier understanding the block diagram is split
into two separate diagrams, which only show the relevant components.
The components shown in the block diagram represent the following components in the DB1500I schematic:
Z
Line
:
the PTTs AC impedance (external)
Z
1
:
R11 = 30
Z
2
:
R12 = 300
Z
syn
:
Q3
Z
bal
:
the sidetone network
R
ref
,Z
ref
:
internal resistors
13 The Double Wheatstone principle
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13.1 Sidetone cancellation
Perfect sidetone cancellation is achieved, when the sidetone balance network is matched to the line impedance by
a factor of 10, which is equal to the matching of the resistors Z2 and Z1.
With ideal matching, no differential potential of the transmitted signal occurs at nodes RI and STB and the output of
the RX amplifier is 0.
13.2 AC impedance
An internal amplifier controls the impedance of Zsyn by matching LI to an internal reference. Part of this internal
reference is accessible by pin CI. When no external component is connected at that pin, the AC impedance of the
circuit is synthesized to 600
.
When a capacitor is connected at CI, the AC impedance of the chip becomes complex. For correct adaption, the
capacitance of CCI should be 1/10 of the line's complex part.
Fig. 5: Double Wheatstone bridge principle
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14.1 Frequency response shaping: Transmit
Fig. 6: Tx signal path
Transmit frequency response shaping is performed by 3 resistors for gain setting and 3..4 capacitors for frequency
shaping:
14.1.1 Microphone gain setting
The electret handset microphone is supplied from the constant voltage at LI (#27), filtered by R20 and
C14 (see fig 6). R21 and R23 are the bias resistors of the electret microphone. Transmit gain is set by both
selecting the proper microphone type (sensitivity) and by varying R21 & R23. Reasonable values for these resistors
are in the range of 1...2.5k
(each), which results in a gain adjustment range in the order of 6..8dB.
14.1.2 Tx frequency shaping:
Transmit frequency shaping can be done by C11,C13 (high pass) and C12( low pass). R22 can be installed to
attenuate the microphone signal without affecting the frequeny response curve,
M1(#23) and M2 (#24)are differential inputs of the microphone amplifier. Please note the proper connection of the
M1 and M2 inputs in respect to the positive and negative side of the microphone.
To find the correct values, a SLR (sending loudness ratings) measurement with the specific handset used in the
customer's application must be made.
14 Further Adjustments
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14.2 Frequency response shaping: Receive
Fig. 7: Rx signal path
The receive signal is applied at the Rx amplifier input, RI (#28) and STB (#6) and is available at the differential
outputs RO1 and RO2.
14.2.1 Receive gain setting:
Rx gain can be set by both the sensitivity of the earpiece and the value of R25.
14.2.2 Rx frequency shaping
Receive frequency shaping is done by C15 (low pass) at the Rx amplifier output. C17 impedes the DC path through
RO1, RO2.
To find the correct values, a RLR (receive loudness ratings) measurement with the specific handset used in the
customer's application must be made.
14.2.3 Metering pulses filtering
If filtering of metering pulses (typ. 12 or 16kHz ) is required (for example in Germany) two blocking filters can be
installed:
LBF1 , CBF1 as notch filter at the line input and
LBF2 ,CBF2 as notch filter at the Rx amplifier input
Note:
since CBF1 is connected at the line side, it must be a .../250V capacitor and LBF1 must be able to drive the
maximum line current (
100mA) without saturation.
LBF2 and CBF2 however, can be low voltage, low current components .
The application AN1500, shown with two resonators, gives adequate attenuation of the metering pulses signal. The
benefit of this application is, that only one filter (LBF1,CBF1) is used on the high voltage/high current side, while the
second notch filter (LBF2,CBF2) is connected at a low voltage/low current node, enabling use of low cost
components.
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15.1 Line current path
When going off-hook, SW1/1 short
circuits the leakage supply resistor
R1 and enables a low-ohmic path
from line into the telephone. At the
same time SW1/2 supplies the base
of Q2 via R7 and R8 and signals a
"off-hook" state to the ICs
HS/DP-pin (#10). The base/gate of
Q1 is pulled down by Q2 and the
SA2532K is started up. V
LI
(pin #27)
is regulated to the specified voltage
by shunt regulation from Q3.
Line current flows through the
following path:
La -- RB1 -- Q1 -- R11 -- Q3 -- V
SS
--
RB1 -- Lb
Fig. 8: DC mask & line current path
15.2 DC mask path
The DC characteristics (DC loop resistance) of the application is determined by the following conditions:
Va,b = V
LI
+ V
R11
+ V
CE,Q1
+ 2x(V
f,RB1
)
V
LI
:
The voltage at LI (#27) is shunt-regulated to 4.5V by Q3.
V
R11
:
V
R11
= I
line
* R11,
where: R11=30
changing the value of R11 is not recommended, since it affects the following parameters:
AC impedance
Tx and Rx gains
DTMF level
AGC switching positions
V
CE,Q1
:
This parameter is mostly affected by the type of hook transistor configuration used, see pt.16
for details
2x(V
f,RB1
):
Generally, the rectifier bridge must be installed to meet the specification for independence of
polarity. V
f
is typ. 0,7....0,8V (20...100mA). If lower forward voltages are required, an active
(MOSFET) bridge must be used.
15.2.1 Setting for low DC mask:
The standard application regulates the voltage at LI to
4.5V
DC
for line currents >10mA, determining the absolute
level of the DC mask. Lower line currents cause a slope-down of V
LI
, enabling operation down to 5mA . The
resulting DC mask fits into most countries DC mask specs. Some countries however, like Denmark or Norway
require a very low DC mask at line currents below
20mA line current. The constant voltage level at LI can be
lowered to about 4.3V by connecting a 16k
-resistor from CI (#7) to Vss (#26). With this adaption, the DC mask is
15 Off-Hook conditions & DC mask
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lowered by only
0.2V for line currents >17mA. At lower line currents however, as required for these countries, the
DC mask is lowered significantly, since slope-down of LI occurs already at line currents <17mA..
Fig. 9 : Example for low DC mask: Denmark
Fig.10 shows a typical example for a low DC mask setting compared with the DC-mask specs for Denmark (ETS
300 001: March 1996) : the solid line indicates the DC mask with a 16k
resistor connected at CI, while the dotted
line shows the DC mask of the original AN1500 A0 version with a single PNP hook transistor (ref. pt.16).
Note: When connecting a resistor at CI, AC impedance, DTMF level, Tx/Rx gains and LLC gain curves are slightly
changed. Therefore, after installing a resistor at CI, the above parameters must be readjusted.
15.3 Speech mode
In speech mode, shunt regulation (by Q3) is active and line current flows as described in pt 15.1. At the same time,
both Tx and Rx amplifiers and 2 wire-4 wire conversion circuits are active.
15.4 DTMF dialing
During DTMF dialing the same line conditions as in Speech mode apply, except that speech is muted in both
directions and a confidence tone is sent to the Rx amplifier.
The DTMF signal is modulated to the line by controlling the shunt transistor, Q3. During inter-digit pauses speech is
also muted.
15.5 Pulse dialing
With pulse dialing, the line has to be interrupted during "break" periods and short circuited during "make" periods.
For example, "LD 60/40 10pps" means: break/make ratio is 60:40 with 10 pulses per second =
The dialing pulse is a 60ms break (line interrupt) followed by a 40ms make (line short circuit).
Dialing number "1" will result in one dialing pulse, total time = 100ms.
Dialing number "0" will result in 10 dialing pulses, total time = 10*100ms = 1sec.
Line break pulses are performed by Q1 being switched off. The on-off control signal is output from the HS/DP pin
(#10) switching Q2 (and in turn Q1) on and off.
DC mask: Denmark
-1
1
3
5
7
9
11
13
15
0
5
10
15
20
25
30
35
40
I line [mA]
Ua,b [V]
CI = 16k
CI = n.c.
DC mask UL
DC mask LL
AN1500A
sames
sames
sames
sames
17/27
Make pulses are performed by Q3 with Q1 being switched on. The base of Q3 (=pin CS, #25) is pulled to V
SS
,
resulting in V
LI
= V
BE
0.7V.
CS is pulled low during the complete dialing period of one digit, which means in worst case (dialing number "0") the
circuit cannot be supplied from line and must be buffered by the V
DD
-cap, C9. Therefore C9 must be big enough to
supply the active circuit for 1 second.
15.6 Pre-digit, Inter-digit ,inter-tone and access pauses
During pulse and DTMF dialing, several pauses must be added (see also: data sheet):
pre-digit pause (PDP):
Pause between CS=low and first break (pulse dialing only)
inter-digit pause (IDP):
Pause between pulse dialed out numbers, from last "make" to next PDP
inter-tone pause (ITP):
Pause between DTMF dialed out numbers
access pause (AP):
manually inserted pause in a digit string (see pt. 7.8)
The following tables give an overview of the advantages and disadvantages of 3 different types of hook transistor
arrangements: single bipolar PNP, PNP darlington and MOSFET. Any of these configurations can be installed on
the demo board. Just check for corresponding part name on the PCB layout.
16.1 electrical requirements
Both hook transistor (Q1) and driver transistor (Q2) must be >=200V types, Q1 must have an IC >100mA. If single
PNP configuration is used, the transistor must have a gain
IC
IB
100
at I
C
=100mA. The driver transistor (Q2) must
have enough gain to be in full saturation at high line currents ( if driving a bipolar hook transistor ).
recommended types:
Q1
Q2
2SA1210, MPSA92,BSS92 (depending on configuration)
BSP92 (SMD)
KSA1156Y
2N5551
MPSA43
BF820 (SMD)
16.2 Single bipolar transistor
Schematic
+
-
lowest DC mask at low currents
just one transistor
Transistor type must have a gain
IC
IB
100
at I
C
=100mA
high on-resistance at high
currents slightly affects gains and
DTMF level
10k
base resistor (R4) affects
AC impedance
16 Hook Transistor options
AN1500A
sames
sames
sames
sames
18/27
16.3 Bipolar darlington transistor
Schematic
+
-
low
cost
high DC mask at low currents
may be tight to spec limits for
some PTTs
2
transistors
10k
base resistor (R4) affects
AC impedance
16.4 VMOS-FET with surge protection
(surge protection = R3 =20
may also be used with bipolar hook transistor options)
Schematic
+
-
powerless
switching
low
on-resistance
low
DC-mask
excellent surge protection
gate resistor (R5) does not affect
AC impedance
MOS handling required
higher cost than bipolars
few
vendors
Principle: the source voltage is limited to
10V (D6; see schematic) in off-hook state . High voltage peaks induced
at line will generate a high positive voltage drop across R3, lifting the gate voltage over the source voltage and thus
cause the (P-channel) Transistor to shut off.
16.5 VMOS-FET with overcurrent protection
(overcurrent protection =R3,Q5 may also be used with bipolar hook transistor options)
Schematic
+
-
powerless
switching
low
on-resistance
lowest
DC-mask
adjustable overcurrent protection
gate resistor (R5) does not affect
AC impedance
MOS handling required
higher cost than bipolars
few
vendors
extra (low cost) transistor
required
Principle: the line current generates a voltage drop across R3. If this voltage drop is >0.7V, C-E of Q5 is on and
shuts Q1 off by short circuiting its Gate/Source voltage.
The shutoff current is calculated by
I
shutoff
= 0.7V / R3 ;
installed = 0.7V/3.9
= 180mA
AN1500A
sames
sames
sames
sames
19/27
16.6 Current Limiting
Fig. 9 : Example of current limiting circuit
Principle: the line current generates a voltage drop across R6. If this voltage drop is >0.7V the Q6 switches on
effectively shutting off Q9. The 2W resistor R4 is used to dissipate the power generated as a result of the current
through and voltage across C-E of Q9.
I
shutoff
= 0.7V / R6
16.7 Overvoltage protection of the PCB:
Additionally to the protection measures described in pt. 16.4 and 16.5 it is highly advised to install an additional
surge protection device directly at the a- and b- terminals.
The maximum C-E breakdown voltages of the line and driver transistors are:
transistor type (line)
V
CEO
,V
(BR)DSS
transistor type (driver)
V
CEO
BSS 92,BSP92
200V
MPS-A42, KSP42
300V
MPS-A 92
300V
MPS-A43,KSP43
200V
2 SA 1209
160V
2N5551
160V
2 SA 1210
200V
The clamping voltage of a 150V-varistor can be up to 400V at 5 Amp. clamping current. In other words, it may not
be able to protect the line transistor at very high surge spikes.
10V
C2
10u
Q9
M
PSA92
Q7
Q
M
PSA9
2
Q8
Q
M
PSA9
2
Q6
BC
327
Q5
M
PSA43
Q3
QMPSA43
R6 10
R4 820 2W
R7
100
R5
22k
R3
15k
R10
1000k
R2
150k
R1
220k
R8 30
TP
1
0
TP2
TP
7
AN1500A
sames
sames
sames
sames
20/27
16.8 DC-mask for various hook transistor arrangements
Fig. 9 shows a typical DC
mask graph for the optional
hook transistor
arrangements: MOSFET with
overcurrent pro-tection,
MOSFET with surge
protection, single PNP and
PNP darlington .
The X-scale shows line
current in mA and the Y-
scale shows the voltage
across the a- and b-
terminals.
Check with your application's
PTT require- ments to find
the arrangement that fits best
into the specification.
(see also: pt 15.2.1: setting
for low DC mask)
Fig. 11: DC mask for various
hook transistor options
Q3 is used to shunt excess line current to V
SS
to maintain a constant voltage on LI (#27). It is also used for DTMF
line modulation and short circuits the speech part during pulse dialing (ref. Fig.8).
The transistor must be capable of driving >100mA and have a typ. gain B >=100.
Q4 is used to switch the piezo ringer on and off, it can be any NPN single or darlington transistor capable of driving
100mA at 25V U
CE
.
recommended types:
Q3
Q4
BC327-16
BCX 51-16 (SMD)
BC547
BC517 (Darlington)
BCV27 (SMD- Darlington)
In on-hook state the circuit is supplied by a very small current to maintain retention of stored numbers and ringing
melody. The hook transistor is off and the HS pin (#10) is forced to zero by R8 and R9//Q2
B,E
. The IC is powered
down, only a very small current flows from line to maintain V
DD
and thus retention of stored memories and ringing
melody. The DC resistance of the application in this state is >5M
(= the value of R1).
2
3
4
5
6
7
8
9
0
5
10
15
20
25
30
35
40
45
50
I Line [mA]
Ua
,
b
[V
]
MOSFET with surge protection
single PNP (2SA1210)
bipolar darlington
MOSFET with current protection
17 Shunt- and Ringer Transistors
18 On-hook conditions
AN1500A
sames
sames
sames
sames
21/27
18.1 Quiescent current path
La -- R1 (determines on hook DC resistance) -- RB1 -- R15 -- V
DD
(C9 // D1)
V
SS
-- RB1 -- Lb
If the telephone is disconnected from line memories are not lost since C9 keeps charging V
DD
for a limited period of
time. The absolute time span depends on the quality (internal discharge) of C9 and the leakage resistance of D1.
In on-hook state the circuit is supplied by a very small current to maintain the retention of stored numbers and the
ringing melody
Frequency discrimination assures that the tone ringer is activated only when a valid ring signal is applied and not
when pulse dialing from a parallel telephone (false "bell-tinkle").
19.1 Ringing frequency comparator
The ring signal is checked at pin FCI (#21) for a valid ringing frequency. As soon as a signal is applied to the line
the internal "ring frequency detector" will start, provided that the signal level at FCI is above the trigger threshold (
2/3 V
DD
) . If the frequency is within the specified range the melody generator will send a bitstream out of MO (#8),
charging the piezo ringer via Q4 and discharging it via D5 and an internal high voltage transistor. As soon as a non-
valid or missing ring signal is detected, the bitstream is stopped and the circuit returns to standby.
Ringing signal path
La -- C1 -- R2 -- RB1 -- C8//D4 (charges piezo ringer supply) -- C8//D4 (charges V
DD
)
V
SS
-- RB1 -- Lb
another path exists from C1 -- D2 -- R3 to FCI // C2 // R4 for the ringing frequency detector input.
20 Oscillator input
A 3.58MHz ceramic resonator (recommended type MuRata CSA 3.58MHz ) must be connected at OSC (#11). The
parallel capacitor C10 is to trim the oscillation frequency (not required with the recommended resonator type).
The exact resonant frequency should not be measured at the OSC input directly, because the capacitive load of the
Oscilloscope probe will shift the oscillation frequency.
DTMF frequencies are derived from the resonant frequency, if these frequencies (see DTMF frequency standards
or data sheet) are not centered, the oscillator must be trimmed.
EMC (electromagnetic compatibility) and RFI (radio frequency interference) is a major concern in most PTT
approvals. And due to the upcoming digital networks (GSM, CDMA, DECT) also a feature which can be "heard" by
the user. Therefore it is a major headache for telephone designers, since EMC testing is generally done with
finished designs and failing EMC tests may result in adding expensive components, like coils, chokes etc.
Much can be done by considering EMC from the very beginning ! The most important factors are IC technology,
layout and placement of EMC blocking components:
21.1 Technology:
Due to SAMES unique CMOS technology the circuits show far less sensitivity to RFI than bipolar circuits which
makes EMC a much easier task.
21.2 Layout hints:
19 Ringing mode
21 EMC & RFI issues
AN1500A
sames
sames
sames
sames
22/27
As a common rule, V
SS
ground planes should be as large as possible. "Bottlenecks" and long distances in the
ground path should be avoided.
Additionally, long distances between LI (#27) and the Emitter of the shunt transistor (Q3) should be avoided.
Therefore, Q3 should be placed near the IC pins :
collector = pin #26 =Vss,
base
= pin #25 = CS,
emitter
= pin #27 = LI.
21.3 EMC blocking parts:
Connections for blocking components, preferably ceramic capacitors (far less cost than coils) should be already
considered in the layout design. These capacitors should be connected as close to the IC (or line/handset
connector) pins as possible with a low-ohmic connection to V
SS
. SMD caps have best performance for EMC
blocking because of short leads and they can be placed directly underneath the IC at the solder junction.
If the use of SMD components is not possible, leaded ceramic capacitors can be connected at top PCB side as
shown in the demo board's layout. Refer to EC1..EC7 on both schematic and layout.
The actual number of required EMC blocking components in the customer's design cannot be predicted, since
EMC performance is influenced by many other factors, like telephone assembly, wire lengths etc.
21.4 Blocking of AGND:
For SA2532K EMC designs, it is very effective to block the AGND-pin (#5) with an inductor of
150nH or
higher. This small inductance can be installed without extra cost by a printed coil with
8..10mm diameter and
5 turns (see PCB layout).
How to calculate the inductance of a printed spiral coil:
where:
n = number of turns
d
o
= outer diameter in cm
d
i
= inner diameter in cm
Example:
The printed coil used in the DB1500I layout has the following dimensions
(see Fig.12):
d
o
= 8.2 mm
d
i
= 2.6 mm
Fig. 10:printed coil on DB1500I
n = 5.5
PCB for EMC protection
Note: Instead of a printed coil, a helical air-coil (7mm diameter, 7..9mm length, 5..7 turns) made by a piece of
copper wire may also be used.
[ ]
(
)
L
n d
d
d
d
d
d
nH
o
i
o
i
o
i
+
+
-
+
10 75
1 2 72
2
.
.
[ ]
(
)
L
nH
nH
+
+
-
+
=
10 75 55 0 82 0 26
1 2 72
0 82 0 26
0 82 0 26
146
2
.
.
.
.
.
.
.
.
.
AN1500A
23/26
sa m e s
sa m e s
sa m e s
sa m e s
22 Board Schematic
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
A
B
C
D
A
B
C
D
Q_
b
BSS 9
2
Q
2_a
BSS 9
2
VR 1
VD R
W
LC
C
LA
Z1
LIN E
JMP
8
6
4
2
7
5
3
1
H
G
F
E
D
C
B
A
J1
3
1
2
4
O N
O FF
SW 1_a
1
3
4
2
IC 2
BR IDG E
2
1
Z3
R inger
7
O N
5
O FF
6
8
SW 1_b
Q 4
BC 547B
Q 2
M PSA 45
JU MPER
4
3
2
1
D
C
B
A
J3
JU MPER
4
3
2
1
D
C
B
A
J2
Q1
B
MP
S
A
9
2
Q1
A
MP
S
A
9
2
Q 3
BC 327
Q_
c
2S
A
1210
Q
1_a
B
C
557
D 4
24V
D 6
10V
D2
12V
D 11
5V6
D_
a
12V
D_
b
12V
LED 2
TO NE
X1
3.58 M Hz
S17
LN R
S16
R 2
S15
R 1
S14
PAU SE
S13
#
S12
*
S11
0
S10
9
S9
8
S8
7
S7
6
S6
5
S5
4
S4
3
S3
2
S2
1
S1
M UTE
+ C 8
10u/25V
+
C5
1U
/
10V
+
C 9
470u/16V
+ C 6
10u/36V
+ C 14
100u/25V
+ C 16
100U /6V
D 10
D5
1N
4148
LE
1
F2
F1
M 2
M 1
Z2
H AND SET
C 2
10N
C 12
X
C 10
22p
C 15
X
C1
1
10n
C1
680n/
250V
C1
3
10n
R 22
X
R 10
10K
R 4
220K
R1
1
30
R 14
7K5
R 12
300
R 17
100K
R 15
330K
R1
3
100K
R2
2K
2
R1
5M
1
R3
330K
R1
8
510
R7
220K
R8
150K
R 9
1M
R2
0
2K
2
R 21
1K1
R2
6
1K
R2
5
X
C1
7
10u
R 23
1K1
R_
c
100K
R 10C
10K
R 10B
100K
R 10A
10K
R
1_a
100K
R
1_b
100K
R
2_b
20
R
2_a
3.
9
S
A
25
32
K
M OD E_O UT
LS
LLC
M OD E
M O
H S/DP
C S
C I
STB
R I
FCI
LI
D
V
D
S
S
V
O SC
R 4
R 3
R 2
R 1
C 4
C 3
C 2
C 1
R O 2
AG ND
R O 1
M 2
M 1
IC1
a
b
a
b
a
b
c
c
c
c
b
a
23
24
3
2
5
12
16
15
14
13
20
19
18
17
11
26
4
9
22
8
10
7
25
6
28
27
1
21
3
5
4
2
4
3
2
1
*
0
#
R2
R1
9
8
7
PAUSE
6
5
4
LNR
MUTE
3
2
1
Keypad Layout
2. MO SFET
3. Single PNP
1. MO SFET with current lim it
Line Transistor Options
R 13
1K8
C 4
C 7
15nF
10nF
SAMES Telecom
3rd March 1997
Date :
of
Single Chip Telephone Application Circuit
Rev : B
Sch.
Sh
Pn#
SA2532KA/B
01
01
AN1500A
24/27
sames
sames
sames
sames
23 Board Layout
AN1500A
25/27
sames
sames
sames
sames
24 Part list
Designator
Part Type
Description
C1
680n/250v
Ringer Capacitor
C2
10n
Anti aliasing filter, ring frequency detector
C3
not fitted (hookswitch filter)
C4
not fitted (sidetone network)
C5
1u
DC-AC separation, RX amplifier
C6
10u/35v
DC-AC separation, RX amplifier
C7
not fitted
C8
10u/30V
Filter and buffer for ringer supply
C9
470u/16v
Vdd supply capacitor
C10
Oscillator fine tuning
C11
10n
TX response shaping, DC-AC separation
C12
TX response shaping (low pass) (not fitted)
C13
10n
TX response shaping, DC-AC separation
C14
100u/25v
Electret handset microphone supply filter
C15
10n
RX Response shaping (not fitted)
C16
100u/25v
Analogue ground filter
C17
10u
DC-AC separation RX Output
CBF1
.../250V
Metering pulses blocking filter (not fitted)
CBF2
..../10V
Metering pulses blocking filter (not fitted)
D1
12V
Gate voltage protection for MOSFET transistor (not fitted)
D2
12V
Ringer voltage clamping, FCI input protection
D3
not fitted
D4
24V
Ringer voltage limitation
D5
1N4148 (or LED)
Piezo ringer discharge (LED for ring indicator)
D6
10V
Surge protection
D7-D9
1N4148
not fitted
D10
1N4148
Keyboard
D11
5v6
Vdd limitation
EC1-EC6
1n
EMC blocking capacitors (not fitted)
IC1
SA252K
Single Chip Telephone
IC2
DF06
Rectifier bridge
J1
Line
Line connector pin selection
J2
Mode
Dialling mode selector
J3
LLC
Line Loss compensation selector
J4
not fitted
J5, J6
(short circuited)
Simulate on-resistance of keypad
LBF1
not fitted
Metering pulses blocking filter, must not be in saturation at Iline max
LBF2
not fitted
Metering pulses blocking filter
LE1
EMC filter (printed on PCB)
LED1
not fitted
n/a
LED2
LED Tone Indicator (SA2532K)
Q1
BSS92
Hook transistor for Mosfet option (not fitted)
Q1A,B
MPSA92
Hook transistor for PNP Darlington option
Q1C
2SA1210
Hook transistor for single PNP option (not fitted)
Q2
MPSA45
Driver transistor for Q1
Q3
BC327
Line current shunt transistor
Q4
BC547B
Ringer driver transistor
Q5
BC557
Current limiter transistor (not fitted)
R1
5.1M
Leakage current limitation
R2
2K2
Ringing impedance
R3
330k
FCI input protection and voltage divider
R4
220k
Voltage divider
AN1500A
26/27
sames
sames
sames
sames
Designator
Part Type
Description
R5
not fitted
R6
not fitted
Line Current sensing resistor for Q5
R7
220k
Pull-up resistor, HS input current limitation
R8
150k
Base resistor for Q2
R9
1M
Base shunt resistor for Q2
R10
10k
Base/gate series resistor for Q1
R11
30
Sensing resistor for DC-mask and Line current
R12
300
Side tone balance bridge resistor
R13
2k7
Side tine network
R14
3k3
Side tone network
R15
330k
Leakage current supply during On-Hook
R16
not fitted
Ringing impedance
R17
100k
Pull-up resistor for Q4
R18
510R
Low pass filter for ringer capacitance
R19
not fitted
Series resistor for LED1
R20
2K2
Filter for electret hanset microphone supply
R21, R23
1K1
Supply for electret microphone
R22
not fitted
TX Frequency response shaping
R24
short circuited
RX Frequency response shaping
R25
short circuited
RX Frequency response shaping
R26
1K
Series resistor for LED2
S1-S17
SPST Keypad
Switches
SW1
SW-HOOK
Telephone Hook switch
VR1
150V
Varistor, surge protection
X1
3.58MHz Ceramic
resonator
Z1
LINE
AMP modular connector
Z2
Handset
AMP modular connector
Z3
Ringer
Piezo ringer connector
Applications based on the SA2531/2 are continuously updated. Ask your local distributor or SAMES sales office for
available papers.
25 Applications
AN1500A
27/27
sames
sames
sames
sames
Disclaimer:
The information contained in this document is confidential and proprietary to South African
Micro-Electronic Systems (Pty) Ltd ("SAMES") and may not be copied or disclosed to a third party, in whole or in
part, without the express written consent of SAMES. The information contained herein is current as of the date of
publication; however, delivery of this document shall not under any circumstances create any implication that the
information contained herein is correct as of any time subsequent to such date. SAMES does not undertake to
inform any recipient of this document of any changes in the information contained herein, and SAMES expressly
reserves the right to make changes in such information, without notification,even if such changes would render
information contained herein inaccurate or incomplete. SAMES makes no representation or warranty that any
circuit designed by reference to the information contained herein, will function without errors and as intended by the
designer
.
South African Micro-Electronic Systems (Pty) Ltd
P O Box 15888,
33 Eland Street,
Lynn East,
Koedoespoort Industrial Area,
0039
Pretoria,
Republic of South Africa,
Republic of South Africa
Tel:
012 333-6021
Tel:
Int +27 12 333-6021
Fax:
012 333-3158
Fax:
Int +27 12 333-3158
Web Site : http://www.sames.co.za
26 Liability and Copyright Statement
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