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Preliminary
Product Description
Ordering Information
Typical Applications
Features
Functional Block Diagram
RF Micro Devices, Inc.
7628 Thorndike Road
Greensboro, NC 27409, USA
Tel (336) 664 1233
Fax (336) 664 0454
http://www.rfmd.com
Optimum Technology Matching Applied
Si BJT
GaAs MESFET
GaAs HBT
Si Bi-CMOS
SiGe HBT
Si CMOS
GN
D
V
CC1
V
CC1
VC
C
B
IAS
2F0
16
1
13
14
15
GND
GND
RFIN
2
3
4
VR
EG
1
VMO
D
E
VR
EG
2
BIAS
G
N
D
GN
D
9
8
7
6
5
RF OUT
RF OUT
RF OUT
12
11
10
RF2162
3V 900MHZ LINEAR AMPLIFIER
3V CDMA/AMPS Cellular Handsets
3V JCDMA/TACS Cellular Handsets
3V TDMA/AMPS Cellular Handsets
Spread-Spectrum Systems
CDPD Portable Data Cards
Portable Battery-Powered Equipment
The RF2162 is a high-power, high-efficiency linear ampli-
fier IC targeting 3V handheld systems. The device is
manufactured on an advanced Gallium Arsenide Hetero-
junction Bipolar Transistor (HBT) process, and has been
designed for use as the final RF amplifier in dual-mode
3 V CDMA/AMPS hand-held digital cellular equipment,
spread-spectrum systems, and other applications in the
800MHz to 960MHz band. The RF2162 has an analog
bias control voltage to maximize efficiency. The device is
self-contained with 50
input and the output can be eas-
ily matched to obtain optimum power, efficiency, and lin-
earity characteristics. The device is packaged in a
compact 4 mmx4mm, 16-pin, leadless chip carrier.
Single 3V Supply
29dBm Linear Output Power
29dB Linear Gain
35% Linear Efficiency
On-board Power Down Mode
800MHz to 960MHz Operation
RF2162
3V 900MHz Linear Amplifier
RF2162 PCBA
Fully Assembled Evaluation Board
2
Rev A17 011011
3.75
3.75
+
1.50 SQ
4.00
4.00
1
0.45
0.28
3.20
1.60
0.75
0.50
12
INDEX AREA 3
1.00
0.90
0.75
0.65
0.05
0.00
NOTES:
5
Package Warpage: 0.05 max.
4
Pins 1 and 9 are fused.
Shaded Pin is Lead 1.
1
Dimension applies to plated terminal and is measured between
0.10 mm and 0.25 mm from terminal tip.
2
The terminal #1 identifier and terminal numbering convention
shall conform to JESD 95-1 SPP-012. Details of terminal #1
identifier are optional, but must be located within the zone
indicated. The identifier may be either a mold or marked
feature.
3
0.80
TYP
2
1
Dimensions in mm.
Package Style: LCC, 16-Pin, 4x4
Preliminary
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RF2162
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Absolute Maximum Ratings
Parameter
Rating
Unit
Supply Voltage (RF off)
+8.0
V
DC
Supply Voltage (P
OUT
31dBm)
+4.5
V
DC
Mode Voltage (V
MODE
)
+3.0
V
DC
Control Voltage (V
PD
)
+3.0
V
DC
Input RF Power
+12
dBm
Operating Case Temperature
-30 to +110
C
Storage Temperature
-30 to +150
C
Moisture Sensitivity
Modified JEDEC Level 2
Parameter
Specification
Unit
Condition
Min.
Typ.
Max.
Overall
T = 25C, V
CC
= 3.4V, Freq=824MHz to
849MHz unless otherwise specified
Usable Frequency Range
800
960
MHz
Typical Frequency Range
824-849
MHz
Linear Gain
28
29
31
dB
Second Harmonic (including
second harmonic trap)
-30
dBc
Max CW Output Power
31.5
dBm
Total Efficiency (AMPS mode)
50
%
Maximum Linear Output Power
(CDMA Modulation)
29
dBm
Total Linear Efficiency
30
35
%
Adjacent Channel Power Rejec-
tion
-46
-44
dBc
ACPR @ 885kHz
-58
-56
dBc
ACPR @1980kHz
Noise Power
-90
-89
dBm
V
CC
= 3.4V; BW = 30kHz; RX Band NF mea-
sure from TX center band to RX center band.
Maximum Linear Output Power
(CDMA Modulation)
29
dBm
V
CC
= 3.0V
Total Efficiency (AMPS mode)
50
%
Max CW Output Power
30
30.5
31
dBm
Total Linear Efficiency
30
36
%
Adjacent Channel Power Rejec-
tion
-46
-44
dBc
ACPR @ 885kHz
-58
-56
dBc
ACPR @ 1980kHz
Input VSWR
<2:1
Output Load VSWR
10:1
No damage.
TDMA
Linear Output Power
30
dBm
Linear ACP
-29
-28
30kHZ offset
Linear ALT CP
-49
-48
60kHZ offset
Efficiency
45
46
O/P= 30dBm
Power Supply
Power Supply Voltage
3.0
3.4
4.5
V
Idle Current
135
200
mA
V
MODE
=0V to 0.5V
V
REG
Current
10
15
mA
Total pins 6 and 7, V
REG
= 2.8V
Turn On/Off time
<100
ns
Total Current (Power down)
10
A
V
PD
= Low
V
REG
"Low" Voltage
0
0.2
V
V
REG
"High" Voltage
2.7
2.8
2.9
V
VMODE Bias Control Voltage
Range
0 to 2.5
V
Caution! ESD sensitive device.
RF Micro Devices believes the furnished information is correct and accurate
at the time of this printing. However, RF Micro Devices reserves the right to
make changes to its products without notice. RF Micro Devices does not
assume responsibility for the use of the described product(s).
Preliminary
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RF2162
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Pin
Function
Description
Interface Schematic
1
GND
Ground connection. Connect to package base ground. This ground
should be isolated from the backside ground contact on top metal layer.
2
GND1
Ground for stage 1. Keep traces physically short and connect immedi-
ately to ground plane for best performance. This ground should be iso-
lated from the backside ground contact on top metal layer.
3
GND1
Same as Pin 2.
4
RF IN
RF input. An external DC blocking capacitor is required if this port is
connected to a DC path to ground or a DC voltage.
5
VREG1
Enable voltage for first stage. When this pin is "low", all circuits are shut
off. When this pin is 2.8V, all circuits are operating normally. V
REG
requires a regulated 2.8V for the amplifier to operate properly over all
specified temperature and voltage ranges. A dropping resistor from a
higher regulated voltage may be used to provide the required 2.8V. A
100pF high frequency bypass capacitor is recommended.
6
VMODE
This is an analog bias current control pin. The range is 0V for minimum
bias to 3.0 for maximum bias.
7
VREG2
Enable voltage for second or output stage. When this pin is "low", all
circuits are shut off. When this pin is 2.8V, all circuits are operating nor-
mally. V
REG
requires a regulated 2.8V for the amplifier to operate prop-
erly over all specified temperature and voltage ranges. A dropping
resistor from a higher regulated voltage may be used to provide the
required 2.8V. A 100pF high frequency bypass capacitor is recom-
mended.
8
GND
Bias circuitry ground. See application schematic.
9
GND
Ground connection. Connect to package base ground. This ground
should be isolated from the backside ground contact on top metal layer.
10
RF OUT
RF output and power supply for the output stage. The bias for the out-
put stage is provided through this pin and pin 13. An external matching
network is required to provide the optimum load impedance; see the
application schematics for details.
11
RF OUT
Same as pin 10.
See pin 10.
12
RF OUT
Same as pin 10.
13
2FO
Harmonic trap. This pin connects to the RF output but is used for pro-
viding a low impedance to the second harmonic of the operating fre-
quency. An inductor or transmission line resonating with an on chip
capacitor at 2fo is required at this pin.
14
VCC BIAS
Power supply for bias circuitry. A 100pF high frequency bypass capaci-
tor is recommended.
15
VCC1
Interstage tuning and bias supply for first stage.
16
VCC1
Interstage tuning and bias supply for first stage.
Pkg
Base
GND
Ground connection. The backside of the package should be soldered to
a top side ground pad which is connected to the ground plane with mul-
tiple vias. The pad should have a short thermal path to the ground
plane.
GND1
RF IN
VCC1
From Bias
Stages
RF OUT
From Bias
Stages
Preliminary
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RF2162
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Application Schematic - US CDMA
330
100 pF
100 pF
100 pF
100 pF
1 k
100 pF
9.1 pF**
5.1 pF**
100 pF
27 nH*
100 pF
10 nF
1 pF
0
TL
1
TL
2
* High Q inductor (i.e., Coilcraft 0805HQ-series).
**High Q capacitors (i.e., Johanson C-series).
16
1
13
14
15
2
3
4
9
8
7
6
5
12
11
10
10 nH
0
15 nH
100 pF
1.8 nH
TL
3
TL
4
1 nH
RF OUT
RF IN
VREG
VMODE
V
CC
2nd Harmonic Trap
Bypassing for V
CC
Interstage tuning for centering
frequency response
To Vary Gain
Matching network for
optimum input return loss
Bypassing for
V
REG1
and V
REG2
Matching network for
optimum load impedance
Bias Return
Preliminary
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RF2162
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Application Schematic - US TDMA
820
C30
100 pF
100 pF
100 pF
1 k
100 pF
12 pF**
4.7 pF**
16 nH*
100 pF
10 nF
1 pF
0
TL
1
TL
2
* L1 is a High Q inductor (i.e.,Coilcraft 0805HQ-series).
**C1 and C14 are High Q capacitors (i.e., Johanson C-series).
16
1
13
14
15
2
3
4
9
8
7
6
5
12
11
10
27 nH
P1-1
1.5 nH
TL
5
TL
7
VREG
VMODE
3.6 pF
1.5 nH
100 pF
TL
3
RF OUT
RF IN
2nd Harmonic Trap
Interstage tuning for
centering frequency response
Bypassing for V
CC
To Vary Gain
Bypassing for
V
REG1
and V
REG2
Bias Return
Matching network for
optimum load
impedance
15 nH
Matching network for
optimum input return loss
100 pF
Preliminary
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RF2162
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Evaluation Board Schematic - US CDMA
(Download Bill of Materials from www.rfmd.com.)
R2
C25
4.7
F
C30
C6
100 pF
C5
100 pF
C27
100 pF
R1
1 k
C13
100 pF
C1**
C14**
C3
100 pF
L1*
C4
100 pF
C28
10 nF
C2
4.7 uF
C17
1 pF
R3
0
CDMA (US)
Board
R2 (
)
C14 (pF)
C30 (pF)
C1 (pF)
L1 (nH)
330
5.1
100
9.1
27
TL
1
TL
2
C10
4.7
F
* L1 is a High Q inductor (i.e., Coilcraft 0805HQ-series).
**C1 and C14 are High Q capacitors
(i.e., Johanson C-series).
16
1
13
14
15
2
3
4
9
8
7
6
5
12
11
10
L4
18 nH
R4
0
L2
15 nH
J1
RF IN
C18
100 pF
P1-1
TL
3
L3
1.8 nH
TL
4
L5
1 nH
J4
RF OUT
2162400B
P1
1
2
P1-1
VCC
GND
P2
1
2
P2-1
VREG
VMODE
P2-2
P2-1
P2-2
TL
4
CDMA (US)
Transmission
Line Length
TL
5
L=15-20 mils
W=14 mils
L=40-45 mils
from L3
W=16 mils
TL
3
L=15 mils
W=16 mils
165 mils
TL
2
TL
1
175 mils
TL
5
Preliminary
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RF2162
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Evaluation Board Schematic - US TDMA
R2
C25
1
F
C30
C6
100 pF
C5
100 pF
C27
100 pF
C13
100 pF
C1**
C14**
L1*
C4
100 pF
C28
10 nF
C2
4.7 uF
C17
1 pF
R3
0
TDMA (US)
Board
R2 (
)
C14 (pF)
C30 (pF)
C1 (pF)
L1 (nH)
820
5.6
56
12
16
TL
1
TL
2
* L1 is a High Q inductor (i.e., Coilcraft 0805HQ-series).
**C1 and C14 are High Q capacitors (i.e., Johanson C-series).
16
1
13
14
15
2
3
4
9
8
7
6
5
12
11
10
L4
27 nH
J1
RF IN
P1-1
TL
4
L3
1.5 nH
TL
5
TL
7
J4
RF OUT
2162401B
P1
1
2
P1-1
VCC
GND
P2
1
2
P2-1
VREG
VMODE
P2-2
C55
3.6 pF
L10
1.5 nH
C3
100 pF
TL
6
TL
3
TL
4
TDMA (US)
Transmission
Line Length
TL
5
L=49 mils
W=16 mils
L=12 mils
W=16 mils
TL
3
135 mils
82 mils
TL
2
TL
1
90 mils
TL
6
L=12 mils
TL
7
L=12 mils
W=14 mils
C18
100 pF
L2
15 nH
R1
1 k
P2-2
R4
0
P2-1
Er = 4.7
H = 14 mils
t = 1 mil
Preliminary
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Evaluation Board Layout - CDMA
Board Size 2.0" x 2.0"
Board Thickness 0.031", Board Material FR-4
Preliminary
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Evaluation Board Layout - TDMA
Preliminary
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RF2162
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